JPH0360210B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a synchronous burst transmission phase control system, and in particular, to a synchronous burst transmission phase control system, which is capable of transmitting SDMA/TDMA via communication satellites.
The present invention relates to a synchronous burst transmission phase control method for establishing and maintaining a TDMA frame between multiple earth stations that communicate using the (space division multiple access/time division multiple access) method. Recently, the SDMA/SS-TDMA system is one of the satellite communication systems formed between multiple earth stations using large-capacity communication satellites, and there are strong expectations that it will adapt to the increasing demand for satellite communication systems. has been done. What is shown in Figure 1 is this SDMA/SS
- A conceptual diagram of the TDMA system, showing the relevant main parts within the communication satellite and their corresponding parts. As an example,
It shows the relative relationship with the earth station in the 4-spot area. For convenience of explanation, only one earth station is set in each spot area on the earth corresponding to the angular spot beam of the communication satellite in FIG. , without any impediment to its generality. In FIG. 1, the communication satellite side is equipped with an onboard receiver 1, an onboard transmitter 2, a matrix switch circuit 2, a matrix switch control circuit 4, and spot beam antennas 5-1 to 5-4. On the side, 4 spot area A,
Earth stations 6-1 to 6-4 corresponding to B, C, and D are provided. Now, earth station 6-1 in spot area A is
It is assumed that this station is a predetermined reference station in this SDMA/SS-TDMA system. When a predetermined TDMA frame is established and in normal operation, the earth stations 6-1 in each spot area A, B, C, and D
4 are received by corresponding spot beam antennas 5-1 to 5-4, frequency-converted by the on-board receiver 1, and input to the matrix switch circuit 3. These received signals are input to the onboard transmitter 2 via the matrix switch circuit 3 whose switching is controlled by the matrix switch control circuit 4, and after being amplified to a predetermined transmission power, the corresponding signals are transmitted to the onboard transmitter 2. Spot beams 7-1 to 4 by spot beam antennas 5-1 to 4
to the corresponding spot areas A, B, C and D. In this case, as an example, the connection mode, , and as shown in FIG. 3 are set for each of the up link and down link, corresponding to the TDMA frame shown in FIG. 2. In addition, a method is used in which communication line switching control is periodically time-divisionally controlled. Note that an example of the TDMA frame shown in FIG.
A synchronization window 105 forms a time slot for time synchronization between the communication satellite side and the reference station side, and a time slot for connecting predetermined stations of participating earth stations 6-1 to 6-4. data windows 106, 107, 108 and 1
It is composed of 09. In addition, in Figure 3, the abbreviation shown as SBA is the spot
means a beam antenna, and therefore:
SBA(1), SBA(2), SBA(3) and SBA(4) correspond to spot beam antennas 5-1, 2, 3 and 4 in FIG. 1, respectively. Third
In an example of the connection mode shown in the figure, the communication lines between the respective spot areas formed in a time-division manner via communication satellites are as follows, corresponding to the connection modes, and. ...A→A, B→B, C→C, D→D ...A→B, B→C, C→D, D→A ...A→C, B→D, C→A, D→ B...A→D, B→A, C→B, D→C In other words, based on each time slot in the TDMA frame of FIG. 2, spot areas A, B, Between C and D, the above-mentioned communication satellite is used as a medium.
SDMA/SS-TDMA system is formed. As mentioned above, establishing and maintaining the TDMA frame is a prerequisite for forming the SDMA/SS-TDMA system. In the case of the conventional TDMA satellite communication system, one or several of the participating earth stations serves as a reference station, and transmits a reference burst signal according to a reference time signal provided within this reference station.
TDMA is transmitted using the cycle corresponding to the TDMA frame as a reference, and this reference burst signal is received by each participating station via a communication satellite.
The time slot standard as a method has been established. However, in the case of the SDMA/SS-TDMA system, switching control of the matrix switch circuit 3 according to a predetermined connection mode is performed in synchronization with a reference time signal built in the matrix switch control circuit 4. Therefore, first, at the reference station,
It is necessary to generate the time reference of the own station in synchronization with the reference time signal of the matrix switch control circuit 4 in the communication satellite. Needless to say, the distance between the communication satellite and the reference station varies slowly over time even when a geostationary satellite is used as the communication satellite, so the synchronization described above means that the reference station The time reference of the reference station itself is constantly controlled by referring to the time reference within the communication satellite so that the signal transmitted according to the time reference of the own station is always in synchronization with the time reference within the communication satellite. It means adjusting. As a countermeasure for this, the SDMA/SS-TDMA system
A synchronous burst transmission phase control method has been considered as a means to establish and maintain a TDMA frame. FIG. 4 is a conceptual system block diagram showing only the relevant parts in the synchronous burst transmission phase control method. In Figure 4,
The reference station on the earth has a synchronous burst generating means 8,
A modulation/transmission system 9, a reception/demodulation system 10, a phase error detection means 11, and a metric pattern phase control means 12 are provided, and within the communication satellite 13, an equivalent gate means 14 is provided. Also, in the diagram, up links and down links are shown.
Equivalent delay lines 15 and 16 are shown for the propagation paths corresponding to the links, respectively. In FIG. 4, the synchronous burst generating means 8 outputs a predetermined synchronous burst signal generated based on the reference time signal in the reference station, and passes through the modulation transmission system 9 and the equivalent delay line 15 to the equivalent The signal is input to the gate means 14. In the equivalent gate means 14, the synchronized burst signal is gated by a synchronization window generated and input based on the reference time signal in the communication satellite, and is sent back to the reference station via the equivalent delay line 16. . The synchronous burst signal is shown in Fig. 5a as an example.
As shown in the commonly used PSK
(Phase Shift Keying) Corresponding to the case where a modulation method is applied to a carrier wave, an unmodulated carrier wave portion (Continuous Wave: (abbreviated as CW) and a predetermined code time series signal (abbreviated as Bit Tining Recovery: BTR) that acts for clock pulse extraction.
It is equipped with a preamble consisting of a part modulated by a preamble, a part modulated by a predetermined synchronization signal (Vnique Word: UW), and a part modulated by a predetermined synchronization signal (Vnique Word: abbreviated as UW). A modulation part using a metric pattern (abbreviated as METRIC) consisting of a predetermined code time series signal to be used continues. When the synchronous burst transmission phase control system is in a normal operating state, the synchronous burst signal returned to the predetermined reference station via the equivalent delay transmission line 16 is as shown in FIG. 5b, as described above. shown,
The second half of the metric pattern is gated off and input to the reception demodulation system 10, with the trailing edge 100 of the synchronization window generated based on the time reference within the communication satellite as the boundary. This synchronous burst signal is transmitted to the reception demodulation system 10 by 2
The unique word (UW), shown in solid line in FIG. A synchronous burst signal formed by the metric pattern (METRIC) is generated and sent to the phase error detection means 11. The phase error detection means 11 detects the trailing edge 100 of the synchronization window in FIG. 5b and the metric pattern (METRIC) of the synchronization burst signal shown in FIG. 5c, which corresponds to this trailing edge 100. The gated trailing edge time position 102 is detected and the metric
The time difference from the reference time position set at the center time position of the pattern (METRIC) is extracted and output as a phase error signal in the synchronous burst transmission phase control method. This phase error signal is sent to the synchronization burst generation means 8 via the metric pattern phase control means 12, and controls the phase of the synchronization burst signal generated by the synchronization burst generation means 8. The subsequent operation is as described above, and the phase error signal output from the phase error detection means 11 is made to be zero by the synchronous burst transmission phase control method formed by the closed loop shown in FIG. , the phase of the synchronization burst signal is controlled and adjusted to establish and maintain a TDMA frame synchronized to a synchronization window within the communications satellite. Note that as a phase control method in the synchronous burst generating means 8, for example, a voltage controlled oscillator may be used, or a frequency divider may be used. For the specific details of the above-mentioned synchronous burst transmission phase control method, please refer to the literature RARAPUANO, N.
SHIMASAKI, “SYNCHRONIZATION OF
EARTH STATIONS TO SATELLITE−
SWITCHED SEQU−ENCES, “AIAA 4TH
COMMUNICATIONS SATE－LLITE
As detailed in SYSTEMS CONFENCE, APRIL 1972, when detecting the time position 102 of the trailing edge of the gate off in the measurement metric pattern (METRIC), the up link and down link are Signal-to-noise ratio and synchronization window trailing edge 100 in a transmission system including
(Due to error factors caused by the waveform characteristics in Figure 5b, an uncertain time region occurs at the time position of the trailing edge of the detected metric pattern (METRIC). When using the two-phase phase modulation method, the metric pattern (METRIC) that is received and demodulated and output is compared for each constituent bit with the corresponding constituent bit of the original metric pattern (METRIC). , detect the match/mismatch of each metric bit corresponding to multiple measurement times, and determine the time position of the trailing edge of the metric pattern (METRIC) by majority logic of the detected data over these measurement times. do,
We aim to improve the functionality of the phase error detection means in the synchronous burst transmission phase control system. However, in the conventional synchronous burst transmission phase control method described above, a method is adopted in which the received and demodulated measurement metric pattern (METRIC) is directly processed by a logic device with a hardware configuration. It has the disadvantage that it lacks the above flexibility and cannot be applied to SDMA/SS-TDMA systems that use a polyphase PSK modulation system of four or more phases. SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks, and to provide a storage means for temporarily storing a metric pattern received and demodulated and input in a predetermined time slot, and a method for comparing the metric pattern with a predetermined reference metric pattern. A means for extracting a weighting coefficient value of each symbol for each measurement time in response to matching; a means for extracting a threshold determination signal for each symbol for an integrated value of the weighting coefficient value over the number of measurements; It is equipped with a flexible processing method that can sufficiently correspond to the transmission characteristics and shape characteristics of the synchronization window, etc., through means for generating a phase error signal by referring to the threshold value judgment signal of
The object of the present invention is to provide a synchronous burst transmission phase control method that is also applicable to PSK modulation methods. The synchronous burst transmission phase control system of the present invention includes a plurality of spot beams corresponding to up links and down links, and connects the line between the up links and down links in a predetermined connection mode. SDMA/SS-TDMA (Space Division
Multiple Access/Satellite Switching Time
For the purpose of establishing and maintaining a TDMA frame between earth stations corresponding to a plurality of different spot areas in a satellite communication line using the SDMA/SS-TDMA method, The reference time within the communication satellite is received by the communication satellite in response to a synchronized burst signal sent from a satellite communication reference station that has a satellite communication line operation control function based on the period corresponding to the TDMA frame. A specific gate signal called a synchronization window is generated as a base.
receiving and inputting the synchronous burst signal that is turned off and sent back to the satellite communication reference station, and in the satellite communication reference station, a predetermined metric pattern forming a part of the synchronous burst signal;
a metric pattern storage means for storing n (an integer greater than 1) number of measurements;
symbol weighting means for comparing and matching the metric pattern read from the pattern storage means with a predetermined reference metric pattern for each symbol, and extracting a predetermined weighting coefficient value for each symbol in accordance with the comparison result; A weighting coefficient accumulating means integrates the weighting coefficient value n times for each symbol, and the integrated value for each symbol by the weighting coefficient accumulating means is compared with a predetermined reference level value, so that the weighting coefficient value is integrated for each symbol. , a predetermined K(1
a symbol threshold determination means for extracting a K-value discrimination value for each symbol, and a symbol length of a time-domain metric pattern gated and passed by the synchronization window with reference to the K-value discrimination value for each symbol; and symbol timing determination means for generating a phase error signal corresponding to the amount of symbol length displacement extracted by comparison with a predetermined reference symbol length, as a phase error detection means. Hereinafter, the present invention will be explained in detail with reference to the drawings. FIG. 6 is a block diagram showing a main part of an embodiment of the time phase error detection means applied to the present invention. As shown in FIG. 6, the time phase error detection means applied to the present invention includes a shift register (p) 17, a shift register (Q) 18,
UW detection circuit 19 and timing signal generation circuit 2
0, AND gate 21, metric pattern storage means 29 consisting of memory (p) 22 and memory (Q) 23, metric pattern weighting consisting of reference metric pattern generation circuit 24 and weighting circuits 25-1 to 25-m. Means 30
, a weighting coefficient accumulation means 31 consisting of accumulation circuits 26-1 to 26-m, a symbol threshold judgment means 32 consisting of threshold judgment circuits 27-1 to 27-m, and a symbol timing judgment circuit 28. . Note that this phase error detection signal corresponds to the case where 4-phase PSK is applied as the modulation method for the carrier wave, and in the figure, m indicates the number of symbols forming the metric pattern. is generally an integer value greater than 1. In FIG. 6, from terminals 51 and 52,
Synchronous burst signals corresponding to the P and Q channels sent from the reception demodulation system are input to the shift registers (p) 17 and 17, respectively.
UW detection circuit 19 and shift register (Q) 1
8 and the UW detection circuit 19. In the shift register (p) 17 and shift register (Q) 18, the metric pattern (METRIC) in the synchronous burst signal of each channel is temporarily stored. Also,
In the UW detection circuit 19, the synchronized burst signals of both P and Q channels inputted from terminals 51 and 52 via the reference clock signal inputted from terminal 53 are converted into a unique word (UW) shown in FIG. ) are detected, and a UW detection signal is output and sent to the timing signal generation circuit 20. The timing signal generation circuit 20 inputs the UW detection signal and a predetermined reference clock signal input from the terminal 53, generates a predetermined first timing signal, and outputs the AND gate 2.
Output to 1. Note that the timing signal generation circuit 2
0, the second, third and fourth timing signals are sent to the integration circuits 26-1 to 26-1, respectively.
m, threshold value judgment circuits 27-1 to 27-m and symbol timing judgment circuit 28, and a predetermined address signal and write/read control signal are sent to memory (p) 22 and memory (Q), respectively. Sent to the 23rd. The AND gate 21 inputs the reference clock signal input from the terminal 53 and the first timing signal sent from the timing signal generation circuit 20, and generates a reference clock signal corresponding to the first timing signal. A signal is output and sent to shift register (p) 17 and shift register (Q) 18. Shift register (p) 17
and in shift register (Q) 18,
The metric patterns (METRIC) of the P and Q channels inputted from terminals 51 and 52 and temporarily stored are sequentially output via the reference clock signal to the memory (p) 22 and the memory (p), respectively. Q) Sent to 23rd.
In the memory (p) 22 and the memory (Q) 23, each channel of P and Q is sent to a predetermined address via the address signal and write control signal sent from the timing signal generation circuit 20, respectively. A metric pattern (METRIC) is stored a predetermined number of times. Thereafter, the metric pattern (METRIC) for a predetermined n number of times stored at a predetermined address in each of the memory (p) 22 and the memory (Q) 23 is generated by the address signal inputted from the timing signal generation circuit 20. and a read control signal, the signals are sequentially read out in the form of parallel signals and sent symbol by symbol to weighting circuits 25-1 to 25-m, respectively. In this case, since the number of symbols of the metric pattern (METRIC) is assumed to be m, m weighting circuits are required. Moreover, the weighting circuit 25-
Integration circuits 26-1 to 26-m connected to 1 to m,
Similarly, m threshold value determination circuits 27-1 to 27-m are required. In the weighting circuits 25-1 to 25-m, the memory (p) and the memory (Q) are
The parallel output of the metric pattern (METRIC) of each channel read from 23 is
Input each bit in the form of a symbol, and
A predetermined reference metric pattern (METRIC) outputted from the reference metric pattern generation circuit 24 is input, the two metric patterns (METRIC) are compared and matched symbol by symbol, and a corresponding one is generated based on the comparison result. predetermined weighting coefficient values are set and extracted, and sent to corresponding integration circuits 26-1 to 26-m. This weighting coefficient value is set, for example, as follows. Now, let the symbols corresponding to the j-th bit of the metric pattern (METRIC) read from the memories (p) 22 and (Q) 23 at the time of the i-th measurement be a _ij , b _ij , and a _ij and b _ij 's,
Let the symbol after comparison with the reference metric pattern (METRIC) be ( _ij , _ij ). In this case, weighting coefficient values α ₀ , α ₁ , α ₂ and α ₃ are set as shown in the table below depending on the appearance rate of 1 or 0 in _ij and _ij .

[Table] As an example, the weighting coefficient values α ₀ , α ₁ , α ₂ and α ₃ shown in the above table are the symbols (a _ij , b _ij )
Correspondingly, the signals are sent to the integration circuits 26-1 to 26-m, respectively, and are added up for each symbol over the number of measurements via the control signal input from the timing signal generation circuit 20. When the number of measurements is n, weighting coefficient values for n times are added. In general, the weighting coefficient addition values output from the integration circuits 26-1 to 26-m are expressed by the following equation in the above example. _o 〓 ⁱ⁼¹ α _k {(a _i,j , b _i,j )} (k=0 to 3) i=1, 2,..., n j=1, 2,..., m Threshold In the determination circuits 27-1 to 27-m, the weighting coefficient sum values outputted for each symbol from the integration circuits 26-1 to 26-m are inputted, and the weighting coefficients are inputted to the determination circuits 27-1 to 27-m, respectively, and the weighting coefficients are inputted to the determination circuits 27-1 to 27-m. , for example, a three-value discrimination value is output from each of the threshold determination circuits 27-1 to 27-m by comparison with a predetermined reference level value. The time positions 103 and 104 of the metric pattern (METRIC) in FIG.
An example of the correspondence between the time position on the metric pattern (METRIC) and the ternary identification value is shown, and the area in the metric pattern in FIG. 5c is divided into three as follows. [1] to [L]th symbol...area [L+1] to [L+p]th symbol...area [L+p+1] to [m]th symbol...area (p is a positive integer) Also, as an example, the weighting coefficient Numeric value α _k (k=0
~3) are set as follows. * _ij matches in comparison verification... _ij →0 * _ij does not match in comparison verification... _ij →1 * _ij matches in comparison verification... _ij →0 * _ij does not match in comparison verification... _ij →1 And, furthermore, the above _ij , Corresponding to the table showing the weighting coefficient value α _k corresponding to the appearance rate of _ij , if * _ij = _ij = 0... α ₀ = 0 * _ij = 0, if _ij = 1... α ₁ = 1 * When _ij = 1, _ij = 0... α ₂ = 2 * When _ij = _ij = 1... α ₃ = 3. In this case, due to the synchronization window shown in FIG. 5b, each symbol in the region of the metric pattern shown in FIG. It is received at
If there is no reception error, the symbols match in comparison, so _ij = _ij =0, that is, α ₀ =0
becomes. Moreover, since each symbol in the area is gated off together and not received, if there is no reception error, the symbols will not match in comparison and verification, so _ij = _ij =1, that is, α ₃ =3. Similarly, for each symbol in the region, in the metric pattern shown in FIG. 5c, symbols located to the left of time position 102 are received without being gated off, so _ij =
b _ij =0, that is, α ₀ =0, and symbols located to the right of time position 102 are gated off and not received, so that _ij = _ij =1, that is, α ₃ =3. From this, the added value of the weighting coefficient value α _k for n measurements is n times the weighting coefficient value above, so the weighted addition value Σα _k of each symbol is
It is expressed by the following formula. Region...Σα _k =0 Region…Σα _k =0 to 3n Region…Σα _k =3n In the above explanation, α _k =0, 3 is used when the noise is negligible, but in general, In wireless communication lines, it is not always possible to ignore the noise that intervenes in the transmission path, so in reality α _k
= 1 or 2 is also possible. In other words, since the weighting coefficient value can range from α _k = 0 to 3, if the three-value discrimination standard levels are L ₁ and L ₂ , then the values in the following range are set for L ₁ and L ₂ . Just choose. 0≦L ₁ <L ₂ ≦3n Of course, it is clear that the above inequality holds true even when L ₁ =0 and L ₂ =3n. Therefore, the correspondence relationship with the ternary discrimination value metric pattern is as follows: Σα _k1 <L ₁ → [1] to [L]th symbol...region L ₁ ≦Σα _k <L ₂ → [L+1] to [L+p ]th symbol...area _L2 ≦ _Σαk →[L+p+1] to [m]th symbol...area. Note that when this is expressed in a general formula, the following formula holds true. _o 〓 ⁱ⁼¹ α _k {(a _i,j , b _i,j )} (k=0 to 3) <L ₁ (j=1, 2,...l) L ₁ ≦ _o 〓 ⁱ⁼¹ α _k {(a _i,j , b _i,j )} (k=0~3) <L ₂ (j=l+1, l+2, ..., l+p) L ₂ ≦ _o 〓 ⁱ⁼¹ α _k {(a _{i ,j} ,b _i,j )}(k=0~3) (j=l+p+1,l+p+2,...m) That is, the time positions 103 and 104 in FIG. like,
l in metric pattern (METRIC)
This corresponds to the boundary position between the th symbol and the (l+1)th symbol and the boundary position between the (l+p)th symbol and the (l+p+1)th symbol. As described above, for each symbol, the m three-value identification values output from the corresponding threshold judgment circuits 27-1 to 27-m are input to the symbol timing judgment circuit 28, and these m By arithmetic processing that refers to binary identification values, metrics
The time position gated off by the synchronization window in the pattern (METRIC) (Figure 5c)
102) in FIG. 5c, the symbol lengths corresponding to time positions 101 and 102 in FIG. The voltage is output as a phase error voltage in the synchronous burst transmission phase control method. This phase error voltage is
The metric pattern phase control means 12 shown in FIG. 4 controls and adjusts the phase of the synchronous burst signal generated in the synchronous burst generating means 8, and transmits the synchronous burst so that the phase error voltage becomes zero. The phase control method operates so that the time position corresponding to the reference symbol length of the metric pattern (METRIC) follows the time position 102 of the gate-off trailing edge of the constant synchronization window (see Figure 5b). , the transmission phase of the synchronous burst signal is held at a predetermined phase, and the SDMA/SS-
As described above, the TDMA frame in the TDMA system is established and maintained. 7a, b, c, d, e and f respectively show the synchronization burst signal, the logic processing process of the metric pattern, the first timing signal, the second timing signal, the third timing signal, and the third timing signal. 4 is an example of a timing chart showing timing signals of FIG. Note that in the timing chart showing the processing steps of the logical processing in FIG. 7b, the logical processing indicated by . . . indicates the following processing contents. ...Write processing to memory...Metric pattern readout processing from memory...Comparison matching and weighting processing...Arithmetic processing...Threshold judgment processing...Symbol timing judgment processing The first timing signal shown in FIG. 7c is ,
Contained in the synchronous burst signal shown in Figure 7a
The timing generation circuit 20 uses the UW signal as a reference.
This corresponds to the writing timing of the metric pattern included in the synchronized burst signal shown in FIG. (See Figure 7b). The second timing signal shown in FIG. 7d is:
The timing signal generated at the timing after reading the metric pattern written based on the first timing signal and the comparison and matching and weighting processing is used to start the next calculation process.
The next arithmetic processing is started based on this second timing signal (see FIG. 7b-//). a metric pattern readout process performed via the first and second timing signals;
Logic processing operations including comparison matching, weighting processing, addition processing, etc. are repeated n times of measurement, and for each symbol, the arithmetic circuit 26 performs n
times are added. The third timing signal shown in FIG. 7e is:
This is a timing signal generated at the timing after the integration process for n measurements, and corresponds to the start timing of the next threshold value judgment process, and the next threshold judgment process is performed based on this third timing signal. The process is executed (see FIG. 7b). The fourth timing signal shown in FIG. 7f is:
A timing signal generated after the threshold value judgment based on the third timing signal.
This corresponds to the start timing of timing determination, and symbol timing determination processing is performed based on this fourth timing signal (see FIG. 7b). As described above with reference to FIGS. 7a, b, c, d, e, and f, the operation of the embodiment has been explained in detail. In the present invention, after the metric pattern is once stored in the memory, As shown in FIG. 7b, the logic for writing to memory, reading metric patterns from memory, comparing and matching and weighting, arithmetic processing, threshold judgment processing, and symbol timing judgment processing, etc. Processing is executed. In the above explanation, as an example, the logical processing from reading out the metric pattern to calculation is performed every time a synchronization burst signal arrives.
We have explained the case where it is executed every time, but of course, once all n times are stored in memory,
Again, it is also possible to execute n integration processes at once. Note that in the above explanation, the modulation method is SDMA/SS-4, which uses a four-phase PSK modulation method.
Although the case where the present invention is applied to the TDMA system has been described, it goes without saying that the present invention can also be effectively applied to cases where a polyphase PSK modulation system of four or more phases is generally used. Furthermore, since the present invention performs logical processing sequentially after storing metric patterns in a flat memory, the process of reading and processing metric patterns can be performed independently of the TDMA frame and TDMA symbol rate. This part of the process can be processed at the speed of a microprocessor. When a microprocessor is applied to the present invention, all of the aforementioned m weighting circuits, m threshold value judgment circuits, and symbol timing judgment circuits are realized by software using one microprocessor. I can also do things. As explained in detail above, the present invention
Applied to satellite communication systems using the SDMA/SS-TDMA system, phase errors are caused by uncertainties when measuring metric pattern displacement due to transmission characteristics in transmission paths via communication satellites and waveform characteristics of synchronization windows. In addition to being able to significantly improve detection characteristic deterioration, the present invention can also be effectively applied to the SDMA/SS-TDMA system that uses a polyphase PSK modulation system or the like as a modulation system for carrier waves. In addition, by storing metric patterns in a flat memory and processing them, a microprocessor can be easily applied, making it possible to downsize the device and economically changing parameters. be.

[Brief explanation of drawings]

Figure 1 is a system conceptual diagram of the SDMA/SS-TDMA system, Figure 2 is a diagram showing an example of a TDMA frame, Figure 3 is a diagram showing an example of a connection mode, and Figure 4 is a diagram of the synchronous burst transmission phase control system. A conceptual system block diagram; FIGS. 5a, b, and c are conceptual waveform diagrams of the metric pattern for transmission, the synchronization window, and the metric pattern during reception demodulation, respectively; FIG. 6 is applied to the present invention. A block diagram showing the main parts of an embodiment of the phase error detection means,
7a, b, c, d, e and f are timing charts showing the synchronous burst signal, the logic value processing process of the metric pattern, the first, second, third and fourth timing signals, respectively; FIG. It is a diagram. In the figure, 1...onboard receiver, 2...onboard transmitter, 3...
Matrix switch circuit, 4...Matrix
Switch circuit control transfer, 5-1 to 4...Spot beam antenna, 6-1 to 4...Earth station,
7-1 to 4...Spot beam, 8...Synchronization burst generation means, 9...Modulation transmission system, 10...Reception demodulation system, 11...Phase error detection means, 12...
Metric pattern phase control means, 13... Communication satellite, 14... Equivalent gate means, 15, 16...
...Equivalent delay line, 17...Shift register (p), 18...Shift register (Q), 19...
...UW detection circuit, 20...Timing signal generation circuit, 21...AND gate, 22...Memory (p), 23...Memory (Q), 24...Reference metric pattern generation circuit, 25-1 to m ... Weighting circuit, 26-1~m ... Integration circuit, 27-
1 to m...Threshold judgment circuit, 28...Symbol/timing judgment circuit, 29...Metric/
pattern storage means, 30... metric pattern weighting means, 31... weighting coefficient accumulation means, 3
2...Symbol threshold determination means.

Claims (1)

[Claims] 1. A plurality of spot beams corresponding to an up link and a down link are provided, and the line connection between the up ring and the down ring is switched and controlled via a predetermined connection mode. SDMA/SS-TDMA (Space Division
Multiple Access/Satellite Switching Time
For the purpose of establishing and maintaining a TDMA frame between earth stations corresponding to a plurality of different spot areas in a satellite communication line based on the (Division Multiple Access) system, the
The above-mentioned satellite communication standard station, which has the operation control function of satellite communication lines using the SDMA/SS-TDMA method,
A specific gate signal called a synchronization window is received by the communication satellite in response to a synchronization burst signal transmitted based on a period corresponding to a TDMA frame, and is generated based on the reference time within the communication satellite. The synchronous burst signal that has been gated off and returned to the satellite communication reference station is received and input, and within the satellite communication reference station, a predetermined metric pattern forming a part of the synchronous burst signal is calculated by n( (Integer greater than 1) Metrics to be stored for the number of measurements.
A pattern storage means compares and matches the metric pattern read from the metric pattern storage means with a predetermined reference metric pattern for each symbol, and sets a predetermined weighting coefficient value for each symbol in accordance with the comparison result. symbol weighting means for extracting the weighting coefficient; weighting coefficient accumulating means for integrating the weighting coefficient value n times for each symbol; and comparing and collating the integrated value for each symbol by the weighting coefficient accumulating means with a predetermined reference level value. symbol threshold determination means for extracting, for each symbol, a predetermined K-value identification value (an integer greater than 1) associated with a reception threshold level; With reference to this, the symbol length of the time domain metric pattern gated and passed by the synchronization window is measured, and a phase error signal is generated corresponding to the symbol length displacement amount extracted by comparison with a predetermined reference symbol length. symbol timing determination means for generating
A synchronous burst transmission phase control system, characterized in that it is provided as a phase error detection means.