JPH0360161A - Insulated gate type field effect transistor and its manufacture - Google Patents

Abstract

PURPOSE:To reduce current drift and obtain an InP MISFET of high performance, by constituting a gate insulating film of a compound film, and constituting only the operating layer side of an oxide film or a nitride film containing no silicon. CONSTITUTION:An N<+> type InP layer 2, as an operating layer, whose impurity concentration is 1.5X10<17>/cm<-3> is deposited on an InP substrate 1 by vapor phase epitaxy. On the surface of the layer 2, an AuGe/Ni layer is formed by vapor deposition method, and subjected to alloying process by heating; then source drain electrodes 3, 4 are formed by patterning. The substrate is transferred in a reaction vessel, and nitrogen (N2) radical and phosphine (PH3) are introduced, thereby depositing a P-N film as a gate insulating film. At this time, the substrate temperature is kept at 30 deg.C. Further, an aluminum film is vapor-deposited and patterned, thereby forming a gate electrode 6.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to an insulated gate field effect transistor and a method for manufacturing the same, and particularly relates to an insulated gate field effect transistor using an indium phosphide layer (InP) as an active layer. This invention relates to improvements in the gate insulating film of insulated gate field effect transistors.

(Prior art) Conventionally, insulated gate field effect transistors (MISFETs) using compound semiconductors have been most actively researched and developed using GaAs-based materials. Research on MISFETs using InP-based materials is becoming more active with the aim of improving the performance and performance of MISFETs.

InP has a higher electron saturation velocity and higher thermal conductivity than GaAs, so it is attracting attention as a material for electronic microwave semiconductor devices that can obtain higher frequency operation and higher output than GaAs.

By the way, unlike GaAs, InP has a small reverse leakage current and it is difficult to form a good Schottky junction. Therefore, as a field effect transistor, instead of an MES type with a Schottky junction as a gate, a metal/insulating film/metal/insulating film/field effect transistor is used.
Development of MIS type FETs using semiconductor junctions as gates has been progressing.

However, one of the biggest problems in realizing an InPMISFET is that a so-called current drift occurs in which the drain current changes over time.

The cause of such current drift is that the insulating film and In
It is thought that this is because the density of electrons traveling through the channel changes over time due to charging and discharging of electrons to the interface state existing at the interface with P.

Therefore, in order to reduce current drift, it is necessary to
It is necessary to reduce the interface state density at the interface with nP as much as possible.

For this reason, conventionally, various insulating film formation methods such as thermal oxidation, anodic oxidation, chemical vapor deposition (CVD), and photo-CVD have been used to form various insulating films such as silicon oxide films and silicon nitride films. attempts have been made to form

InP is a binary compound, and the vapor pressure of the component element phosphorus is high, so if an insulating film is deposited at a temperature of 400°C or higher, the phosphorus dissociates rapidly, causing defects at the InP/insulating film interface. It has been reported that this leads to the generation of high-density interface states. Therefore,
In order to form a good insulating film on the InP surface, it is considered necessary to form it at a low temperature of 300° C. or lower. In fact, it has been proposed that relatively good interface characteristics can be obtained using a silicon oxide film or a silicon nitride film formed by a CVD method that allows deposition at low temperatures.

Furthermore, it has recently been discovered that it is possible to suppress the dissociation of phosphorus from a 1nP substrate by more actively introducing phosphorus into the reaction vessel during the deposition of an insulating film. From the capacitance-voltage characteristics, for example, the interface state density is 5 x 10 ++.

Good values of / cJ CV or less have been reported.

However, InPMISFE using this film as the gate insulating film
When we made a prototype T, the drain current increased to about 10% in 30 minutes.
% fluctuation and could not be put to practical use.

Even though the interface state density is reduced in this way, M
Drain current drift occurs in ISFETs. Although the reason for this is not yet clear, it is presumed that this is because the time constants for charging and discharging electrons via the interface states are widely distributed from large to small time constants. In other words, the interface states contributing to the 7It flow drift are:
These levels have a large charging/discharging time constant of several seconds to several tens of seconds, but these levels are
Since the time constant is too large compared to the level subjected to IJ, it is considered that the level density cannot be calculated by the conventional method of estimating the level density from the capacitance-voltage characteristic curve.

From this point of view, the conventional capacitance-voltage characteristics are unsatisfactory for interface evaluation, and for this reason, InPMI 5FET
Since the relationship between the drain current drift and the insulating film/InPIn characteristics remained unclear, it was not possible to find an effective countermeasure against the drain current drift.

(Problem to be solved by the invention) In this way, the conventional I n P M I S F E
It has not been possible to eliminate the drain current drift of T, and this has been a problem that has hindered the practical application of I n PMI S FET.

The present invention has been made in view of the above-mentioned circumstances, and aims to reduce current drift and provide a high-performance 1 n P M 15 FE.
The purpose is to provide T.

[Structure of the invention]

(Means for Solving the Problems) Therefore, in the present invention, in an insulated gate field effect transistor having an indium phosphide layer as an active layer, the gate insulating film forming the interface between the gate insulating film and the active layer is made of constituent elements. As such, it is made of an oxide film or a nitride film that does not contain silicon.

Preferably, the gate insulating film is made of a composite film, and only the active layer side that forms the interface with the active layer is made of an insulating film made of an oxide film or a nitride film that does not contain silicon as a constituent element.

In addition, in the method of the present invention, an oxide film or a nitride film that does not contain silicon as a constituent element is heated at a substrate temperature of 250 to 400
The temperature is maintained at ℃ while depositing.

In addition, in the method of the present invention, after depositing an oxide film or nitride film that does not contain silicon as a constituent element,
A heat treatment process at 00°C is added.

(Function) As a result of various experiments, the present inventors discovered that in transistors with large current drift, crystalline protrusions are formed on the insulating material side of the interface between the gate insulating film and the active layer.
We hypothesized that this may be the cause of current drift.

As a result of repeated research, we have found that by forming the gate insulating film with an oxide film or nitride film that does not contain silicon, the interface between the gate insulating film and the active layer forms a smooth interface without crystalline protrusions. We discovered that it is possible to obtain a surface without current drift.

Considering this result, we can think of the following.

For example, when depositing a silicon oxide film on the In2 surface by the CVD method, first a natural oxide film of I
An nPO4 layer and an In2Q3 layer are formed thereon. If silicon atoms exist in this state, silicon will form the InPO4 layer and the In20 layer above it at the beginning of the reaction.
It reacts with oxygen in the three layers to form silicon oxide, leaving In and P at the interface. A silicon oxide layer is then formed on this, and since In has the property of diffusing in the oxide film, it diffuses into the silicon oxide layer. On the other hand, it is thought that P remains at the interface and solid-phase growth occurs with the InP substrate crystal as a core, forming crystalline protrusions containing P as a constituent element.

Therefore, it is considered that by using an insulating film that does not contain silicon as a constituent element, it is possible to prevent the natural oxide film from being reduced and to prevent the formation of crystalline protrusions.

In addition, good performance can also be achieved by configuring the gate insulating film as a composite film, and configuring only the active layer side that forms the interface with the active layer with an insulating film made of an oxide film or nitride film that does not contain silicon as a constituent element. While an interface can be formed, the material for the gate insulating film on the gate electrode side can be freely selected.

Preferably, when depositing an oxide film or nitride film that does not contain silicon as the gate insulating film, an extremely good interface could be obtained by performing heat treatment at 250 to 400° C. during or after the deposition.

Here, below 250° C., the unevenness of the interface becomes large, while above 400° C., the film quality deteriorates and the dissociation of InP becomes severe, making it difficult to obtain a good interface.

Furthermore, even if the material is deposited at 250° C. or lower and has many irregularities at the interface, the irregularities disappear by subsequent heat treatment, making it possible to form a good interface.

More preferably, this temperature is between 300°C and 400°C.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an example of the present invention
It is a sectional view showing ET.

This InPMISFET is characterized in that phosphorous nitride (PN) is used as the gate insulating film 5.

In other words, InPMISFET is a semi-insulating InP
An n-shaped InP layer 2 with a film thickness of 0.2 μm and an impurity concentration of 1.5×10 17 /cm −3 is laminated on the substrate 1 as an active layer, and a source layer 2 is arranged at a distance on this surface.
There is a film thickness of 600 mm between the AuGe/Ni layer as the drain electrodes 3 and 4 and these source/drain electrodes 3°4.
It consists of a gate electrode 6 made of an aluminum (Al) layer formed through a gate insulating film 5 made of a PN layer of A.

Next, a method for manufacturing this InPMISFET will be explained.

First, an active layer with a film thickness of 0.2 μm and an impurity concentration of 1.5× is formed on an InP substrate 1 by vapor phase epitaxial growth.
An n-shaped InP layer 2 of 10177cIll-3 is deposited.

Thereafter, an AuGe/Ni layer is formed on the surface of this n-skewer type InP layer 2 by vapor deposition, heated and alloyed, and then patterned by photolithography to form source and drain layers. Form electrode 3.4.

Further, this substrate was transferred to a reaction vessel, nitrogen (N2) radicals and phosphine (PH3) were introduced into the reaction vessel, and a PN film was deposited to a thickness of 600 mm as a gate insulating film. At this time, the substrate temperature was maintained at 30°C.

Thereafter, an aluminum film is further deposited and patterned by photolithography to form the gate electrode 6.

As a result of measuring the interface between the n-shaped InP layer 2 of the InPMISFET thus formed and the PN layer serving as the gate insulating film 5 on an atomic scale, a smooth interface was obtained as shown in FIG. I understand that.

For comparison, FIG. 5 shows the state of the interface between the n-type InP layer and the silicon oxide layer. Here, it can be seen that many crystalline protrusions are formed at the interface, resulting in a highly uneven film. A comparison between FIG. 2 and FIG. 5 also shows that the interface between the gate insulating film and the active layer of the InPMI 5FET according to the example of the present invention is extremely smooth and excellent.

Furthermore, as a result of measuring the drain current drift of this InPMISFET, as shown by curve a in FIG. 3, the change in current was within 3% over a measurement time of 30 minutes. Here, the voltage between the source and drain electrodes is 5V, and the voltage between the gate and drain electrodes is 5V.
The time change in the drain current when the voltage between the drain electrodes is changed from 0 to -4V at time tQ is normalized by the initial value of the drain current.

For comparison, FIG. 3 shows the curves obtained by performing similar measurements on an InPMISFET in which the gate insulating film was made of a silicon oxide film and other configurations were shown in FIG. In this case, a 9% drift occurs in 30 minutes.

From these comparisons, it is clear that InPMI 5F of the present invention example
According to ET, it can be seen that current drift is significantly reduced.

In the above example, the substrate temperature was set at 300°C when forming the PN layer, but after the deposition at room temperature, the temperature was set at 250-400°C.
By annealing at .degree. C., sufficient interfacial properties can be obtained even during deposition at room temperature.

Further, in the above embodiment, the gate insulating film was composed of a single PN layer, but as a second embodiment, as shown in FIG.
After forming a PN layer 5a of about 100%, a layer of 300%
A composite film may be used, such as forming a silicon nitride film 5b as thick as a human being to have a two-layer structure. At this time, the second gate insulating film is not limited to a silicon nitride film, and can be selected as appropriate as necessary. Note that other parts were formed in exactly the same manner as in the first embodiment. Note that the same parts are given the same symbols.

Furthermore, although the gate insulating film is formed of a PN layer in the above embodiment, similar effects can be obtained by using other oxides or nitrides that do not contain silicon, such as InPxoy or AI203.

Furthermore, if the amount of silicon as an impurity is 0.01% or less, a good interface can be obtained without forming protrusions as shown in FIG.

In addition, in addition to I n P M I S F E T
nGaPMISFET, InAsPMISFET, etc. I
It is applicable to nP-based insulated gate field effect transistors.

In addition, the present invention can be implemented with various modifications without departing from the spirit thereof.

〔effect〕

As explained above, according to the present invention, by forming the groove bottom of the interface between the gate insulating film and the active layer with an oxide film or nitride film that does not contain silicon, an I n P film with good characteristics and no current drift is formed. It becomes possible to obtain an MI S FET.

[Brief explanation of drawings]

FIG. 1 shows an example of the present invention.
A cross-sectional view showing E T, FIG. 2 is the same 1 n P M I
A diagram showing a lattice image of the PN/I n P interface of S F ET, FIG.
A comparison diagram showing the time change of the gate current of SFET and a conventional InPMISFET. FIG. 4 is a diagram showing the InPMISFET of the second embodiment of the present invention. FIG. 5 is a diagram showing the gate current of the conventional InPMISFET. FIG. 3 is a diagram showing a lattice image of a silicon-InP interface. DESCRIPTION OF SYMBOLS 1...Semi-insulating 1nP substrate, 2...N medium-sized InP layer, 3...Drain electrode, 4...Source electrode, 5...
・Gate insulating film (PN layer), 6...gate electrode, 5a
...first gate insulating film (PN layer), 5b...second
gate insulating film (silicon nitride layer). Figure 1 Figure 2--1- Figure 3 Figure 5

Claims (3)

[Claims] (1) In an insulated gate field effect transistor whose active layer is a layer mainly composed of indium phosphide, the insulating film forming the interface between the gate insulating film and the active layer is an oxide film that does not contain silicon as a constituent element. Or an insulated gate field effect transistor characterized by a nitride film. (2) An active layer forming step in which an active layer containing indium phosphide as a main component is formed on a semi-insulating substrate, and a source/drain electrode forming step in which source/drain electrodes are formed in predetermined regions on the active layer. , a gate insulating film forming step of depositing an oxide film or nitride film that does not contain silicon as a constituent element while maintaining the substrate temperature at 250°C to 400°C, and a gate electrode forming step of forming a gate electrode on the gate insulating film. A method for manufacturing an insulated gate field effect transistor, comprising: (3) An active layer forming step of forming an active layer mainly composed of indium phosphide on a semi-insulating substrate, and a source/drain electrode forming process of forming source/drain electrodes in predetermined regions on the active layer. , a gate insulating film forming step of depositing an oxide film or nitride film that does not contain silicon as a constituent element; a heating step of heating the substrate to 250°C to 400°C; and a gate forming step of forming a gate electrode on the gate insulating film. 1. A method for manufacturing an insulated gate field effect transistor, comprising the step of forming an electrode.