JPH0360133A - Die bonding - Google Patents
Die bondingInfo
- Publication number
- JPH0360133A JPH0360133A JP19577989A JP19577989A JPH0360133A JP H0360133 A JPH0360133 A JP H0360133A JP 19577989 A JP19577989 A JP 19577989A JP 19577989 A JP19577989 A JP 19577989A JP H0360133 A JPH0360133 A JP H0360133A
- Authority
- JP
- Japan
- Prior art keywords
- bonding pad
- pad
- bonding
- walls
- bonding agent
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 34
- 238000000034 method Methods 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 230000002093 peripheral effect Effects 0.000 abstract description 7
- 239000007767 bonding agent Substances 0.000 abstract 5
- 239000000853 adhesive Substances 0.000 description 22
- 230000001070 adhesive effect Effects 0.000 description 22
- 238000010586 diagram Methods 0.000 description 6
- 239000012790 adhesive layer Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000011521 glass Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000003973 paint Substances 0.000 description 2
- 238000003892 spreading Methods 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- -1 for example Substances 0.000 description 1
- 238000012966 insertion method Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
Landscapes
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体素子を基板に装着するためのダイボン
ディング方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a die bonding method for attaching a semiconductor element to a substrate.
ＩＣ製造工程では、半導体チップがリードフレーム上に
設けたボンディングパッドに接着剤等で接合（ダイボン
ディング）される。また近年、半導体素子の高集積化、
小型化に伴い、プリント基板への半導体素子の実装方式
が従来のＤＩＰ等を用いるピン挿入方式から表面実装方
式へと変化しつつあり、この場合は、フラットバック（
Ｆ Ｐ）やチップキャリヤ（ＣＣ）等の半導体素子がプ
リント基板へ同様にグイボンディングされる。In the IC manufacturing process, a semiconductor chip is bonded (die bonding) to a bonding pad provided on a lead frame using an adhesive or the like. In addition, in recent years, semiconductor devices have become highly integrated,
With miniaturization, the mounting method of semiconductor elements on printed circuit boards is changing from the conventional pin insertion method using DIP etc. to the surface mounting method.
Semiconductor elements such as FP) and chip carriers (CC) are similarly bonded to the printed circuit board.
従来から、これらのダイボンディング工程では素子裏面
の接着剤層から導電性の接着剤がはみ出して半導体素子
の電極をその周辺回路に付着し、これらをショートさせ
るという解決を要する課題があった。そのため、このよ
うなトラブルを防止すべく接着剤の塗布制御（印刷法、
スタンプ法等）が行われている。また、チップをダイボ
ンディングする位置に複数の突子を形成したり（特開昭
６３−２５８０２６号）、ダイボンディング位置の近傍
に溝を形成したり（特開昭６３−９２０４８号）するこ
とも提案されているが、接着剤の粘度、外気温管理等の
難しい事項があるため、十分な成果を挙げ得ない場合が
ある。Conventionally, in these die bonding processes, there has been a problem that the conductive adhesive protrudes from the adhesive layer on the back of the device, attaching the electrodes of the semiconductor device to its peripheral circuits, and shorting them. Therefore, in order to prevent such troubles, adhesive application control (printing method,
stamp law, etc.) are being implemented. It is also possible to form a plurality of protrusions at the position where the chip is die-bonded (Japanese Patent Laid-Open No. 63-258026) or to form a groove near the die-bonding position (Japanese Patent Laid-Open No. 63-92048). Although these methods have been proposed, they may not produce sufficient results due to difficult issues such as adhesive viscosity and outside temperature control.
そこで本発明は、基板のパターン構造に工夫を加えるこ
とにより上記の課題を解決し、半導体素子の電極または
その周辺回路への接着剤の回り込みを生じないようにし
たダイボンディング方法を提供することを目的とする。SUMMARY OF THE INVENTION Therefore, the present invention aims to solve the above-mentioned problems by adding innovations to the pattern structure of the substrate, and to provide a die bonding method that prevents the adhesive from flowing around to the electrodes of the semiconductor element or its peripheral circuits. purpose.
上記の課題を解決するために、本発明に係るダイボンデ
ィング方法では、基板上に形成されてその上に半導体素
子を接合するボンディングパッドの周囲に、このボンデ
ィングパッドを実効的に囲む断面が凸形状の段差を形成
することを特徴とする。In order to solve the above problems, in the die bonding method according to the present invention, a cross section that effectively surrounds a bonding pad formed on a substrate and on which a semiconductor element is bonded has a convex shape. It is characterized by forming a step.
この段差はボンディングパッドの周囲に設けた壁または
溝、あるいはその両方を含むものであってもよい。この
壁は、ボンディングパッドの周縁部を直接立ち上げたも
のでもよいし、あるいはその周縁部から一定の間隙を隔
ててボンディングパッドを囲む枠状のものであってもよ
い。また、必ずしもボンディングパッドの全周を囲む必
要はなく、本発明の目的を達成できる限り実効的に囲ん
でいれば十分であり、一部に切り目があっても構わない
。さらに、この壁はボンディングパッドと共に、または
別々に、例えば厚膜印刷法により形成することができる
。この壁の高さをボンディングパッドの厚さの整数倍に
すれば、ボンディングパッドと壁とを共に厚膜印刷法等
で形成する場合に好都合である。さらに、ボンディング
パッド面の一部を上記の壁と同じ高さに突出させ、この
突出面と壁とに半導体素子−を差し渡す形でダイボンデ
ィングするようにしてもよい。上記の溝としては、上記
のボンディングパッドの周縁部とこれを囲む枠との間隙
部分がこの溝に相当する。さらにこの間隙の底部となる
基板面（セラミック基板の場合はグリーンシート面）に
あらかじめ例えば印加加工（コインニング）により、例
えば■溝を形成しておいてもよい。The step may include walls and/or grooves around the bonding pad. This wall may be formed by directly standing up from the periphery of the bonding pad, or may be a frame-shaped wall that surrounds the bonding pad with a predetermined gap from the periphery. Further, it is not necessarily necessary to surround the entire circumference of the bonding pad, but it is sufficient to surround it effectively as long as the object of the present invention can be achieved, and there may be a cut in a part. Furthermore, this wall can be formed together with the bonding pads or separately, for example by thick film printing methods. Setting the height of this wall to an integral multiple of the thickness of the bonding pad is advantageous when both the bonding pad and the wall are formed by a thick film printing method or the like. Furthermore, a part of the bonding pad surface may be made to protrude to the same height as the above-mentioned wall, and die bonding may be performed in such a manner that the semiconductor element is passed between this protruding surface and the wall. The groove corresponds to the gap between the peripheral edge of the bonding pad and the frame surrounding it. Further, a groove may be formed in advance on the substrate surface (green sheet surface in the case of a ceramic substrate), which is the bottom of this gap, by, for example, coining.
本発明に係るダイボンディング方法においては、段差に
よってボンディングパッドの周囲に形成される溝状の部
分は、半導体素子の裏面の接着剤層からはみ出した接着
剤を滞留させる貯留池として作用し、段差の壁の部分は
この接着剤の流れをせき止めて基板上へ広がることを防
止する作用をする。また、ボンディングパッド面の一部
を突出させ、この突出面と壁とに半導体素子を差し渡す
形でダイボンディングする場合は、接着剤の厚みが均一
化されると共に半導体素子表面への接着剤の回り込みを
防止できる。In the die bonding method according to the present invention, the groove-shaped portion formed around the bonding pad by the step acts as a reservoir for retaining the adhesive that has protruded from the adhesive layer on the back side of the semiconductor element, and The wall portion acts to block the flow of this adhesive and prevent it from spreading onto the substrate. In addition, when die bonding is performed by making a part of the bonding pad surface protrude and passing the semiconductor element between this protruding surface and the wall, the thickness of the adhesive becomes uniform and the adhesive is not applied to the surface of the semiconductor element. Can prevent wraparound.
以下、本発明のいくつかの実施例を添付図面に従って説
明する。なお図面の説明上、各実施例の対応図面には同
一符号を付して重複する説明を省略する。Hereinafter, some embodiments of the present invention will be described with reference to the accompanying drawings. In addition, for the sake of explanation of the drawings, the same reference numerals are given to the corresponding drawings of each embodiment, and redundant explanation will be omitted.
第１図は、第１の実施例の係るダイボンディング方法に
より製造された基板１０の一部を示すものであり、同図
（ａ）はその平面図、同図（ｂ）は断面図、同図（ｃ）
および（ｄ）はボンディングパッド上に異なる半導体素
子を接着剤で接着した様子を示す断面図である。図示の
通り、ボンディングパッド１の周縁から一定の間隙を隔
ててこれを囲む段差としての枠状の壁２を有する。両者
の厚さは同一で、本実施例ではこのボンディングパッド
１と枠状の壁２を１回の厚膜印刷で同時に形成している
。これによれば、半導体素子６１゜６２の裏面から流出
した接着剤５はボンディングパッド１と枠状の壁２とに
囲まれた溝部に溜り、また、枠状の壁２にせき止められ
てその内部に止まる。FIG. 1 shows a part of a substrate 10 manufactured by the die bonding method according to the first embodiment. FIG. 1(a) is a plan view thereof, FIG. 1(b) is a sectional view, and Figure (c)
and (d) is a cross-sectional view showing how different semiconductor elements are bonded onto bonding pads with an adhesive. As shown in the figure, there is a frame-shaped wall 2 as a step that surrounds the periphery of the bonding pad 1 with a predetermined gap therebetween. Both have the same thickness, and in this embodiment, the bonding pad 1 and the frame-shaped wall 2 are simultaneously formed by one thick film printing. According to this, the adhesive 5 that has flowed out from the back surface of the semiconductor elements 61 and 62 accumulates in the groove surrounded by the bonding pad 1 and the frame-shaped wall 2, and is also blocked by the frame-shaped wall 2 and stored inside the groove. Stops at.
第２図は第２の実施例に係るものを示し、同図（ａ）は
平面図、同図（ｂ）は断面図、同図（ｃ）、（ｄ）は半
導体素子を実装した状態を示す図である。図示の通り、
この実施例では壁２をボンディングパッド１の周縁部か
ら直接立ち上げている。この場合は、まず第１回目の厚
膜印刷でボンディングパッド１が形成され、第２回目で
このボンディングパッド１の周縁部上に重ねて枠状に印
刷し壁２が形成される。本実施例では第１実施例と異な
り、周囲に壁２を有するボンディングパッド１の全体が
貯留池となって、流出した接着剤５を内部に止める作用
をする。また、同図（ｄ）の如く半導体素子６２が縦長
のもの（カンチレバー状のもの）である場合は、その一
部が壁２の頂面に載る形となり、その姿勢の安定性は上
記の第１実施例におけるものより優れる。Figure 2 shows the second embodiment, in which (a) is a plan view, (b) is a cross-sectional view, and (c) and (d) show the state in which semiconductor elements are mounted. FIG. As shown,
In this embodiment, the wall 2 is raised directly from the periphery of the bonding pad 1. In this case, the bonding pad 1 is first formed by the first thick film printing, and the wall 2 is formed by printing in a frame shape overlappingly on the peripheral edge of the bonding pad 1 in the second printing. In this embodiment, unlike the first embodiment, the entire bonding pad 1 having a wall 2 around it serves as a reservoir, which functions to trap the leaked adhesive 5 inside. Furthermore, when the semiconductor element 62 is vertically long (cantilever-shaped) as shown in FIG. Better than that in Example 1.
第３図は第３の実施例に係るものを示し、同図（ａ）は
平面図、同図（ｂ）は断面図、同図（ｃ）、（ｄ）は半
導体素子を実装した状態を示す図である。図示の通り、
この実施例では、ボンディングパッド１の周縁から一定
の間隙を隔てた位置に、これを囲む壁２を形成しており
、しかも壁２の高さがボンディングパッド１の厚さの２
倍になっている。すなわち、第１実施例と同様の方法で
ボンディングパッド１とこれを囲む枠状の壁２の下側部
分を厚膜印刷法で形式した後、第２回目の印刷で枠状の
上側部分のみを重ねて印刷して壁２の高さを２倍にして
いる。流出した接着剤５を壁２で囲まれた部分の内部に
止める作用は第１実施例と同様であるが、壁２の高さを
２倍にした分、貯留容量が増大している。また、同図（
ｄ）のように縦長の半導体素子６２に対する作用は、第
２図（ｄ）に示す第２実施例と同様である。FIG. 3 shows a third embodiment, in which (a) is a plan view, (b) is a cross-sectional view, and (c) and (d) show the state in which semiconductor elements are mounted. FIG. As shown,
In this embodiment, a wall 2 surrounding the bonding pad 1 is formed at a position separated from the periphery by a certain distance, and the height of the wall 2 is 2 times the thickness of the bonding pad 1.
It's doubled. That is, after forming the lower part of the bonding pad 1 and the frame-shaped wall 2 surrounding it by thick film printing in the same manner as in the first embodiment, only the upper part of the frame-shaped part is printed in the second printing. The height of wall 2 is doubled by overprinting. The function of stopping the spilled adhesive 5 inside the area surrounded by the wall 2 is similar to that of the first embodiment, but the storage capacity is increased by doubling the height of the wall 2. Also, the same figure (
The effect on the vertically elongated semiconductor element 62 as shown in d) is the same as in the second embodiment shown in FIG. 2(d).
第４図は第４の実施例に係るもの示し、同図（ａ）は平
面図、同図（ｂ）は断面図、同図（ｃ）、（ｄ）は半導
体素子を実装した状態を示す図である。図示の通り、こ
の実施例では上記の第３実施例のものと異なり、ボンデ
ィングパッド１と壁２との間隙の基板１０の上面にＶ溝
４を形成しである。このＶ溝４は、ボンディングパッド
１の形成に先立ってコインニングにより形成されたもの
であり、■溝部の容積分だけ流出する接着剤５に対する
貯留容量が増大する。その他の作用は第３実施例と同様
である。なお、このＶ溝４を形成する方法は、第１実施
例に対しても効果的に適用することができる。FIG. 4 shows a fourth embodiment, in which (a) is a plan view, (b) is a cross-sectional view, and (c) and (d) show the state in which semiconductor elements are mounted. It is a diagram. As shown in the figure, this embodiment differs from the third embodiment in that a V-groove 4 is formed on the upper surface of the substrate 10 in the gap between the bonding pad 1 and the wall 2. This V-groove 4 is formed by coining prior to the formation of the bonding pad 1, and the storage capacity for the adhesive 5 that flows out increases by the volume of the groove portion. Other operations are similar to those of the third embodiment. Note that this method of forming the V-groove 4 can be effectively applied to the first embodiment as well.
第５図は第５の実施例に係るもの示し、同図（ａ）は平
面図、同図（ｂ）は断面図、同図（ｃ）は半導体素子を
実装した状態を示す図である。図示の通り、この実施例
では上記の第３実施例のものと異なり、ボンディングパ
ッド１の上面に半導体素子６２を水平に保持するための
パッドとして突起８を付加している。この突起８を設け
たことにより、同図（Ｃ）に示すように、カンチレバー
状の縦長の半導体素子６２を水平かつ安定に保持するこ
とができるほか、接着剤５の厚みが均一化され、半導体
素子６２の表面への接着剤５の回り込みを防止できる。FIG. 5 shows a fifth embodiment, in which FIG. 5(a) is a plan view, FIG. 5(b) is a sectional view, and FIG. 5(c) is a diagram showing a state in which a semiconductor element is mounted. As shown in the figure, unlike the third embodiment described above, in this embodiment, a protrusion 8 is added to the upper surface of the bonding pad 1 as a pad for horizontally holding the semiconductor element 62. By providing this protrusion 8, the cantilever-shaped vertically long semiconductor element 62 can be horizontally and stably held as shown in FIG. The adhesive 5 can be prevented from coming around to the surface of the element 62.
その他の作用は前述の実施例と同様である。Other operations are similar to those of the previous embodiment.
本発明においては、基板や半導体素子として各種のもの
を用い得る。In the present invention, various types of substrates and semiconductor elements can be used.
例えば、基板の材料は目的とする回路の性質に応じて選
択できるが、−殻内なガラスエポキシ材は勿論、アルミ
ナセラミック材等でもよい。また半導体素子とはＩＣ製
造工程におけるダイシング直後の半導体チップと共に、
バラケージング工程を経たＦＰないしはＣＣその他の形
式のＩＣないしＬＳＩをも指す。For example, the material of the substrate can be selected depending on the properties of the intended circuit, and may be an alumina ceramic material as well as an in-shell glass epoxy material. In addition, a semiconductor element is a semiconductor chip immediately after dicing in the IC manufacturing process.
It also refers to FPs, CCs, and other types of ICs or LSIs that have undergone a disassembly process.
上記のボンディングパッドや実効的段差の形成用材料と
しては、使用する半導体素子の種類に応じて、例えばＡ
ｇ系導電塗料やガラス絶縁塗料等を用いることができる
。またダイボンディング用接着剤としては、例えばＡｇ
ペーストや半田ペーストないし熱硬化もしくはＵＶ硬化
タイプの接着剤等、各種の金属系、高分子系接着剤が挙
げられる。The material for forming the bonding pad and the effective step may be, for example, A
G-based conductive paint, glass insulation paint, etc. can be used. In addition, as a die bonding adhesive, for example, Ag
Examples include various metal-based and polymer-based adhesives, such as paste, solder paste, and thermosetting or UV-curable adhesives.
以上、詳細に説明したように、本発明においては、ボン
ディングパッドの周囲に半導体素子等の裏面の接着剤層
からはみ出した接着剤を滞留させる溝状部分を段差によ
って形成するので、流出した接着剤が基板上に拡がって
半導体素子の電極やその周辺回路に回り込むことがなく
、これらの回路をショートさせるトラブルを確実に防止
することができる。また、これにより接着剤塗布管理に
対する依存度が軽減される。As explained above in detail, in the present invention, a groove-like portion is formed around the bonding pad by a step to retain the adhesive that has protruded from the adhesive layer on the back side of the semiconductor element, so that the adhesive that has flowed out can be removed. This prevents the semiconductor element from spreading onto the substrate and getting around to the electrodes of the semiconductor element and its peripheral circuits, thereby reliably preventing troubles such as short-circuiting of these circuits. This also reduces dependence on adhesive application management.
第１図は本発明の第１実施例の工程を示す基板部分の構
造説明図、第２図ないし第５図はそれぞれ本発明の第２
ないし第５実施例の工程を示す基板部分の構造説明図で
ある。
１・・・ボンディングパッド、２・・・壁、４・・・Ｖ
溝、５・・・接着剤、６１．６２・・・半導体素子、８
・・・突起、１０・・・基板。
３字５１３目−２Ｐ安ヒイづ
第
図
ρｊ
第２大沢伊１
第
図
第４−莢糧伊ｊ
第
図
（ｂ）
第５災複例
第
図FIG. 1 is a structural explanatory diagram of a substrate portion showing the steps of the first embodiment of the present invention, and FIGS.
FIG. 7 is a structural explanatory diagram of a substrate portion showing the steps of the fifth embodiment. 1...Bonding pad, 2...Wall, 4...V
Groove, 5...Adhesive, 61.62...Semiconductor element, 8
...Protrusion, 10...Substrate. 3rd character 513th - 2P Anhizu diagram ρj 2nd Osawa I 1 Figure 4 - Pod Ij Figure (b) 5th disaster compound diagram
Claims (1)
導体素子を接合するダイボンディング方法において、 前記ボンディングパッドの周囲に当該ボンディングパッ
ドを実効的に囲む断面凸形状の段差を形成することを特
徴とするダイボンディング方法。 ２、前記段差を、厚膜印刷法による少なくとも１回の厚
膜印刷により形成することを特徴とする請求項１記載の
ダイボンディング方法。 ３、前記ボンディングパッドと前記段差との間隙の前記
基板表面に、前記ボンディングパッドを実効的に囲む溝
を形成することを特徴とする請求項１または２記載のダ
イボンディング方法。 ４、前記ボンディングパッド面の一部を前記段差の高さ
と等しい高さに突出させ、半導体素子をその突出面と前
記段差の上面とに差し渡してボンディングすることを特
徴とする請求項１記載のダイボンディング方法。[Claims] 1. In a die bonding method in which a bonding pad is formed on a substrate and a semiconductor element is bonded thereon, a step having a convex cross section is provided around the bonding pad to effectively surround the bonding pad. A die bonding method characterized by forming. 2. The die bonding method according to claim 1, wherein the step is formed by at least one thick film printing process using a thick film printing method. 3. The die bonding method according to claim 1 or 2, wherein a groove that effectively surrounds the bonding pad is formed on the surface of the substrate in a gap between the bonding pad and the step. 4. The die according to claim 1, wherein a part of the bonding pad surface is protruded to a height equal to the height of the step, and the semiconductor element is bonded across the protruding surface and the upper surface of the step. Bonding method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1195779A JP2772828B2 (en) | 1989-07-28 | 1989-07-28 | Die bonding method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1195779A JP2772828B2 (en) | 1989-07-28 | 1989-07-28 | Die bonding method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0360133A true JPH0360133A (en) | 1991-03-15 |
| JP2772828B2 JP2772828B2 (en) | 1998-07-09 |
Family
ID=16346827
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1195779A Expired - Lifetime JP2772828B2 (en) | 1989-07-28 | 1989-07-28 | Die bonding method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2772828B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5476820A (en) * | 1994-02-04 | 1995-12-19 | Honda Giken Kogyo Kabushiki Kaisha | Method of manufacturing semiconductor gas rate sensor |
| KR100373117B1 (en) * | 2000-05-25 | 2003-02-25 | 현대자동차주식회사 | Structure for mounting a radiator grille of an automobile |
| DE10213609A1 (en) * | 2002-03-27 | 2003-10-23 | Infineon Technologies Ag | Electrical component with a contact and method for forming a contact on a semiconductor material |
| JP2004119944A (en) * | 2002-09-30 | 2004-04-15 | Toyota Industries Corp | Semiconductor module and mounting substrate |
| JP2007016005A (en) * | 2005-07-11 | 2007-01-25 | Santen Pharmaceut Co Ltd | Aqueous solution containing oxyglutathione |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5918648A (en) * | 1982-07-21 | 1984-01-31 | Mitsubishi Electric Corp | Manufacture of hybrid integrated circuit device |
| JPS63181437A (en) * | 1987-01-23 | 1988-07-26 | Matsushita Electronics Corp | Printed board |
-
1989
- 1989-07-28 JP JP1195779A patent/JP2772828B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5918648A (en) * | 1982-07-21 | 1984-01-31 | Mitsubishi Electric Corp | Manufacture of hybrid integrated circuit device |
| JPS63181437A (en) * | 1987-01-23 | 1988-07-26 | Matsushita Electronics Corp | Printed board |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5476820A (en) * | 1994-02-04 | 1995-12-19 | Honda Giken Kogyo Kabushiki Kaisha | Method of manufacturing semiconductor gas rate sensor |
| KR100373117B1 (en) * | 2000-05-25 | 2003-02-25 | 현대자동차주식회사 | Structure for mounting a radiator grille of an automobile |
| DE10213609A1 (en) * | 2002-03-27 | 2003-10-23 | Infineon Technologies Ag | Electrical component with a contact and method for forming a contact on a semiconductor material |
| US6791349B2 (en) | 2002-03-27 | 2004-09-14 | Infineon Technologies Ag | Electrical component with a contact and method for forming a contact on a semiconductor material |
| DE10213609B4 (en) * | 2002-03-27 | 2006-02-09 | Infineon Technologies Ag | An electrical device having a bonding pad and method of forming a bonding pad on a semiconductor material |
| JP2004119944A (en) * | 2002-09-30 | 2004-04-15 | Toyota Industries Corp | Semiconductor module and mounting substrate |
| JP2007016005A (en) * | 2005-07-11 | 2007-01-25 | Santen Pharmaceut Co Ltd | Aqueous solution containing oxyglutathione |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2772828B2 (en) | 1998-07-09 |
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