JPH0359773U - - Google Patents
Info
- Publication number
- JPH0359773U JPH0359773U JP12106889U JP12106889U JPH0359773U JP H0359773 U JPH0359773 U JP H0359773U JP 12106889 U JP12106889 U JP 12106889U JP 12106889 U JP12106889 U JP 12106889U JP H0359773 U JPH0359773 U JP H0359773U
- Authority
- JP
- Japan
- Prior art keywords
- output
- switch
- comparator
- adder
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Picture Signal Circuits (AREA)
- Input Circuits Of Receivers And Coupling Of Receivers And Audio Equipment (AREA)
Description
第１図は本考案のノイズ除去回路の一実施例を
示すブロツク図、第２図は同第１図の動作波形図
、第３図は同第２図の水平走査線（Ｈ）とノイズ
の関係図である。
１，２……１Ｈ遅延回路、３……加算器、４…
…1/2ゲインアンプ、５，６……コンパレータで
ある。
FIG. 1 is a block diagram showing an embodiment of the noise removal circuit of the present invention, FIG. 2 is an operation waveform diagram of FIG. 1, and FIG. 3 is a diagram of the horizontal scanning line (H) of FIG. It is a relationship diagram. 1, 2...1H delay circuit, 3...adder, 4...
...1/2 gain amplifier, 5, 6...comparators.
Claims (1)
おいて、映像検波出力信号を第１の１Ｈ遅延回路
と加算器入力と第１のコンパレータとに接続し、
同第１の１Ｈ遅延回路出力を第２の１Ｈ遅延回路
と前記第１のコンパレータの他方の入力と第２の
コンパレータと出力信号切換えスイツチの一方の
端子とに接続し、同第２の１Ｈ遅延回路出力を同
第２のコンパレータの他方の入力と前記加算器の
他方の入力とに接続し、同加算器出力を1/2ゲイ
ンアンプを通して前記スイツチの他方の端子に接
続し、前記第１のコンパレータ出力と前記第２の
コンパレータ出力とをそれぞれ２入力オアゲート
回路に接続し、同オアゲート回路出力を前記スイ
ツチの制御端子に接続し、前記第１の１Ｈ遅延回
路出力信号と前記1/2ゲインアンプを通した前記
加算器出力信号とを切換えて同スイツチの共通端
子より補間信号を出力してなるノイズ除去回路。 In a clear vision with a built-in tuner for satellite broadcast reception, a video detection output signal is connected to a first 1H delay circuit, an adder input, and a first comparator,
The output of the first 1H delay circuit is connected to the second 1H delay circuit, the other input of the first comparator, the second comparator, and one terminal of the output signal changeover switch, and The circuit output is connected to the other input of the second comparator and the other input of the adder, the output of the adder is connected to the other terminal of the switch through a 1/2 gain amplifier, and the output of the adder is connected to the other terminal of the switch through a 1/2 gain amplifier. The comparator output and the second comparator output are each connected to a two-input OR gate circuit, the output of the OR gate circuit is connected to the control terminal of the switch, and the output signal of the first 1H delay circuit and the 1/2 gain amplifier are connected. A noise removal circuit configured to switch the adder output signal passed through the switch and output an interpolated signal from the common terminal of the switch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12106889U JPH0359773U (en) | 1989-10-17 | 1989-10-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12106889U JPH0359773U (en) | 1989-10-17 | 1989-10-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0359773U true JPH0359773U (en) | 1991-06-12 |
Family
ID=31669111
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12106889U Pending JPH0359773U (en) | 1989-10-17 | 1989-10-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0359773U (en) |
-
1989
- 1989-10-17 JP JP12106889U patent/JPH0359773U/ja active Pending