JPH0359520B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory device including a memory cell having a MOS transistor configuration, and particularly to a sense amplifier thereof.

[Technical background of the invention and its problems]

Conventionally, a sense amplifier in a semiconductor memory device having a CMOS configuration has been configured as shown in FIG. In the figure, 11 _i1 , 11 _i2 , ... are memory cells of MOS transistor configuration, 12 is a MOS type first differential amplifier, 13 is a MOS type second differential amplifier, and 14 is an output buffer circuit (CMOS inverter). circuit). First, N-channel type
When the chip enable signal supplied to the MOS transistor _Q1 goes high, the transistor _Q1 turns on and becomes ready for sensing operation. Next, the output signal CD _i of the column decoder (not shown) becomes high level, and the MOS transistors Q ₂ and Q ₃ that serve as load elements and the MOS transistors Q ₄ and Q ₅ that serve as differential input elements are disposed between them. When transistors Q ₆ and Q ₇ are turned on,
Memory cell 11 _i connected to bit line _i , BL _i
The columns _{1 ,} 11 _i2 , . _. . are selected, and the bit _{lines i ,} .
The stored information is read to BL _i . Therefore, depending on the information stored in the memory cell 11 _ij , the bit lines _i and BL _i
One of them is at high level and the other is at low level. Corresponding to the potential change of the bit lines _i and BL _i , one of the transistors Q ₄ and Q ₅ whose gates are connected to the bit lines _i and BL _i , respectively, is turned on and the other is turned off. Depending on the on or off state of the transistors Q ₄ and Q ₅ , the potential at the connection point a between the transistors Q ₂ and Q ₆ and the connection point b between the transistors Q ₃ and Q ₇ changes, and the potential at the connection point a and b changes. The potential is supplied to the gates of MOS transistors Q ₈ and Q ₉ that serve as differential input elements of the second differential amplifier 13. This transistor Q ₈ , Q ₉
is a transistor that constitutes a current mirror circuit.
A constant current is supplied from Q ₁₀ and Q ₁₁ , and the potential at the connection point c of transistors Q ₁₁ and Q ₉ is
Consists of Q ₁₂ and Q ₁₃ and works as a buffer circuit
The signal is supplied to a CMOS inverter circuit 14, and an output signal OUT corresponding to the stored information of the selected memory cell _11ij is obtained from this circuit 14.

By the way, when reading information stored in a memory cell, the ratio of the currents flowing through the differential input transistors Q ₄ and Q ₅ (this current ratio is
(converted to voltage by Q ₂ and Q ₃ ) is the bit line
If the voltages of BL _i and BL _i are respectively V ₁ and V 2 , the potential difference between V ₁ and _{V 2} is ΔV, the source potential of transistors Q ₄ and Q ₅ is V ₀ , and the threshold voltage is V _th , then It is expressed as shown in equation (1).

id ₂ /id ₁ = β/2(V ₂ −V ₀ −V _th ) ² /β/2(V ₁ −V ₀
−V _th ) ² = (V ₁ +ΔV−V ₀ −V _th ) ² / (V ₁ −V ₀ −V _th ) ² 1+2ΔV/(V ₁ −V ₀ −V _th ) ² ……(1) Therefore , the sensitivity of this first differential amplifier 12 is highest at the point where "V ₁ - V ₀ - V _th = 0", but if designed in this way, the mutual conductance
gm decreases, the second differential amplifier 13 in the next stage
It takes a lot of time to drive. Therefore, in order to increase the mutual conductance gm and increase the sense sensitivity, the bit lines _i , BL _i
It is necessary to set the potential difference ΔV large.

On the other hand, if the current supplied to the bit line is I _b , then
The time td required for transition from a high level to a low level or from a low level to a high level is approximately "td=C _B · ΔV/I _b ". Here, C _B is the bit line capacitance. That is, if ΔV is set to a large value, the transition time td of the bit line potential becomes a large value.

As mentioned above, in a MOS type differential amplifier, sense sensitivity and mutual conductance gm are inversely proportional, and it has been difficult to reduce the signal delay time of the bit line and the sense circuit at the same time.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and its purpose is to provide a sense amplifier that is highly sensitive and capable of high-speed operation.

[Summary of the invention]

That is, in the present invention, a differential input signal is supplied from a MOS circuit to a first differential amplifier equipped with a pair of bipolar transistors as differential input elements, and the output signal of the first differential amplifier is amplified. is supplied to a second differential amplifier equipped with a pair of MOS transistors as differential input elements for amplification.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. Figure 2 shows its configuration.
In the figure, 15 is a first differential amplifier equipped with a bipolar transistor as a differential input element;
17 is an inverter circuit that functions as a buffer circuit; Q ₁₄ and Q ₁₅ are connected to bit lines whose conduction is controlled by the output signal CD _i of the column decoder;
This is a bit line selection transistor that selects BL _i and BL _i .

FIG. 3 shows an example of the circuit configuration of the first differential amplifier 15 and the second differential amplifier 16. That is, bipolar NPN transistors Q ₁₆ and Q ₁₇ act as differential input elements of the first differential amplifier 15.
includes memory cells of MOS type configuration (not shown)
from the bit line selection transistor Q ₁₄ ,
Storage information (differential input signal) is supplied via _Q15 . The emitters of the differential input transistors Q ₁₆ and Q ₁₇ are commonly connected and connected to the second current V _ss via the current source I. Also, the transistor Q ₁₆ ,
The collectors of Q ₁₇ are connected to the first power supply terminal V _cc via load elements (eg, resistors) R ₁ and R ₂ , respectively. The potential at the connection point d between the resistor R ₁ and the transistor Q ₁₆ and the potential at the connection point e between the resistor R ₂ and the transistor Q ₁₇ are the same as the potential at the connection point d between the resistor R 1 and the transistor Q 16 and the potential at the connection point e between the resistor R 2 and the transistor Q 17.
Supplied to Q ₁₈ and Q ₁₉ . This transistor Q ₁₈ ,
A constant current is supplied to one end of Q ₁₉ from the power supply terminal V _cc via MOS transistors Q ₂₀ and Q ₂₁ in a current mirror circuit configuration, and the other end is connected to a second
Connected to power supply terminal V _ss . Then, the potential at the connection point f between the transistors Q ₂₁ and Q ₁₉ is set to MOS
It is obtained as an output signal OUT via a CMOS inverter circuit 17 consisting of transistors Q ₂₂ and Q ₂₃ .

In the above configuration, bit lines _i ,
The difference between the potentials V ₁ and V ₂ of BL _i is expressed as ΔV, that is, “ΔV=V ₁ −
V ₂ ', the current ratio i ₁ /i ₂ of the currents i ₁ and i ₂ flowing through the transistors Q ₂₆ and Q ₁₇ is expressed by the following equation (2) according to the operation of the bipolar transistor.

Therefore, the differential voltage ΔV ₁ of the output signal obtained from the first differential amplifier 15 is: , "gm=1/R" and does not depend on ΔV or ΔV ₁ . By the way, according to the above formula (3), “ΔV=
25mV", "ΔV ₁ = R _i (1-1/e)", and approximately 2/3 of the voltage when "ΔV = ∞" is output with a constant mutual conductance gm, so the sensitivity is in good condition. On the other hand, in the second differential amplifier 16, the gate and drain of a P-channel type MOS transistor _Q20 are connected, and the transistor _Q20 and
Since the gate-source voltage V _GS with Q ₂₁ is the same for both, they form a current mirror circuit where "i ₃ = i ₄ " near the same potential as described above. Now, the gate potential of MOS transistor _Q18 is high level (at this time, the gate potential of MOS transistor _Q19 is low level), and this transistor
When Q ₁₈ is turned on, the drain side of Q ₁₈ becomes low level. Therefore, transistor Q ₂₀ ,
Q ₂₁ is more conductive and transistor
With the help of the low-level signal supplied to the gate of _Q19 , the potential at the connection point f between transistors _Q21 and _Q19 quickly rises to high level. On the other hand, the gate potential of transistor _Q18 is low level, and the transistor
When the gate potential of _Q19 is high level, the operation is reversed. By the way, since the gate potential of the transistors Q ₁₈ and Q ₁₉ (the potential at the connection points d and e) is an intermediate potential between the potential of the first power supply V _DD and the potential of the second power supply V _ss , the output is V _DD , V Since it does not fully swing between _ss , the waveform is shaped by the inverter circuit 17.
An output signal OUT is obtained that fully swings between V _DD and V _ss .

As described above, the first differential amplifier 15 using bipolar transistors as differential input elements can amplify small signals without reducing mutual conductance. The second differential amplifier 16 used as an element takes time to amplify a small signal, but if the signal is relatively large like the one amplified by the first differential amplifier 15, the mutual conductance gm can be set large.
Moreover, unlike bipolar transistors, there is no carrier accumulation effect, so even if the power supply voltage is amplified to its maximum, the speed will not slow down.

In order to investigate the operating characteristics of the circuit described above, the difference ΔV between the voltages applied to the bases of bipolar transistors Q ₁₆ and Q ₁₇ is 0.8 V, and the resistance values of resistors R ₁ and R ₂ are respectively
10KΩ, difference in output voltage of the first differential amplifier 15 ΔV ₁
is set to 2.4V, and the channel width W of the P-channel MOS transistors Q ₂₀ , Q ₂₁ and the N-channel MOS transistors Q ₁₈ , Q ₁₉ of the second differential amplifier 16 is set to 2.4V.
A simulation was performed by setting the ratio of 1:5, and a comparison was made with the circuit shown in FIG. As a result, when using the same memory cell with a channel length of 3 μm and using the precharge method, the access time was 45 nS in the conventional circuit, while it was approximately 35 nS in the circuit shown in Figure 3 above.
I was able to improve it by 10nS. The above-mentioned simulation has demonstrated that this difference increases as the bit line amplitude ΔV is further reduced to increase the speed.

Note that in order to operate a bipolar differential amplifier, it is necessary to supply a base current of I ₁ /β _NPN (β _NPN is the common emitter current amplification factor), but the memory cell and precharge circuit are configured in a MOS type. In addition, the β _NPN may vary during the manufacturing process, which may adversely affect the setting of the bit line potential. Therefore, depending on the required characteristics, the bipolar differential input transistors may have a Darlington connection structure.

Figure 4 shows the circuit configuration of the third circuit.
Bipolar type NPN differential input transistors Q ₁₆ and Q ₁₇ in the figure and bipolar type NPN transistors Q ₂₄ and Q ₂₅ are connected in Darlington, and between the base and emitter of the transistor Q ₁₆ and between the base and emitter of Q ₁₇ , respectively. Resistance R ₃ ,
R ₄ is connected, and the differential input signals V ₁ and V ₂ are supplied to the transistors Q ₂₄ and Q ₂₅ . In the above configuration, the base current i _B for driving the bipolar transistor Q ₂₄ or Q ₂₅ can be expressed by the following equation (4).

i _B = (V _f /RH + I/β _NPN ² )・1/β _NPN ...(4) In the above equation (4), V _f is the forward voltage of the PN junction diode, RH is the thermal resistance, and this RH is It is well known that increasing the size does not affect the operating speed. As a result, the current i _B can be reduced to 1 μA or less, and compatibility with MOS memory can be improved.

By the way, in the CMOS manufacturing process,
It is common practice to form bipolar transistors at the same time, especially in a CMOS process in which N-type well regions 19, 19 are formed on a P-type semiconductor substrate 18 as schematically shown in FIG. In this case, a P-channel type MOS transistor QP is formed on the well regions 19, 19, and
Forms an NPN type bipolar transistor QB.
At this time, the base region 22 is diffused at the same time as the P-type impurity is diffused into the relatively deep source and drain regions 20 and 21 with a diffusion depth xj, and the source and drain regions 23 and 24 of the N-channel MOS transistor QN with a shallow diffusion depth xj are diffused. If the emitter region 25 and collector contact region 26 are diffused simultaneously with the P-type impurity diffusion, there is no need to add a new manufacturing process.

Note that if the characteristics of the bipolar transistor with such a configuration are not sufficient, characteristic parameters such as β _NPN and cutoff frequency _T can be improved by adding an internal base diffusion step to the above-described manufacturing process. Furthermore, unlike the normal bipolar transistor shown in FIG. 5, there is no buried layer, so the internal collector resistance rc may become large. Theoretically, the minimum dimension is 2 x 5 μm.
When using an emitter, the internal collector resistance rc is
Calculated to be 1KΩ. However, the influence of internal collector resistance rc can be addressed by design. That is, the values of the collector load resistances R ₁ and R ₂ in FIG. 3 may be set to values that are sufficiently larger than the internal collector resistance rc. On the other hand, as a means to lower the internal collector resistance rc, as shown in FIG. 6, a highly concentrated impurity region 26 for contacting the collector region 19 is formed to surround the base region 22, or the emitter area is set large. It is possible that Here, the internal collector resistance rc is not directly related to the amplification coefficient eq/K _T ΔV, and the sense sensitivity is not reduced thereby.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without changing the gist of the invention.

〔Effect of the invention〕

As explained above, according to the present invention, a sense amplifier that is highly sensitive and capable of high-speed operation can be obtained.

[Brief explanation of drawings]

FIG. 1 is a diagram for explaining the configuration of a sense amplifier in a conventional semiconductor memory device, FIG. 2 is a diagram schematically showing a sense amplifier according to an embodiment of the present invention, and FIG. 3 is a diagram for explaining the configuration of a sense amplifier in a conventional semiconductor memory device. FIG. 4 is a diagram for explaining another embodiment of the present invention, and FIG. 5 and FIG.
FIG. 3 is a diagram for explaining the manufacturing process of the circuit shown in the figure. 15...First differential amplifier, 16...Second differential amplifier, _Q16 , _Q17 ...Bipolar type differential input elements, _Q18 , _Q19 ...MOS type differential input elements.

Claims (1)

[Scope of Claims] 1. A first differential amplifier including a pair of bipolar transistors as differential input elements to which a differential input signal is supplied from a MOS circuit, and an output signal of the first differential amplifier is supplied. and a second differential amplifier including a pair of MOS type transistors as differential input elements. 2 The first differential amplifier includes a pair of bipolar transistors having one end commonly connected to which a differential input signal is supplied, and a pair of load elements each connected between the other end of the transistor and a first power supply terminal. , the common connection point of the pair of transistors and the second
The sense amplifier according to claim 1, further comprising a constant current source disposed between the power supplies. 3. The sense amplifier according to claim 1 or 2, wherein each of the pair of bipolar transistors is a Darlington-connected transistor. 4 Claims in which the second differential amplifier comprises a pair of MOS transistors to which the output signal of the first differential amplifier is supplied, and a current mirror circuit that supplies a constant current to each of the transistors. The sense amplifier described in item 1.