JPH0359439B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the field of computer-generated raster graphics, and more particularly to:
Behaviors displayed by cathode ray tube (CRT) display devices, such as devices that require less memory without reducing the number of colors, and that allow background or foreground behavior to be changed independently. .

[Conventional technology]

Raster scan CRT display means are the primary means of communication between a computer user and the user's hardware/software equipment. The basic display device for computer-generated raster graphics is the CRT monitor device,
Closely related to standard television receivers. To exploit the full potential of raster graphics, such display means require extensive random access memory (RAM) and supporting equipment with digital computing power. Recent
As a result of the development of LSI circuits, the price of digital memory has fallen significantly, and microcomputers capable of controlling such displays are now available at affordable prices.

As a result, the development of raster graphics has become active. Typically, each pixel in a rectangular array of picture elements (pixels) of a CRT is assigned an individual address, which consists of the X and Y coordinates of each pixel in the array.

Information for controlling the display is stored in random access memory (RAM) locations with addresses corresponding to the locations assigned to those pixels. The source of the pixel control data stored in the RAM is typically a microcomputer within the graphics controller. This controller then provides the information necessary to determine the type of display.
Write to an addressable memory location in RAM.
This often includes an address in color lookup memory where a binary color control signal is stored that controls the intensity of the color of each pixel in the array. The horizontal and vertical sweeps of the raster scan are quantized to create pixel addresses. These addresses are then applied to a memory in which the controller has previously written the display decision information, ie, the color and brightness of the pixels addressed in the scan. As mentioned above, this information is an address in color backup memory.

Digital color control signals are read from addressed locations in lookup memory. This digital color control signal is converted to an analog signal and applied to the three color electron guns of a typical CRT to control the brightness and color of each pixel as it is scanned.

A known technique for controlling the display of such devices is to have a pixel memory and a corresponding behavioral memory, with the former pixel memory having a display control bit in each addressable memory location where background/foreground control bits are stored. Containing a pixel image, the latter behavior memory defines the color or behavior of each pixel. The required memory size is the number of pixels x (background/foreground control bits + number of color bits)
be equivalent to. Note that the number of color bits is typically 4 bits for each pixel.

There is a need in color graphics devices to reduce the amount of memory required without reducing the variety of colors displayed by each pixel.

[Summary of the invention]

The invention provides an apparatus that includes a random access memory in which, for example, four control bits and four behavioral bits are stored in addressable locations. The addressable location then corresponds to a pixel address of one pixel of a set of four adjacent pixels. Addressing four adjacent pixels at a time takes account of the fact that in most displays, i.e., thematic, birtual, trend, etc., four such pixels have the same background or foreground color. It is for use. Thus, the required memory size is
Compared to conventional devices that require 5 bits of memory per each pixel, there are 2 bits for each pixel in a device that uses a 5-bit behavioral signal.

The sweep signals are quantized to form pixel addresses, and these pixel addresses are used to address the RAM. This RAM then has the address of one of the four pixels that it is used to address.

The pixel clock generates one pixel clock pulse each time each pixel is scanned. During each memory read cycle,
The four background/foreground control bits that were stored at the addressed location in RAM are written to the shift register. The shift register reads or generates one control bit for each pixel clock pulse generated by the pixel clock. Foreground and background register means are provided in which the four behavioral bits generated by the memory are stored during each read cycle.

A unique set of behavior bits, a set of escape controls, a detector for escape codes, inhibits escape codes from being written to the foreground or background behavior registers.

Whenever the escape code detector detects that four behavioral bits stored at an addressed location form an escape code, the four behavioral bits that are read during the next memory read cycle are Behavior bits are stored in background behavior registers. Note that only the set of behavior bits immediately after the escape code is detected are written to the background behavior register. All other sets of behavior bits read from memory are written to and stored in the foreground behavior register. The background/foreground control bits (these are read from the shift register and are one control bit for each pixel clock pulse) are applied to a 2:1 multiplexer.
The multiplexer is also provided with signals stored in the foreground and background behavior registers. Depending on the value of the background/foreground control bits read from the shift register and applied to the multiplexer,
The behavior bits stored in the foreground or background behavior registers and the control bits are applied to a 5-bit latch circuit to form a color index, or address. The color index is then applied to a color lookup memory and, for example, the 8 bits of the color signal stored in the addressed location of the color lookup memory are applied to a digital to analog converter (D/A converter). red,
It generates green and blue color control signals, and these signals are applied to the CRT's color electron gun.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide an improved means for controlling color in a raster graphics device that reduces the amount of memory required without reducing the number of behaviors displayed.

Another object of the present invention is to provide an improved means for controlling color in a raster graphics device that can independently change background or foreground behavior.

Further objects, features, and effects of the present invention will become readily apparent from the following description of preferred embodiments with reference to the drawings.

〔Example〕

FIG. 1 is a block diagram of an apparatus for controlling colors displayed by a raster graphics device.

The illustrated device is computer generated,
In other words, it is a device for controlling the video (image) displayed by the raster graphics device being controlled.

Graphics controller 10 writes into color lookup memory 16 as well as random access pixel memory 12 and behavior memory 14 binary digital information used to control the brightness and color of each pixel of conventional color CRT 17. The raster scanning logic 18 of the CRT 17 includes conventional quantization circuitry to digitize the horizontal and vertical sweep signals of the raster scan of the CRT 17 and provide a number, or address, for each pixel on the surface of the CRT 17.

19 to individually specify each of the 640 horizontal pixels and 480 vertical pixels of a standard CRT raster.
- A bit address is required, ie an address consisting of 10 bits for the X component and 9 bits for the Y component. The X component address corresponds to the ordinate of the pixel of the approximately rectangular raster, and the Y component address corresponds to the abscissa.

In FIG.
Additionally, although pixel memory 12 and behavioral memory 14 are each shown as separate memories, they may be combined into a single conventional random access memory. Pixel clock 20 generates one clock pulse for each pixel of the raster as it is scanned. The output of the pixel clock 20 is applied to the control circuit of the present invention for synchronizing operations as will be described later, and is also provided to the memory 1.
2, 14 and 16. a set of adjacent pixels to minimize memory size and to allow slower memory usage;
For example, a single address is used as a memory address for a set of four pixels aligned in a horizontal scan line.

In other words, by addressing four pixels at a time, the lower two bits of each individual pixel's address are ignored. More precisely, they are considered logic zeros. pixel memory 12
stores four background/foreground control bits in each addressable memory location. These bits then determine whether the color of the corresponding pixel is a background color or a foreground color, as described below. The four behavioral bits stored in each addressable memory location in memory 14 form part of the address of the memory location in color backup memory 16. Stored in each addressable memory location of color lookup memory 16 are eight bits, or one byte, of a binary color control signal.

During each read cycle of this random access memory and especially the behavioral memory 14, 4
One behavior bit is read from behavior memory 14 and provided to escape code detector 22. Then, this detector determines whether the four behavior bits have a predetermined value, that is, whether they are a predetermined set of behavior bits (hereinafter sometimes referred to as an "escape code"). For example, it is checked whether all four behavior bits are logic ones.

If the bit stored at the addressed location in behavioral memory 14 is not an escape code, detector 22 generates a register enable signal. This signal allows register 24 to store the behavior bit read from behavior memory 14. If the four behavior bits read from behavior memory 14 constitute an escape code, the escape code detector detects whether either register 24 or background behavior register 26 contains a special set of behavior bits, ie, an escape code. Prevents or inhibits code from being stored, but generates a register enable control signal. This signal allows background behavior register 26 to store the set of behavior bits read from behavior memory 14 during the next memory 14 read cycle. During each read cycle of memories 12 and 14, background/foreground control bits are stored in shift register 28.
The control bits loaded into the shift register 28 are:
One pixel is shifted out of shift register 28 for each pixel clock pulse. Each control bit is then applied to multiplexer 30 as it occurs.

If the background/foreground control bit is logic 1, then
Multiplexer 30 provides the four signals stored in foreground behavior register 24 to color index latch circuit 32.

Also, if the background/foreground control bit is a logic 0, multiplexer 30 provides the four signals stored in background behavior register 26 to color index latch circuit 32. The background read from shift register 28 during each clock period/
The foreground control bits are combined with the four behavioral bits from multiplexer 30 to form a 5-bit color index or address. These addresses are stored in latch circuit 32 and then applied to the address logic circuit of color lookup memory 16. Typically, each addressable location of color lookup memory 16 stores an 8-bit, ie, color control signal. When these signals are read from memory 16, they are applied to a conventional D/A converter 34.

These color control signals are converted by the D/A converter 34 into analog signals for controlling the brightness of the red, green, and blue color electron guns of the ordinary CRT 17.

Synchronous with the scanning of each pixel in the array, the color lookup memory 16 stores 8 pixels for each pixel being scanned.
- Generates a bit-byte color control signal. This 8-bit byte is then provided to D/A converter 34. D/A converter 34
converts 6 bits of the 8-bit color control signal for that pixel into three analog signals. These analog signals are color CRT
Controls the brightness of 17 red, green and blue electron beam guns. In the preferred embodiment, two bits of each color control signal are provided to a fourth D/A converter, where these two bits are converted to a digital analog signal, as is commonly known in the art. used to create a permanent record of a raster display using equipment that

During normal raster scanning, the background/foreground control bits generated by shift register 28 determine whether the pixel being scanned has a foreground or background color. Multiplexer 30 (which is provided with the background/foreground bits) determines which set of behavioral bits are provided to latch circuit 32. Latch circuit 3
5 bits from 2 to 2 are color search memory 1
6 is used as the address of the memory location. This memory 16 stores color control signals for each pixel.
When scanned by the electron beam of CRT17,
Determines the color that each pixel displays.

[Effects of the present invention]

As is clear from the above description, the device according to the invention can be used without reducing the number of displayed colors.
It also largely reduces the amount of memory required in a color graphics device while keeping other variables approximately the same.

Additionally, the present invention allows the colors of the background and foreground to be changed independently of each other.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an apparatus for controlling colors displayed by a raster graphics device. 10: Graphics controller, 12: Pixel memory, 14: Behavioral memory, 16: Color lookup memory, 17: Color CRT,
18: Raster scanning logic, 20: Pixel clock, 22: Escape code detector, 24:
4-bit foreground behavior register, 26:4
-Bit background behavior register, 28:4-
Bit shift register, 30:2:1 multiplexer, 32: 5-bit latch, 34:
D/A converter.

Claims (1)

[Scope of Claims] 1. Pixel clock means for generating one pixel clock pulse per pixel for scanning each pixel; raster scanning logic means for generating an address signal for each pixel as described above; A random access that generates a set of "n" (where n is an integer greater than or equal to 2) control bits and a set of behavioral bits that are signaled and stored in the addressed memory location during each memory read cycle. memory, the address of the addressed memory location is the address of the first pixel of a set of "n" adjacent pixels of a horizontal scan line, and the memory read cycle is performed every nth clock pulse. a random access memory which generates a random access memory; and a shift register means which is loaded with "n" control bits read from said random access memory on each memory read cycle and which generates one control bit for each pixel clock pulse. and first and second behavior register means for storing behavior bits from said random access memory during each memory read cycle, and wherein each set of behavior bits generated during each memory read cycle is a predetermined behavior bit. a detection means for checking whether the set of behavior bits is a set of the predetermined behavior bits, and a detection means for checking whether the set of behavior bits checked by the detection means is not the set of the predetermined behavior bits, the set of behavior bits is stored in the first behavior register means; and when it is the predetermined set of behavior bits, the set of behavior bits is not stored in either the first or second behavior register means and is stored in the random access memory during the next memory read cycle. means for storing in second behavior register means a set of behavior bits read from said shift register means; said control bits and a set of behavior bits from said selected behavior register means to form an address of a color control memory. A device for controlling color. 2. In the statement of claim 1, n=4, the first behavior register means is a foreground behavior register means, and the second behavior register means is a background behavior register means. A device for controlling colors displayed by a raster graphics device, characterized in that the detection means is via register means and the detection means is escape code detection means. 3. A device for controlling colors displayed by a raster graphics device as set forth in claim 1, characterized in that n=4. 4. In claim 1, the first behavior register means holds a part of the address of the color control memory that generates the foreground color signal, and the second behavior register means holds a part of the address of the color control memory that generates the foreground color signal. , a device for controlling colors displayed by a raster graphics device, characterized in that it retains a portion of the address of said color control memory that generates a background color signal.