JPH0358467A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To protect a semiconductor integrated circuit against latch-up and data stored in a memory cell against damage by a method wherein an input protective element region where all input protective elements are arranged is provided near the periphery of a semiconductor chip outside a bonding pad. CONSTITUTION:An inner element region 6 is provided at the center of a semiconductor chip 1, a bonding pad 3 is provided adjacent to the outside of the inner element region 6, and an input protective element region 7 where all input protective elements are arranged is provided near the periphery of the semiconductor chip 1 outside the bonding pad 3. In this case, the input protective element region 7 is provided outside the inner element region 6 through the intermediary of the bonding pad 3 and hundreds of mums distant from inner elements, so that carriers, which occur in an input protective element region 7 and are injected into a semiconductor substrate, can be prevented from reaching to the inner elements without a barrier or a trap formed of a diffusion layer or a well. By this setup, a semiconductor integrated circuit can be protected against latch-up and data stored in a memory cell can be prevented from being damaged.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit having an input protection element. [Prior Art] In a conventional semiconductor integrated circuit, as shown in FIG. 3, an internal element region 6 is provided in the center of a semiconductor chip 1, and a part or all of an input protection element is arranged outside the internal element region. An input protection element region 7 is provided, and bonding pads 3 are arranged outside the input protection element region 7 and near the peripheral edge of the semiconductor chip 1. Usually, between the internal element region 6 and the input protection element region 7, there is a diffusion layer or Well was being disciplined.

[Problem to be solved by the invention]

In the conventional semiconductor integrated circuit described above, a part or all of the input protection element is placed between the bonding pad and the internal element area, so input protection is difficult due to sudden changes in input voltage or input of large voltage. Carriers generated in this region easily reach internal elements, causing latch-up and data corruption in memory cells. In addition, to prevent this, it is necessary to secure an isolation region within the semiconductor chip in order to form a diffusion layer or well at power supply potential or ground potential between the input protection region and the internal element region. This had the disadvantage of causing an increase in size.

[Means to solve the problem]

The semiconductor integrated circuit of the present invention includes an internal element area provided in the center of a semiconductor chip, a bonding pad provided outside the internal element area, and input protection provided near the periphery of the semiconductor chip outside the bonding pad. It has an input protection element area in which all of the elements are arranged.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a layout diagram showing a first embodiment of the present invention. As shown in FIG. 1, an internal element area 6 is provided in the center of the semiconductor chip 1, a bonding pad 3 is provided adjacent to the outside of the internal element area 6, and a peripheral edge of the semiconductor chip 1 outside the bonding pad 3 is provided. An input protection element region 7 in which all input protection elements are arranged is provided nearby.

Here, the input protection element region 7 is arranged outside the internal element region 6 with the bonding pad 3 interposed therebetween, and has a distance of several hundred knots to the internal element.
Carriers generated in the input protection element section and injected into the semiconductor substrate can be prevented from reaching internal elements without using barriers or traps such as diffusion layers or wells, preventing latch-up and data corruption in memory cells. ．． FIG. 2 is a layout diagram showing a second embodiment of the present invention.

As shown in FIG. 2, bonding pads 3 are arranged around the entire periphery of an internal element region 6 provided in the center of a semiconductor chip 1, and an input protection area is provided near the periphery of the semiconductor chip on the outer periphery of the bonding pads 3. This embodiment has the same width as that of the first embodiment except that 7 is provided. [Effects of the Invention] As explained above, the present invention arranges all of the input protection elements near the peripheral edge of the semiconductor chip outside the bonding pads, thereby eliminating the need for input protection parts and internal elements that were conventionally necessary. There is no need to provide a diffusion layer or well for latch-up countermeasures between the two, and a semiconductor integrated circuit with high latch-up resistance can be obtained with an occupied area equal to or smaller than the conventional one.

[Brief explanation of drawings]

1 and 2 are layout diagrams showing first and second embodiments of the present invention, and FIG. 3 is a layout diagram showing an example of a conventional semiconductor integrated circuit.

Claims (1)

[Claims] An internal element area provided in the center of the semiconductor chip, a bonding pad provided outside the internal element area, and an input protection element all arranged near the peripheral edge of the semiconductor chip outside the bonding pad. What is claimed is: 1. A semiconductor integrated circuit comprising: an input protection element region;