JPH0357007A - Information processor - Google Patents

Information processor

Info

Publication number
JPH0357007A
JPH0357007A JP1192878A JP19287889A JPH0357007A JP H0357007 A JPH0357007 A JP H0357007A JP 1192878 A JP1192878 A JP 1192878A JP 19287889 A JP19287889 A JP 19287889A JP H0357007 A JPH0357007 A JP H0357007A
Authority
JP
Japan
Prior art keywords
signal
clock
clock frequency
frequency
operation state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1192878A
Other languages
Japanese (ja)
Inventor
Akiyoshi Nakamura
明善 中村
Yutaka Ozawa
裕 小澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP1192878A priority Critical patent/JPH0357007A/en
Publication of JPH0357007A publication Critical patent/JPH0357007A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To reduce the power consumption by providing a clock frequency selecting means which selects a clock frequency in accordance with the signal of a clock frequency control means. CONSTITUTION:A device consists of an operation state detecting means 10 which detects the operation state, a clock control means 11 which outputs the signal to select a clock frequency corresponding to the operation state, and a frequency selecting means 12 which selects the frequency by this signal. An output 13 of the clock frequency selecting means 12 is the clock signal to a CPU. Consequently, the clock frequency is switched by detecting that a display part is opened/closed or the device is not used for a long time. Thus, the program load time after interruption of the use is omitted, and the time when the device can be operated by a battery as a weak point of a portable computer is extended because the power consumption for interrupted use is reduced, and the life of a display body is extended.

Description

【発明の詳細な説明】 「産業上の利用分野」 本発明は、装置の不作動状態を検出してクロック周波数
を選択する情報処理装置に関する。
DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to an information processing device that selects a clock frequency by detecting an inactive state of the device.

「従来の技術」 従来の電子計算機では作業を中断する時は、電源を切ら
なければ、動作中と同様な電力を消費する.しかし、電
源を切ってしまうと、動作中のプログラムを消してしま
うために、再びプログラムを実行するためには、プログ
ラムをフロッピーディスク等の記録媒体から読み込む必
要がある。従って短時間の作業中断の場合、その後のプ
ログラムのロードに時間がかかるうえにフロッピーディ
スクドライブを駆動する電力を消費してしまう。
``Conventional technology'' When a conventional electronic computer interrupts work, it consumes the same amount of power as when it is in operation, unless the power is turned off. However, when the power is turned off, the running program is erased, so in order to run the program again, it is necessary to read the program from a recording medium such as a floppy disk. Therefore, if the work is interrupted for a short time, it takes time to load the subsequent program and consumes power to drive the floppy disk drive.

「発明が解決しようとする課題」 しかしながら、表示部が開閉する電子計算機の場合、そ
の主な使用形態として、電源の無い場所でのバッテリー
による駆動が想定されるため無駄な電力の消費は問題で
ある。
"Problem to be Solved by the Invention" However, in the case of electronic computers with display parts that open and close, wasteful power consumption is a problem because it is expected that they will be mainly used in places where there is no power source. be.

そこで本発明はこのような課題を解決するもので、その
目的とするところは、装置の使用状態を検出してクロッ
ク周波数を変化させて、装置を合理的に作動させるとこ
ろにある。
The present invention is intended to solve these problems, and its purpose is to detect the usage status of the device and change the clock frequency to rationally operate the device.

「課題を解決するための手段」 本発明は、装置の不作動状態を検出する検出手段と、前
記検出手段の検出によってクロック信号を制御するクロ
ック周波数制御手段と、前記クロック周波数制御手段の
信号によって前記クロック周波数を選択するクロック周
波数選択手段とを少なくとも備えたことを特徴とする. 「実施例j 以下に本発明の一実施例としてクロック周波数を表示部
の開閉によって切換える電子計算機について図に基づい
て説明する. 第1図に本発明の構成を示す.作動状態を検出する作動
状態検出手段10と作動状態に対応したクロック周波数
を選択する信号を出力するクロック制御手段1lと、そ
の信号によって周波数を選択する周波数選択手段12と
で構成される.クロック周波数選択手段12からの出力
13はCPUはオンになる. 第3図は実施例のブロック図であって、スイッチ30に
よる割り込みによってCPU31はR○M32から表示
部の状態を調べるプログラムを実行し、表示部の開閉状
態をクロック周波数制御レジスタ34に書き込む、クロ
ック周波数制御レジスタ34の状態が変わるとこのレジ
スタ34の状態を常時監視しているクロック周波数制御
手段35はクロック周波数制御レジスタ34のビットの
オン、オフから表示部の開閉状態を検出して、表示部が
開いていたらクロック制御信号302をオフにして、表
示部が閉じていたらクロック制御信号302をオンにす
る. 第4図は、クロック周波数選択回路で、信号402は第
3図の信号302と、信号405は信号304とそれぞ
れ同じであり、第5図は回路のタイミング図である. 第4図において401はクロック信号で、第5図では4
0で示される.信号40をフリップフロップ4003で
1/2分周し、信号42を生或する、信号40と42の
ノア4004をとり信号43を生成し信号44.45の
立ち上がるタイミング1+を信号40のたちあがりより
半周期進めている。これは4007.4008のアンド
で信号40の1/2の周波数の信号42,信号43との
アンドを信号44.45とそれぞれとることでクロック
を選択しているため、信号44.45がクロックの周期
の途中で変化してしまうとクロック周期の途中からクロ
ック周波数が変化してしまうので、これを防ぐためであ
る. アンド4007では信号43によってたちあげられた信
号44とクロック周波数401を1/2分周した信号4
2のアンドをとり、アンド4008では、同様に信号4
5とクロック周波数401に等しい信号40のアンドを
とっている.つまりクロック制御信号41のオン、オフ
によって、信号44、45のどちらかがオンになり40
07、4008のアンドと4009のノアによってクロ
ック周波数401か、その2分の1の周波数をクロック
信号46として出力する. 次にクロック制御信号41のオン、オフによって出力信
号46がどのように変化するかを第5図によって示すと
、tsでクロック制御信号がハイレベル(表示部が閉じ
た状態〉になるとフリップフロップ4005に入力され
るクロック制御信号43がオンになる1+で、信号44
と45は反転し信号44がハイレベルになる.すると信
号42が出力される.またt2でクロック制御信号41
がローレベル(表示部が開いた状態)になるとフリップ
フロップ4005に入力される信号43がオンになるt
3で信号44と45は反転し、信号45がハイレベルに
なる.すると信号40が出力信号となる. このようにしてクロック周波数を制御できる.表示部を
開閉させることで、実施例を説明したが表示部を動かさ
なくても、一定時間キー人力がなければタイマー機能を
作動させて一定時間後にクロック信号を変化させてもよ
く、電源電池の電圧が一定値以下に低下したときにクロ
ック信号を下げて使用してもよい. クロック信号を上げるか下げるかについては、キ一人力
等が無い時に、速い処理を必要とする場合と、また反対
に実施例のように速い処理を必要としない場合があるた
め、本発明は機器の使用状態に応じてクロック信号を変
え機器の使用効率を高めるものである。
"Means for Solving the Problems" The present invention includes a detection means for detecting an inoperative state of an apparatus, a clock frequency control means for controlling a clock signal by the detection of the detection means, and a clock frequency control means for controlling a clock signal by the signal of the clock frequency control means. The present invention is characterized by comprising at least clock frequency selection means for selecting the clock frequency. Embodiment j Below, as an embodiment of the present invention, an electronic computer in which the clock frequency is switched by opening and closing the display section will be explained based on the drawings. Fig. 1 shows the configuration of the present invention. Operating state for detecting the operating state It is composed of a detection means 10, a clock control means 1l which outputs a signal for selecting a clock frequency corresponding to the operating state, and a frequency selection means 12 which selects a frequency based on the signal.Output 13 from the clock frequency selection means 12. The CPU is turned on. Fig. 3 is a block diagram of the embodiment, in which the CPU 31 executes a program to check the status of the display unit from the R○M 32 by an interrupt from the switch 30, and checks the open/closed status of the display unit based on the clock frequency. When the state of the clock frequency control register 34 written in the control register 34 changes, the clock frequency control means 35, which constantly monitors the state of this register 34, changes the open/closed state of the display section from the on/off state of the bit of the clock frequency control register 34. If the display section is open, the clock control signal 302 is turned off, and if the display section is closed, the clock control signal 302 is turned on. Signal 302 and signal 405 in Figure 3 are the same as signal 304, and Figure 5 is a timing diagram of the circuit. In Figure 4, 401 is a clock signal;
Indicated by 0. Divide the signal 40 in half by a flip-flop 4003 to generate a signal 42.Nor 4004 of the signals 40 and 42 to generate a signal 43, and set the rising timing 1+ of the signal 44. The cycle is progressing. This is because the clock is selected by ANDing the signals 42 and 43, which have a frequency of 1/2 of the signal 40, with the signals 44.45 and 4007.4008, so the signal 44.45 is the clock. This is to prevent the clock frequency from changing in the middle of the clock cycle if it changes in the middle of the cycle. In the AND 4007, the signal 44 raised by the signal 43 and the signal 4 obtained by dividing the clock frequency 401 by 1/2
2 and 4008, similarly, signal 4 is
5 and a signal 40 equal to the clock frequency 401. In other words, depending on whether the clock control signal 41 is turned on or off, either the signal 44 or 45 is turned on and the signal 40 is turned on.
The AND of 07 and 4008 and the NOR of 4009 output the clock frequency 401 or a half thereof as the clock signal 46. Next, how the output signal 46 changes depending on whether the clock control signal 41 is turned on or off is shown in FIG. At 1+, the clock control signal 43 input to the
and 45 are inverted, and signal 44 becomes high level. Then, signal 42 is output. Also, at t2, the clock control signal 41
When becomes a low level (the display section is open), the signal 43 input to the flip-flop 4005 turns on.
At 3, signals 44 and 45 are inverted, and signal 45 becomes high level. Then, signal 40 becomes the output signal. In this way, you can control the clock frequency. Although the embodiment has been explained by opening and closing the display part, even if the display part does not move, if there is no key manual power for a certain period of time, the timer function can be activated and the clock signal can be changed after a certain period of time. The clock signal may be lowered and used when the voltage drops below a certain value. Regarding whether to raise or lower the clock signal, there are cases where fast processing is required when one person has no power, and there are cases where fast processing is not required as in the embodiment. The clock signal is changed depending on the usage status of the equipment to increase the usage efficiency of the equipment.

「発明の効果」 以上説明したように本発明によれば、表示部の開閉、あ
るいは装置をしばらく使わないことを検出してクロック
周波数を切換えることで、使用中断後のプログラムロー
ド時間を省くことができ、また、断続的な使用での消費
電力を低減できるためポータブルコンピュータの弱点で
あるバッテリーによる動作可能時間を延ばすことができ
、表示体の寿命を延ばすことができる。
"Effects of the Invention" As explained above, according to the present invention, by detecting opening/closing of the display section or not using the device for a while and switching the clock frequency, it is possible to save program loading time after interruption of use. In addition, since power consumption during intermittent use can be reduced, the operating time of batteries, which is a weak point of portable computers, can be extended, and the life of the display body can be extended.

【図面の簡単な説明】[Brief explanation of drawings]

を示す図、第3図は本預明の一実施例のブロック図、第
4図はクロック周波数を選択するクロック周波数選択回
路の回路図、 回路のタイミング図ゆ 第5図は、 周波数選択 10 11 12 作動状態検出手段 クロック周波数制御手段 クロック周波数選択手段 401 402 403 404 クロック信号 クロック制御信号 電源オン信号 リセット信号 以上
Figure 3 is a block diagram of an embodiment of this invention, Figure 4 is a circuit diagram of a clock frequency selection circuit that selects a clock frequency, and Figure 5 is a timing diagram of the circuit.Frequency selection 10 11 12 Operating state detection means Clock frequency control means Clock frequency selection means 401 402 403 404 Clock signal Clock control signal Power on signal Reset signal or higher

Claims (1)

【特許請求の範囲】 装置の不作動状態を検出する検出手段と、 前記検出手段の検出によってクロック信号を制御するク
ロック周波数制御手段と、 前記クロック周波数制御手段の信号によって前記クロッ
ク周波数を選択するクロック周波数選択手段とを少なく
とも備えたことを特徴とする情報処理装置。
[Scope of Claims] Detection means for detecting an inoperative state of the device; Clock frequency control means for controlling a clock signal based on detection by the detection means; and a clock for selecting the clock frequency based on a signal from the clock frequency control means. An information processing device comprising at least frequency selection means.
JP1192878A 1989-07-26 1989-07-26 Information processor Pending JPH0357007A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1192878A JPH0357007A (en) 1989-07-26 1989-07-26 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1192878A JPH0357007A (en) 1989-07-26 1989-07-26 Information processor

Publications (1)

Publication Number Publication Date
JPH0357007A true JPH0357007A (en) 1991-03-12

Family

ID=16298481

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1192878A Pending JPH0357007A (en) 1989-07-26 1989-07-26 Information processor

Country Status (1)

Country Link
JP (1) JPH0357007A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7577417B2 (en) 2002-04-03 2009-08-18 Hitachi, Ltd. Mobile terminal

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7577417B2 (en) 2002-04-03 2009-08-18 Hitachi, Ltd. Mobile terminal

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