JPH0355050B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a pulse generator that generates a rectangular wave pulse whose pulse edge phase can be controlled.

[Problems with conventional technology]

It is well known to convert analog signals into digital form by digitizing the analog signals in two successive switching stages using dual flash type (series-parallel) analog-to-digital converters. In this analog-to-digital conversion method,
The digital output of the first conversion stage is converted to analog form, subtracted from the input analog signal and the difference signal is provided to the second conversion stage, which combines the outputs of these two conversion stages to form the desired digital I'm getting a signal. To compensate for the propagation delay of the first conversion stage and the digital-to-analog converter, the input analog signal is fed to the subtracter via a delay line. The digital outputs of the two conversion stages must each represent the level of the input analog signal (upper bits) and the level of the corresponding difference signal at the same time (lower bits), so the analog signals are converted through a sample and hold circuit. is supplied to the vessel. However, conventional sample and hold circuits have the disadvantage that they degrade analog signals to an unacceptable degree in some applications. By clocking the second conversion stage with a delay to the clocking of the first conversion stage, a sample and hold circuit can be omitted. In this case, the delay of this clock signal must be equal to the delay due to the delay line, but the delay line can be adjusted or the phase of the clock edges can be adjusted to make these delays equal. However, variable delay lines are generally much more expensive than fixed delay lines, and variable delay lines are difficult to adjust accurately.

High speed (10MHz) like a conventional high speed clock generator
(above) circuits do not have accurate and stable voltage characteristics like low frequency (10KHz or less) circuits. One problem with this limitation in conventional high speed circuits is that they cannot accurately control and adjust the phase of the pulse edges of the clock signal produced by the high speed clock generator.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a square wave pulse generator in which the phase of the pulse edges can be precisely controlled and adjusted.

[Means and actions for solving problems]

The square wave pulse generator of the present invention includes a comparator and a circuit for generating a series of voltage pulses in which at least one of the pulse edges having a leading edge and a trailing edge is generally ramped. This comparator has a first input terminal supplied with this series of voltage pulses, a second input terminal supplied with a DC voltage level corresponding to the DC voltage of the output pulse of the comparator and a variable DC voltage, and this series of voltage pulses. A signal having one or two voltage levels is generated at the output depending on whether the voltage level of the pulse exceeds this DC voltage level or not. This comparator thus generates at its output a repetitive rectangular wave signal whose transition, ie the phase of at least one of the leading and trailing edges, is determined by the DC voltage level.

〔Example〕

Hereinafter, the present invention will be specifically explained based on illustrated embodiments.

FIG. 1 is a circuit diagram showing a preferred embodiment of the present invention, and FIG. 2 is a waveform diagram for explaining the dynamic difference thereof. The oscillator 10 generates a repetitive output signal (waveform a in FIG. 2) whose frequency is stable because the frequency is determined by the interval between zero volt crossing points of the output waveform, but whose voltage waveform is unstable. The output signal from the oscillator 10 is supplied to the non-inverting input terminal (+) of the comparator 12, and the inverting input terminal (-) of the comparator 12 is grounded. Therefore, comparator 12 produces a square wave output such that the falling edge of the pulse occurs midway between the rising edge and the edge of the pulse. In this specification, the term "square wave" refers to a repetitive wave having two voltage levels and transitions between these two voltage levels almost instantaneously, so that when this waveform is displayed on a conventional oscilloscope, , voltage levels are represented by horizontal lines and transitions are represented by vertical lines. On the other hand, the term "square wave" means a square wave with an impulse factor (ratio of the period of one level to the total period of the waveform of one cycle...duty cycle) of 50%. The output waveform of the comparator 12 is shown in FIG. 2 as waveform b. Comparator 1 via low-pass filter 16
2 is applied to the non-inverting input (+) of the second comparator 14. The time constant of this low pass filter 16 is much longer than the half period of the square wave output signal of the comparator 12. Therefore, the signal supplied to the non-inverting input terminal (+) of the comparator 14 has the waveform c in FIG.
The rising and falling edges of this waveform have a limited slew rate. A DC voltage (waveform d in FIG. 2) generated as described later is applied to the inverting input terminal (-) of the comparator 14. Therefore, as shown as waveform e in FIG. 2, the impact coefficient of the output signal generated at the non-inverting output terminal of the comparator 14 is determined according to the level of this DC voltage d. As shown in comparison to FIGS. 2A and 2B, the phase of the falling edge relative to the rising edge can be varied. Second
In FIGS. A and 2B, the level of the DC voltage signal d is different. Note that the circuits 10, 12, and 16 constitute pulse generating means according to the present invention.

The DC signal applied to the inverting input (-) of comparator 14 is generated in a feedback loop. This feedback loop includes low-pass filters 18 and 20 connected to the inverting and non-inverting outputs of the comparator 14, respectively, and the inverting input (-) and non-inverting input (+) of the comparator 14 to the low-pass filters 18 and 20, respectively. and 20, respectively.
The inverting input (-) of amplifier 22 is connected to potentiometer 24 via resistor 26 . The value of this resistor 26 is much larger than the values of the resistors in filters 18 and 20. The output terminal of the amplifier 22 is connected to the inverting input terminal (-) of the comparator 14.

The signals generated by low pass filters 18 and 20 are:
These are the DC levels (average levels) of the two output signals generated by the comparator 14, respectively.

The DC level of each output signal generated by the comparator 14 is determined depending on the impulse coefficient of the signal generated at the non-inverting output terminal of the comparator 14.
Since we are combining two DC levels at
The effects of temperature and supply voltage dependent variations in the output voltage level of the comparator can be removed by common mode rejection.

Since the level of the DC voltage supplied to the inverting input (-) of the comparator 14 can be shifted by the potentiometer 24, the duty factor of the non-inverting output signal from the comparator 14 can be adjusted. Since the resistance value of resistor 26 is large, this resistor 26 acts as a current source. Therefore, potentiometer 24 does not significantly affect the correction made by the common mode rejection action of amplifier 22. Note that the circuits 18 to 26 serve as DC voltage level generating means according to the present invention.

The illustrated square wave pulse generator can be used to generate clock pulse signals having clock edges (negative or positive) whose phase can be precisely controlled and adjusted. That is, this pulse generator can be used to generate precisely delayed clock pulses for the second conversion stage of a dual flash analog-to-digital converter. The clock pulse for the first conversion stage is also obtained from the output of comparator 12.

The present invention can be modified in various ways without departing from the spirit thereof, and the embodiments described above are not intended to limit the present invention in any way. For example, since it is generally only necessary to change the phase of one edge of the output signal of the comparator 14, both edges of the signal fed to the non-inverting input (+) of the comparator 14 need to be sloped. There isn't.

〔Effect of the invention〕

As mentioned above, in accordance with the present invention, the non-inverted and inverted square wave output signals from the comparator circuit are
The duty factor of the square wave output signal is unaffected by temperature- and power supply voltage-dependent fluctuations of the comparator circuit, since the filters provide an average DC level, which is combined in an operational amplifier and then fed back to the inverting input of the comparator circuit. Furthermore, by appropriately selecting the voltage of the potentiometer connected to one input terminal of the operational amplifier, the DC level supplied to the non-inverting input terminal of the comparator circuit can be made equal to the gradient wave signal from the first low-pass filter. Since it can be adjusted crosswise over a range of amplitudes, the impulse coefficient of the output square wave can be arbitrarily selected over the entire range.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a preferred embodiment of the present invention, and FIGS. 2A and 2B are waveform diagrams for explaining the operation of FIG. 1. In the figure, 14 is a comparator, 16 is a first low-pass filter, 18 and 20 are second and third filters,
22 is an operational amplifier, and 24 is a potentiometer.

Claims (1)

[Claims] 1. A first low-pass filter to which a square wave input signal is supplied; and a comparison device in which the output signal of the first low-pass filter is supplied to a non-inverting input terminal and outputting non-inverting and inverting output signals. a circuit, second and third filters to which said non-inverting and inverting output signals of said comparator circuit are respectively supplied; output signals of said second and third filters being respectively supplied to non-inverting and inverting input terminals, said It has an operational amplifier that supplies an output signal to the inverting input terminal of the comparator circuit, and a slider connected to either the non-inverting or inverting input terminal of the operational amplifier, and the slider is connected to either the non-inverting or inverting input terminal of the operational amplifier, and the slider is connected to the non-inverting input terminal or the inverting input terminal of the operational amplifier, and the slider is connected to either the non-inverting input terminal or the inverting input terminal of the operational amplifier. and a potentiometer for supplying a square wave pulse generator.