JPH0354865B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit in which a switching regulator is formed on a chip on which a high withstand voltage element circuit and a low withstand voltage element circuit are formed.

Transistors constituting semiconductor integrated circuits are increasingly becoming fine-patterned due to demands for higher speeds and lower power consumption. Along with this, the withstand voltage of the transistor decreases, so the power supply voltage also decreases.

[Prior Art] As mentioned above, the withstand voltage of transistors forming a semiconductor integrated circuit is lowered, and it is necessary to lower the power supply voltage supplied from the outside. However, if the operating power supply voltage of some ICs is low, other existing ICs may
The power supply cannot be shared with the IC, and a separate power supply must be prepared. In addition, if large transistors are used in areas that require high driving capacity, such as output circuits, and fine transistors are used in logic circuits that require high speed and low power, two power supplies are required due to the difference in gate breakdown voltage. The problem arises that .

It is also possible to divide the power supply voltage by resistors to provide a transistor circuit with a low gate withstand voltage, but this does not allow for lower power consumption.

[Problem that the invention seeks to solve]

As mentioned above, miniaturization of the transistors that make up an IC conventionally required a separate power supply, and there were also problems in that it was not easy to mix them with current ICs.

[Means for solving problems]

The present invention provides a semiconductor integrated circuit that solves the above problems, and its means include a switching regulator on a semiconductor chip, and uses the switching regulator to receive a power supply voltage supplied from the outside. This is achieved by a semiconductor integrated circuit characterized in that the voltage is stepped down and supplied to internal circuits as an operating power supply voltage.

The internal circuit includes a first circuit formed of low voltage transistors and a second circuit formed of transistors with higher voltage resistance than the low voltage transistors, and the first circuit includes a switching regulator. Preferably, the output voltage of the generator is applied as the operating power supply voltage, and the second circuit is supplied with a power supply voltage supplied from the outside.

[Effect]

The above semiconductor integrated circuit has a built-in switching regulator to step down the power supply voltage and provide a low voltage to the circuit, so there is no need to provide a separate low voltage source as in the past, and the power consumption of the entire device increases. Consumption is low, high density and high speed can be achieved, and it is easy to mix with conventional circuits.

〔Example〕

Hereinafter, the present invention will be explained by way of examples with reference to the accompanying drawings.

FIG. 1 is a circuit configuration diagram of a semiconductor integrated circuit 1 according to the present invention, which includes a high-voltage element circuit 11,
It is composed of a low breakdown voltage element circuit 12 and a switching regulator 13.

The high voltage element circuit 11 is a circuit made up of elements with high voltage resistance such as an output circuit, and is directly applied with the conventional power supply of 5 [V].

The low breakdown voltage element circuit 12 is a logic circuit and is composed of elements with low breakdown voltage, and includes a switching regulator 13.
The above 5 [V] is stepped down and 2 [V] is applied.

FIG. 2 is a circuit diagram showing a first embodiment of the switching regulator 13.

The circuit in Figure 2 consists of an oscillator OSC, N-channel enhancement type MOS transistors Q ₁ and Q ₂ , an inverter INV, a comparator COMP, and a capacitor C ₁ ,
Consists of C ₂ .

The operation of the first embodiment having the above configuration will be explained based on the waveform diagram of FIG. 3.

The oscillator OSC generates the pulse signal shown in Figure 3a.
Pa inputs to the gate of transistor _Q1 . This gate input Pa is inverted by the inverter INV.
It becomes Pb (Fig. 3b) and is input to the gate of transistor _Q2 .

Since the transistor Q ₁ is of the N-channel enhancement type, it is turned on when the gate input Pa becomes H, and conduction occurs between the high voltage 5 [V] in _FIG . 1 and the capacitor C ₁ . Therefore, charge is gradually accumulated in the capacitor _C1.In proportion to the amount of charge accumulated, while the gate input Pa is H, the potential at the connection point C gradually increases as shown in Figure 3c. do.

On the other hand, while the gate input Pa is H, the transistor
Since the gate input Pb of Q ₂ is L (the third
In Figure b), the N-channel enhancement type transistor _Q2 is in the off state. Capacitor C ₂ therefore discharges the previously stored charge to ground. In proportion to this decrease in discharge amount, the potential at the connection point d also falls below the reference potential _Vref , as shown in FIG. 3d.

This reference potential is 2 [V], and while the potential at the connection point d is lower than this 2 [V], the comparator COMP is at the low level.
The output (Figure 3e) is inverted and input to the oscillator OSC, which continues to operate and the gate input Pa maintains the H state (Figure 3a).

However, when the gate input Pa becomes L (FIG. 3a), the transistor _Q1 is turned off and no charge is stored in the capacitor _C1 . At this time, the gate input Pb of the transistor _Q2 is inverted by the inverter INV and becomes H (FIG. 3b). Therefore, transistor Q ₂ is turned on, conduction occurs between capacitors C ₁ and C ₂ , and the charge stored in C ₁ flows to C ₂ ,
The potential at the connection point d begins to rise (FIG. 3d).

The potential at the connection point d becomes equal to the reference potential _Vref at the point in time, and when it rises further, the output signal Pe from the comparator COMP becomes H (Fig. 3e), and the inverted L
A signal enters the oscillator OSC.

Therefore, the operation of the oscillator OSC is stopped and the transistor _Q1 remains in the off state (FIG. 3a). If the oscillator OSC continues to stop, no charge is supplied to the capacitor _C1 , so even if the transistor _Q2 is conductive, the potential at the connection point d gradually decreases until it becomes equal to the reference potential _Vref again. Figure 3 d).

After that, when the potential at the connection point d falls below the reference potential of 2 [V], the L output of the comparator COMP is inverted and input to the oscillator OSC, and the oscillator OSC starts operating again, and as shown by the arrow, the transistor
Gate input Pa of Q ₁ becomes H (Fig. 3 d, e,
a).

After that, the switching regulator 13 repeats the same operation as described above, increasing the high voltage from 5 [V] to 2 [V].
2 [V] is taken out from the connection point d and input to the low voltage element circuit 12.

FIG. 4 is a circuit diagram showing a second embodiment of the switching regulator 13. Figure 2, 1st
The difference from the embodiment is that two N-channel enhancement type MOS transistors Q ₃ and Q ₄ and one capacitor C ₃ are added. According to this second embodiment, charge is accumulated in the newly provided capacitor C ₃ due to the on/off operation of the transistor Q ₃ whose gate input Pb (FIG. 3b) lags behind the gate input Pa of the transistor Q ₁ . be done. Therefore, the voltage waveform at the new connection point f is also the same as the voltage waveform at the connection point C (FIG. 3e), but with a delay. On the other hand, transistors Q ₂ and Q ₄ also repeat their on/off operations at different times. Therefore, the voltage waveform at the connection point d is smaller than that in the first embodiment (Fig. 3d).
The second embodiment is smoother.

FIG. 5 is a circuit diagram of the third embodiment. In this embodiment, transistor Q ₁ is a P-channel enhancement type transistor, and both transistors Q ₁ and Q ₂ constitute a complementary type transistor. Unlike the first and second embodiments (Figs. 2 and 3), each gate input Pa of transistors Q ₁ and Q ₂
Pb has the same waveform, but since _Q1 and _Q2 operate in opposite directions, the waveforms at the connection points c, d, and e are the same as those shown in FIG. 3c, d, and e. Unlike the first embodiment, there is no inverter INV and capacitor _C2 , so
The circuit configuration has become simpler.

FIG. 6 shows an application example of the present invention, in which a semiconductor substrate
A power supply V _BB GEN is installed to apply a negative bias voltage to SB, and the oscillator of that power supply
The OSC is shared by the regulator 13 of the present invention, and the capacitor C of the regulator 13 is externally attached.

〔Effect of the invention〕

According to the present invention, by incorporating a switching regulator, it is possible to efficiently step down a high voltage and provide a low voltage to the circuit, so there is no need to separately provide a low voltage source as in the past. As a result, the power consumption of the entire device is reduced, high density and high speed can be achieved, and it is easy to mix use with conventional circuits.

[Brief explanation of drawings]

FIG. 1 is an overall configuration diagram of the integrated circuit of the present invention, and FIG.
The figure is a block diagram showing the first embodiment of the switching regulator shown in Fig. 1, Fig. 3 is a waveform diagram of each part of the circuit shown in Fig. 2, and Figs. 4 and 5 are respectively the switching regulator. FIG. 6 is a block diagram showing a second and third embodiment of the controller, and FIG. 6 is a block diagram showing an application example of the device of the present invention. 1... Semiconductor integrated circuit according to the present invention, 11...
High voltage element circuit, 12...Low voltage element circuit, 13
... Switching regulator, Q ₁ ... First transistor, Q ₂ ... Second transistor, C ₁ ...
capacitor.

Claims (1)

[Claims] 1. A first circuit formed of a low voltage transistor on a semiconductor substrate, a second circuit formed of a transistor with a higher voltage resistance than the low voltage transistor, and an oscillator for generating substrate bias. a substrate bias generation circuit that applies a substrate bias voltage to the semiconductor substrate in response to the oscillator output; and a switching regulator that operates in response to the oscillator output and steps down an externally supplied power supply voltage. the first circuit is supplied with the output voltage of the switching regulator as an operating power supply voltage, and the second circuit is supplied with a power supply voltage supplied from the outside. Features of semiconductor integrated circuits.