JPH0354497B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data communication system for exchanging data between data terminal devices.

2. Description of the Related Art Conventionally, there has been a method of using a power distribution line as a communication line as a simple and inexpensive method of data communication without using a dedicated line. However, the method of using power supply distribution lines as communication lines is only applicable to systems where there is no problem even if some data errors occur because the line contains a lot of noise, such as communication between computers. It has been difficult to apply it to data communications that require high speed and high reliability.

The purpose of this invention is to reduce the number of
The object of the present invention is to provide a data communication method that enables high-speed communication of about 10 kilobits per second or more and high-quality communication with a bit error rate of 10 ^{-3 or} more.

In order to achieve the above object, the data communication system of the present invention includes a communication control unit, a CPU, and a memory between each data terminal device and a line, and N times the desired communication speed of data communication between the data terminal devices. A communication device is provided which performs communication at a communication speed of Data with a synchronization character as one unit is transmitted sequentially, and the receiving side communication device receives the transmitted unit data, and only if there is no error, moves the data to the address position corresponding to the address of the received data in its own memory. In addition to storing the above-mentioned several character data, the address, an acknowledgment code indicating normal reception, an error control code, and data in which the synchronization character is one unit are transmitted to the sending side, and if there is an error, the address and The data including the disapproval code, error control code, and synchronization character as one unit are returned to the sending side, and the communication device on the sending side manages a memory address when the returned unit data is normally received, and then sends the data. The retransmission process is repeated until confirmation that all the received data has been successfully received.

The present invention will be explained in detail below with reference to embodiments shown in the drawings.

FIG. 1 is a block diagram of a communication system using indoor power distribution lines in which the present invention is implemented. In the figure, communication devices T1, T2, ..., Tn are provided between each data terminal device DT1, DT2..., DTn and an indoor power distribution network L as a communication line, and the communication devices T1, T2..., Tn are provided respectively. coupler C1, respectively;
It is connected to the indoor power distribution network L via C2, . . . , Cn.

FIG. 2 shows communication devices T1, T2, . . . shown in FIG. 1.
FIG. 3 is a block diagram showing an example of Tn. The communication device T shown here includes two CPUs 1 and 2, two communication control units 3 and 4, and a 2-port memory 5.
The communication control unit 3 is connected to the CPU 1 and the 2-port memory 5 by bus B1, and the communication control unit 4 is connected to bus B2.
is connected to the CPU 2 and the 2-port memory 5. In addition, the communication control unit 3 is a data terminal device DT.
The communication control section 4 is connected to a modem 6.
Further, the CPUs 1 and 2 are configured to be able to interrupt each other via interrupt signal lines IT1 and IT2. 2
The CPUs 1 and 2 are designed to control the communication control units 3 and 4 while transferring data generated in the process via the two-port memory 5.

Although only one communication device is shown in FIG. 2, when data is transferred between data terminal devices, transmission and reception operations are performed with communication devices installed in other data terminal devices. It is done. Transmission and reception between the communication devices is full-duplex, and communication is performed at a speed three times (N times) the desired communication speed.

Next, refer to the time chart shown in Figure 3.
Transmission and reception operations between two data terminal devices will be explained.

In FIG. 3, aDTE→P1 shows a state in which transmission block 1 is transmitted from the terminal device DT to the CPU 1 in the form of serial data. The CPU 1 converts this transmission block 1 into parallel data and writes it into the 2-port memory 5. This state is shown in Figure 3, written in g2PM. Further, the CPU 1 generates a transmission start interrupt to the CPU 2 to notify the CPU 2 that writing to the 2-port memory 5 has started [see FIG. 3e]. Upon receiving this interrupt, the CPU 2 retrieves the stored transmission block 1 data from the 2-port memory 5, converts the communication content, and transmits it as serial data to the other party's data terminal device via the modem 6 (Fig. 3c). reference〕. Transmission block 1
When all transmissions (including retransmissions) are completed, the CPU
2 generates a transmission end interrupt to the CPU 1 [see Figure 3 f].

Next, the own data terminal device DT expects to receive reception block 1 as a response. CPU2
When it starts receiving the reception block 1 from the other party's communication device (see Figure 3 d), it converts the data into parallel data and sequentially writes it into the 2-port memory 5 (see Figure 3 g). And CPU2 is CPU
1, a reception start interrupt is generated (see Figure 3 f). Upon receiving this interrupt, the CPU 1 sequentially reads the data from the 2-port memory 5 in the original order of data characters (see Figure 3 h), converts the communication content, and converts the data into serial data to the own data terminal.
Inform the DT [see Figure 3b]. Reception block 1
When the reception of the data is completed, the CPU 1 generates a reception end interrupt to the CPU 2 [see FIG. 3e].

When transmitting data between two data terminal devices, it is first necessary to establish a data link, that is, confirm the start of data communication.

FIG. 4 shows a time chart when establishing a data link.

Next, the operation when establishing a data link will be explained with reference to FIG. In FIG. 4, S is a synchronization character SYZ, E is a data link establishment request ENQ, B is an error control character BCC,
A indicates the data communication acknowledgment character ACK.

First, the own data terminal device DT sends the synchronization character SYN, the own data terminal device number F1, the other party's data terminal device number F2, and a data link establishment request.
Each ENQ code is sent to the CPU 1 at the desired communication speed and stored in the 2-port memory 5 [see Figure 4a]. When the CPU 1 receives the code signals SYN, F1, F2, and ENQ, it interrupts the CPU 2 and instructs it to send the data in the two-port memory 5 onto the power distribution network L (see FIG. 4b). In response to this interrupt, the CPU 2 takes out the data from the two-port memory 5, converts it to three times the communication speed, adds an error control character BCC to the data shown in FIG. 4a, and sends it to the other party.

The data terminal device of the other party receives the code shown in FIG. 3c via the communication device, and sends a synchronization character SYN,
The CPU 2 receives the own data terminal device number F2, the other party's data terminal device number F1, the data communication acknowledgment character ACK, and the error control character BCC (see FIG. 4d). Fourth
The order of the data terminal equipment numbers F1 and F2 in Figures c and 4d is reversed because the transmitting and receiving data terminal equipment is reversed. In addition, in the above, the data terminal device number is
The reason why F1 and F2 are included is to clearly identify the communication partner when a plurality of data terminal devices are installed as shown in FIG.

If an error occurs due to the above communication overshoot, repeat steps c and d in FIG. When the contents of FIG. 4 d are normally confirmed by CPU 2, CPU 2 generates an interrupt to CPU 1 [see FIG. 4 e]. The CPU 1 retrieves SYN, F2, F1, and ACK from the two-port memory 5 and transmits them to its own data terminal device DT (see FIG. 4 f), thereby establishing a data link.

Once the data link is established, data transmission begins. FIG. 5 shows a time chart of data transmission and retransmission in case of error.

Figure 5a shows the format of the transmission contents from the CPU 2 to the other party's data exchange device, in which the synchronization character SYN, memory address, two data characters, and error control character BCC are 1.
Sent as unit data. In the illustrated example, first 2
data characters Dn, Dn+1 and a memory address Mn representing the memory addresses of these two data characters are transmitted, and the next unit is 2 data characters Dn, Dn+1.
data characters Dn+2, Dn+3 and these two
As long as the memory address Mn+2 representing the memory address of the data character is transmitted, and as long as the communication device of the other party continues to respond to this data transmission with the acknowledgment signal ACK, the CPU 2 will transmit the representative memory address Mn, Mn+2, Mn+2, Mn+4, Mn
Data including +6... will be sent.

However, as shown in Figure 5b, CPU2
If a response is received to Mn disapproval i.e. synchronization character SYN, memory address Mn, disapproval response
When receiving data with NACK and error control character BCC as one unit, CPU 2 assumes that an error has occurred during Mn transmission and sends SYN, Mn, Dn, Dn following Mn+2 transmission as shown in Figure 5a.
+1, resend BCC. In Figure 5b, Mn is an error, Mn+2 is approved, and then Mn is approved by retransmission, so there are a total of 4 data characters Dn,
It is confirmed by memory addresses Mn and Mn+2 that Dn+1+Dn+2 and Dn+3 have been transmitted normally. In this way, when all representative memory addresses are confirmed, the transmission of the predetermined data ends.

Note that the data transmission and reception shown in FIG. 5 is performed between the own communication device and the other party's communication device, and the other party's communication device also naturally performs the transmission and retransmission shown in FIG.

Further, as described above, communication between communication devices is performed at a speed three times the desired communication speed, and the time difference from the desired communication speed is used for error control, that is, retransmission. Furthermore, the address of the two-port memory 5 is managed by a synchronous communication method between the CPUs in the communication device, so that the communication content is converted regardless of the data content. Furthermore, even in retransmission processing, communication is performed only by managing memory addresses.

Furthermore, it is of course possible that the content received by the CPU-2 contains a BCC error, but in this case, check the order of the memory addresses Mn that were normally received by the own data terminal device DT, and check if the memory is empty. Address data should be sent with priority.

FIG. 6 shows a memory map of the two-port memory 5 in each operating state in the above embodiment. 6th
Figure a shows the memory contents in the initial clear state, that is, at the time of transmission or reception start interrupt, and the synchronization character SYN is written in all areas.
Figure 6b shows the case where transmission data D1, D2...Dn are added to the CPU 1 from the data terminal device and written to the memory storage areas M1, M2...Mn, or transmitted from the other party's data terminal device. A case is shown in which data contents D1, D2...Dn are written to storage areas M1, M2...Mn of the memory. Figure 6c shows the memory contents when the data link is established, and here the own data terminal device number is shown.
F1, partner data terminal device F2, and request code ENQ are stored. FIG. 6d shows the memory contents when there is a request to establish a data link from another data terminal device and the own data terminal device responds to the request. Compared to the case of FIG. 6c, the other party's data terminal device number F2 and own data terminal device number F1
is reversed and also includes the acknowledgment code ACK.

In the above embodiment, the communication device T includes two CPUs 1 and 2 and a communication control section 3, as shown in FIG.
Although we have explained the case where communication contents are converted using this communication device, as shown in FIG. Alternatively, the data may be transferred via the memory 15 by performing data communication using the same communication procedure and speed.

Also, instead of the communication device shown in FIG. 2, as shown in FIG.
24, shared memory 25, gates 26, 2
A communication device that transfers data via 7 may also be used. However, the communication device shown in FIG. 2 is the most superior in that the delay in transfer time is small.

According to the data communication method of the present invention, transmission data is sent by including several characters and a memory address in one unit of data, and the communication device on the transmission side uses the memory address when the unit of data that is returned is normally received. The system manages the data and repeats retransmission until confirmation that all transmitted data has been received correctly, so even if an error occurs during transmission, retransmission ensures that data can be sent and received. I can do it. Furthermore, high-speed communication is possible because data is exchanged between communication devices at a communication speed N times the desired communication speed between data terminal devices. Therefore, when the data communication system of the present invention is applied to communication using a power line, high-speed, high-quality communication can be performed even if data errors occur due to noise in the power line.

If it is assumed that the probability of impulse occurrence is constant in the case of a power supply line at N times the communication speed, and the communication time is the same compared to the desired communication speed, errors will generally increase due to the width of the impulse. However, by segmenting data and sending it as in this invention, the probability of errors occurring for each unit of data including memory addresses is reduced, and data communication can now be performed using power supply distribution lines, which were previously considered unsuitable. It can be done effectively.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a communication system using indoor power distribution in which the present invention is implemented, Fig. 2 is a block diagram showing an example of the communication device shown in Fig. 1, and Fig. 3 is a data terminal device shown in Fig. 1. Figure 4 is a timing chart for explaining the transmission and reception operations during the same period, Figure 4 is a time chart including the data format when establishing the same data link, Figure 5 is the time chart including the data format for the same data transmission and retransmission in case of an error. 6 is a diagram showing a memory map of each operating state in the embodiment shown in FIGS. 1 and 2,
FIGS. 7 and 8 are block diagrams showing other examples of the communication device shown in FIG. 1. DT (DT1, DT2..., DTn): Data terminal device, T (T1, T2...Tn): Communication device, C1, C
2...Cn: coupler, L: power distribution network, 1, 2,
11, 21, 22: CPU, 3, 4, 13, 14,
23, 24: Communication control unit, 5: 2 port memory,
15: Memory, 25: Shared memory, 26, 27:
Gate.

Claims (1)

[Claims] 1 A data communication method that exchanges data between data terminal devices via a line, and includes a communication control unit, a CPU, and a memory between each data terminal device and the line. A communication device that performs communication at a communication speed N times the desired communication speed is provided, and the communication device on the sending side stores the data to be transmitted from the data terminal device in the memory, and also stores the address and number of this memory. Character data, an error control code, and a synchronization character are sequentially transmitted as one unit, and the receiving communication device receives the transmitted unit data and stores the received data in its own memory only if there is no error. The several character data is stored in the address position corresponding to the address of , and the address, an acknowledgment code indicating normal reception, an error control code, and data in which the synchronization character is one unit are returned to the sending side, and the error is detected. If there is, the data containing the address, rejection code, error control code, and synchronization character as one unit is returned to the sending side, and the sending side communication device normally receives the returned unit data. A data communication method that is characterized by managing the memory addresses of the data and repeating retransmissions until confirmation that all transmitted data has been successfully received.