JPH0353612A - Comparing circuit - Google Patents

Comparing circuit

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Publication number
JPH0353612A
JPH0353612A JP1189106A JP18910689A JPH0353612A JP H0353612 A JPH0353612 A JP H0353612A JP 1189106 A JP1189106 A JP 1189106A JP 18910689 A JP18910689 A JP 18910689A JP H0353612 A JPH0353612 A JP H0353612A
Authority
JP
Japan
Prior art keywords
input terminal
output
comparator circuit
level
channel mosfet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1189106A
Other languages
Japanese (ja)
Inventor
Masayuki Takori
田古里 眞行
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1189106A priority Critical patent/JPH0353612A/en
Publication of JPH0353612A publication Critical patent/JPH0353612A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To prevent malfunction due to noise by causing a constant current to flow to a resistive element corresponding to the output of a comparator circuit to set a Schmitt width optionally depending on a noise level from an equipment itself employing the comparator circuit or from a peripheral equipment. CONSTITUTION:The comparator circuit is constituted by adding an inverter 21 whose noninverting input terminal 2 is connected to a resistive element 8 with respect to gate of MOSFETs 12, 15, and whose input terminal is connected to an output terminal 23, a P-channel MOSFET 6 whose gate is connected to a gate of a MOSFET 3, an a P-channel MOSFET 7 whose gate is connected to the output terminal of the inverter 21 and which is inserted between the P-channel MOSFET 6 and a resistive element 8. The Schmitt width is set optionally depending on a noise level from an equipment itself employing an integrated circuit incorporating the comparator circuit or from a peripheral equipment by causing a constant current to flow to the resistive element 8 in response to the logic level of the output of the comparator circuit.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は初段がNチャンネルMOSFETで構成された
第1の差動増幅器と、初段がPチャンネルMOSFET
で構成された第2の差動増幅器が並列に接続された比較
回路に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention includes a first differential amplifier whose first stage is composed of an N-channel MOSFET, and a first stage composed of a P-channel MOSFET.
The present invention relates to a comparator circuit in which second differential amplifiers configured with the following are connected in parallel.

〔従来の技術〕[Conventional technology]

第3図はこの種の比較回路の従来例を示す回路図である
FIG. 3 is a circuit diagram showing a conventional example of this type of comparison circuit.

この比較回路はPチャンネルMOSFET3.9.11
.14.15.16.19と、NチャンネルMOSFE
T5.10.12.13.17,18.20と、抵抗4
とからなっており、電源が電源供給端22.24から供
給されている。
This comparison circuit is a P-channel MOSFET 3.9.11
.. 14.15.16.19 and N-channel MOSFE
T5.10.12.13.17, 18.20 and resistance 4
, and power is supplied from power supply terminals 22 and 24.

非反転入力端2と、反転入力端1の間に入力信号が印加
されるために、入力範囲を大きくとれるように初段がP
チャンネルMOSFET15.16と初段がNチャンネ
ルMOSFETI0.12で構成された差動増幅器が並
列に接続されている。そして、非反転入力端2と反転入
力端1の間に印加された入力信号はNチャンネルMOS
 FET10.12で構成された差動増幅器とPチャン
ネルMOSFET15.16で構威された差動増幅器で
増幅され、その出力信号は出力端子23に出力される。
Since the input signal is applied between the non-inverting input terminal 2 and the inverting input terminal 1, the first stage is set to P so that the input range can be widened.
Channel MOSFETs 15.16 and a differential amplifier whose first stage is composed of an N-channel MOSFET I0.12 are connected in parallel. The input signal applied between the non-inverting input terminal 2 and the inverting input terminal 1 is an N-channel MOS
The signal is amplified by a differential amplifier composed of FETs 10 and 12 and a differential amplifier composed of P-channel MOSFETs 15 and 16, and the output signal thereof is outputted to output terminal 23.

この出力レベルは非反転入力端2に対して反転入力端1
のレベルが低い場合はハイレベル(以降、Hレベルと記
す)となり、非反転入力端2に対して反転入力端1のレ
ベルが高い場合はロウレベル(以降、Lレベルと記す)
となる。
This output level is the same as that of the inverting input terminal 1 for the non-inverting input terminal 2.
When the level of is low, it becomes a high level (hereinafter referred to as H level), and when the level of inverting input terminal 1 is higher than that of non-inverting input terminal 2, it is a low level (hereinafter referred to as L level)
becomes.

〔発明が解決しようとする課題) 上述した従来の比較回路は、入力端がMOS FETの
ゲートのため非常に高インピーダンスであり、この比較
回路を内蔵した集積回路を装置等−に組み込んだ場合に
、周辺の装置の発生するノイズあるいはこの比較回路を
内蔵した集積回路を用いた装置自体が発生するノイズが
、入力端に印加されて出力にエラーが発生しやすく、そ
の場合装置が誤動作するという欠点がある。
[Problems to be Solved by the Invention] The conventional comparator circuit described above has a very high impedance because the input terminal is the gate of a MOS FET, and when an integrated circuit containing this comparator circuit is incorporated into a device, etc. The disadvantage is that noise generated by peripheral devices or the noise generated by the device itself that uses an integrated circuit that incorporates this comparison circuit is applied to the input terminal and tends to cause errors in the output, causing the device to malfunction. There is.

本発明は上記の欠点に鑑み、ノイズ等の妨害を受けにく
い比較回路を提供することを目的とする。
SUMMARY OF THE INVENTION In view of the above drawbacks, it is an object of the present invention to provide a comparison circuit that is less susceptible to disturbances such as noise.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の比較回路は、 比較回路の少なくとも一方の入力端に直列に接続された
抵抗素子と、 比較回路の出力の論理レベルに対応して、前記抵抗素子
に定電流を流す定電流供給回路とを有する。
The comparison circuit of the present invention includes: a resistance element connected in series to at least one input terminal of the comparison circuit; and a constant current supply circuit that supplies a constant current to the resistance element in accordance with the logic level of the output of the comparison circuit. has.

〔作用〕[Effect]

抵抗素子に定電流供給回路が定電流を流すと、その分入
力のレベルが大きくないと、出力の論理レベルは変わら
ない。
When a constant current supply circuit causes a constant current to flow through a resistive element, the logic level of the output will not change unless the input level is correspondingly large.

〔実施例) 次に、本発明の実施例について図面を参照して説明する
[Example] Next, an example of the present invention will be described with reference to the drawings.

第1図は本発明の比較回路の第1の実施例を示す回路図
である。
FIG. 1 is a circuit diagram showing a first embodiment of the comparison circuit of the present invention.

本実施例は、第3図の従来例の非反転入力端2とMOS
FET12.15のゲートとの間に抵抗8を挿入し、入
力端が出力端23に接続されたインバータ21と、ゲー
トがMOSFET3のゲートに接続されたPチャネルM
OSFET6と、ゲートがインバータ21の出力端に接
続され、PチャネルM O S F E −r 6と抵
抗8との間に挿入されたPチャネルMOSFFT7とを
追加して構成されている。
In this embodiment, the non-inverting input terminal 2 of the conventional example shown in FIG. 3 and the MOS
A resistor 8 is inserted between the gates of FETs 12 and 15, an inverter 21 whose input terminal is connected to the output terminal 23, and a P-channel M whose gate is connected to the gate of MOSFET 3.
It is configured by adding an OSFET 6 and a P-channel MOSFFT 7 whose gate is connected to the output terminal of the inverter 21 and inserted between the P-channel MOSFET 6 and the resistor 8.

次に本実施例の動作について説明する。Next, the operation of this embodiment will be explained.

非反転入力端2と反転入力@i1の間に印加された入力
信号はNチャンネルMOSFET10.12で構成され
た差動増幅器とPチャンネルMOSFET15.16で
構成された差動増幅器で増幅ざれ、その出力信号は出力
端子23に出力される。この出力レベルは非反転入力端
2に対して反転入力端1のレベルが低い場合はHレベル
となり、非反転入力端2に対して反転入力端1のレベル
が高い場合はLレベルとなる。
The input signal applied between the non-inverting input terminal 2 and the inverting input @i1 is amplified by a differential amplifier composed of an N-channel MOSFET 10.12 and a P-channel MOSFET 15.16, and its output is The signal is output to the output terminal 23. This output level becomes H level when the level of inverting input terminal 1 is lower than that of non-inverting input terminal 2, and becomes L level when the level of inverting input terminal 1 is higher than that of non-inverting input terminal 2.

ここで、出力・レベルがHレベルとなるとインバータ2
1の出力が1−レベルとなり、PチャンネルMOSFE
T7がオンして式(1)に示す電流が流れる。
Here, when the output level becomes H level, inverter 2
1 output becomes 1- level, P channel MOSFE
T7 is turned on and the current shown in equation (1) flows.

ただし  Voo  ・・・ 電源電圧Vcsa・・・
 NチャンネルMOSFET5のゲート・ソース間電圧 VGS3・・・ PチャンネルMOSFET3のゲート
・ソース間電圧 R4 ・・・ 抵抗4の抵抗値 したがって、抵抗8に電圧降下LLXRa(Raは抵抗
8の抵抗値)が生じる。
However, Voo... Power supply voltage Vcsa...
Gate-source voltage VGS3 of N-channel MOSFET 5... Gate-source voltage R4 of P-channel MOSFET 3... Resistance value of resistor 4 Therefore, a voltage drop LLXRa (Ra is the resistance value of resistor 8) occurs across resistor 8. .

この電圧下降IL XR8が入力のシュミット幅となり
、非反転入力端2が反転入力端1に対して電圧降下IL
 XRa分の電『を下げないと出力はLレベルにならな
い。このシュミット幅は抵R4.8を任意に選ぶことに
より、シュミット幅を任意に設定できる。すなわち、こ
の比較回路の内蔵される集積回路を用いた装置自体、あ
いは周辺装置によるノイズのレベルによって、シュミッ
ト幅が任意に設定出来るのでノイズによる誤動作を防止
出来る。又、定IR流源を構或する抵抗R4とシュミッ
ト幅を設定する抵抗R8を、集積回路化に際して同じ種
類の抵抗で作ることにより、シュミット幅のバラッキの
少ない比較回路を提供出来る。
This voltage drop IL XR8 becomes the Schmitt width of the input, and the voltage drop IL
The output will not go to L level unless the voltage of XRa is lowered. This Schmidt width can be arbitrarily set by arbitrarily selecting a resistor R4.8. In other words, the Schmitt width can be arbitrarily set depending on the level of noise caused by the device itself using the integrated circuit in which the comparator circuit is built, or by the peripheral devices, so malfunctions due to noise can be prevented. Furthermore, by making the resistor R4 that constitutes the constant IR current source and the resistor R8 that sets the Schmitt width from the same type of resistor when integrated into a circuit, it is possible to provide a comparison circuit with less variation in the Schmitt width.

第2図は本発明の第2の実施例を示す回路図である。FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

動作は第1図の実施例と同様であり、抵抗3oに流れる
電流I LLは式(2)で示される。
The operation is similar to the embodiment shown in FIG. 1, and the current ILL flowing through the resistor 3o is expressed by equation (2).

1LL= Voo−VGS5 −VGS3 .....
. (2)R4 したがって、シュミット幅はL LL X R 30と
なり抵抗4.30を任意に選ぶことにより、シュミット
幅を任意に設定出来る。すなわち、この比較回路の内蔵
される集積回路を用いた装置自体、あるいは周辺装置に
よるノイズのレベルによって、シュミット幅が任意に設
定出来るので、ノイズによる誤動作を防止でき、さらに
定電流源を構成する抵抗4とシュミット幅を設定する抵
抗30を、集積回路化に際して同じ種類の抵抗で作るこ
とにより、シュ蔑ット幅のバラツキの少ない比較回路を
提供できる。又、比較回路は、非反転入力と反転入力の
両方に抵抗素子を接続して、比較回路の出力によって制
御されるスイッチ素子により定電流源を非反転入力端と
反転入力端の両方に接続しても同様の効果が得られる。
1LL=Voo-VGS5-VGS3. .. .. .. ..
.. (2) R4 Therefore, the Schmidt width is L LL X R 30, and by arbitrarily selecting a resistance of 4.30, the Schmidt width can be set arbitrarily. In other words, the Schmitt width can be arbitrarily set depending on the level of noise from the device itself using the integrated circuit in which the comparison circuit is built, or from peripheral devices, so malfunctions due to noise can be prevented. By making the resistor 4 and the resistor 30 for setting the Schmitt width using the same type of resistor when integrated into a circuit, it is possible to provide a comparison circuit with less variation in the Schmidt width. In addition, the comparator circuit has a resistive element connected to both the non-inverting input and the inverting input, and a constant current source connected to both the non-inverting input terminal and the inverting input terminal by a switch element controlled by the output of the comparator circuit. The same effect can be obtained.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、非反転入力端と反転入力
端の少なくとも一方に抵抗素子を接続し4 て、比較回路の出力に対応して抵抗素子に定電流を流す
ことにより、比較回路が用いられた装置自体、あるいは
周辺’lfiffによるノイズのレベルによって、シュ
ミット幅が任意に設定出来るので、ノイズによる誤動作
を防止することができる効果がある。
As explained above, the present invention connects a resistive element to at least one of the non-inverting input terminal and the inverting input terminal, and flows a constant current through the resistive element in accordance with the output of the comparator circuit. Since the Schmidt width can be arbitrarily set depending on the device used or the level of noise caused by the surrounding 'lfiff, malfunctions due to noise can be prevented.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の比較回路の第1の実施例を示す回路図
、第2図は本発明の第2の実施例を示す回路図、第3図
は従来例を示す回路図である。 1・・・反転入力端、   2・・・非反転入力喘、2
3・・・出力端、   22.24・・・電源供給端、
21.33・・・インバータ、 4.7.30・・・抵抗
FIG. 1 is a circuit diagram showing a first embodiment of a comparison circuit of the present invention, FIG. 2 is a circuit diagram showing a second embodiment of the present invention, and FIG. 3 is a circuit diagram showing a conventional example. 1... Inverting input end, 2... Non-inverting input end, 2
3... Output end, 22.24... Power supply end,
21.33...Inverter, 4.7.30...Resistor

Claims (1)

【特許請求の範囲】 1、初段がNチャンネルMOSFETで構成された第1
の差動増幅器と、初段がPチャンネルMOSFETで構
成された第2の差動増幅器が並列に接続された比較回路
において、 前記比較回路の少なくとも一方の入力端に直列に接続さ
れた抵抗素子と、 前記比較回路の出力の論理レベルに対応して、前記抵抗
素子に定電流を流す定電流供給回路とを有することを特
徴とする比較回路。
[Claims] 1. The first stage is composed of an N-channel MOSFET.
A comparison circuit in which a differential amplifier and a second differential amplifier whose first stage is composed of a P-channel MOSFET are connected in parallel, a resistive element connected in series to at least one input terminal of the comparison circuit; A comparison circuit comprising: a constant current supply circuit that causes a constant current to flow through the resistance element in accordance with a logic level of an output of the comparison circuit.
JP1189106A 1989-07-20 1989-07-20 Comparing circuit Pending JPH0353612A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1189106A JPH0353612A (en) 1989-07-20 1989-07-20 Comparing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1189106A JPH0353612A (en) 1989-07-20 1989-07-20 Comparing circuit

Publications (1)

Publication Number Publication Date
JPH0353612A true JPH0353612A (en) 1991-03-07

Family

ID=16235467

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1189106A Pending JPH0353612A (en) 1989-07-20 1989-07-20 Comparing circuit

Country Status (1)

Country Link
JP (1) JPH0353612A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014062825A (en) * 2012-09-21 2014-04-10 Asahi Kasei Electronics Co Ltd Voltage detection circuit, and voltage detection method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014062825A (en) * 2012-09-21 2014-04-10 Asahi Kasei Electronics Co Ltd Voltage detection circuit, and voltage detection method

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