JPH0352436A - Fail safe circuit in equilibrium transmission circuit - Google Patents
Fail safe circuit in equilibrium transmission circuitInfo
- Publication number
- JPH0352436A JPH0352436A JP18767589A JP18767589A JPH0352436A JP H0352436 A JPH0352436 A JP H0352436A JP 18767589 A JP18767589 A JP 18767589A JP 18767589 A JP18767589 A JP 18767589A JP H0352436 A JPH0352436 A JP H0352436A
- Authority
- JP
- Japan
- Prior art keywords
- transmission line
- receiver
- circuit
- disconnection
- bias
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005540 biological transmission Effects 0.000 title claims abstract description 79
- 238000001514 detection method Methods 0.000 claims abstract description 14
- 238000012544 monitoring process Methods 0.000 claims description 2
- 230000002159 abnormal effect Effects 0.000 abstract description 3
- 230000008054 signal transmission Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Landscapes
- Dc Digital Transmission (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、ＥＩＡ ＲＳ４２２（１１）に準拠した平
衡伝送回路のケーブル抜け等により発生する伝送路断時
に、レシーバ入力に適当なバイアス電圧を与えレシーバ
出力を確定させる為の７エイルセーフ回路伝送路に関し
、特に、高速伝送時における波形歪の低減を計ったフェ
イルセーフ回路伝送路に関する．
［従来の技術］
従来のこの種のバイアス印加回路を第３図に示す．
図示されているように、従来のバイアス印加回路では、
バイアス電圧が、インターフェースボイント２１とレシ
ーバ２３との間において、レシーバ入力に対し常時印加
されている。このバイアス電圧は、電圧■を抵抗Ｒ１、
Ｒ２、Ｒ３により分圧した電圧のうちＲ２の両端に現れ
る電圧（ＶＤＢ）と等しい．
このバイアス電圧により、伝送路断時においてもレシー
バ２３の入力電圧は、所定の値に固定され、出力電圧が
確定される．
尚、図面中、２２は平衡伝送路であり、２８はドライバ
である．
［発明が解決しようとする課題１
上述した、従来のバイアス印加回路は、常時バイアス電
圧が印加されている為、伝送路が断状態でない正常状態
での信号の送受信に関し、下記の不具合がある．
−ａに、レシーバ２３の出力は、レシーバの入力端子Ａ
．Ｂの電位差により決り、
（Ａ＠子電位）＞（Ｂ＠子電位）の時はハイレベル．（
８９子電位）〉（Ａ端子電位）の時は＋７一レベルとな
る．
ところか、上述した従来回路では、入力端子Ａ、１３間
に常時直流バイアスＶＤＢが、Ａ＠子の電位が高くなる
方向で印加されてする為に、■ ドライバ２８の入力が
ローレベルとなった時点よりＡ＠子の電位が降下し、同
時にＩｌｌｌの電位か上昇し、（Ｂ＠子電位）〉（Ａ端
子電位）となり、レシーバ出力がローレベルとなる迄に
要する時間をＴ１とし、
■ ドライバ２８の入力がハイレベルとなった時点より
、Ａ端子の電位が上昇し、同時にＢ端子の電位か下降し
、（Ａ端子電位）〉（Ｂ端子電位）となり、レシーバ出
力がハイレベルとなる迄に要する時間をＴ２とした時、
Ｔ１はＴ２よりも大きくなる。[Detailed Description of the Invention] [Industrial Application Field] The present invention applies an appropriate bias voltage to the receiver input when a transmission line is disconnected due to a cable disconnection in a balanced transmission circuit conforming to EIA RS422 (11). This article relates to a fail-safe circuit transmission line for determining the receiver output, and in particular to a fail-safe circuit transmission line designed to reduce waveform distortion during high-speed transmission. [Prior Art] Figure 3 shows a conventional bias application circuit of this type. As shown, in the conventional bias application circuit,
A bias voltage is constantly applied to the receiver input between the interface point 21 and the receiver 23. This bias voltage is determined by connecting the voltage ■ to the resistor R1,
Of the voltage divided by R2 and R3, it is equal to the voltage (VDB) appearing across R2. With this bias voltage, the input voltage of the receiver 23 is fixed at a predetermined value even when the transmission line is disconnected, and the output voltage is determined. In the drawing, 22 is a balanced transmission line, and 28 is a driver. [Problem to be Solved by the Invention 1] The conventional bias application circuit described above has the following problems with regard to signal transmission and reception in a normal state where the transmission line is not disconnected because a bias voltage is constantly applied. -a, the output of the receiver 23 is connected to the input terminal A of the receiver.
．． It is determined by the potential difference of B, and when (A@child potential)>(B@child potential), it is high level. (
89 terminal potential)> (A terminal potential), it becomes +7-1 level. However, in the conventional circuit described above, since the DC bias VDB is constantly applied between the input terminals A and 13 in the direction in which the potential of A@ becomes high, ■ the input of the driver 28 becomes low level. From this point on, the potential of A@ child drops, and at the same time, the potential of Illll increases, so that (B @ child potential) > (A terminal potential), and the time required until the receiver output becomes low level is T1, ■ Driver From the time when the input of 28 becomes high level, the potential of the A terminal rises and at the same time the potential of the B terminal falls, until (A terminal potential)>(B terminal potential), and the receiver output becomes high level. When the time required for this is T2, T1 is larger than T2.
この為、第４図に示す様に、ドライバ２８の入力にデュ
ーティ比５０％の方形波を加えても、レシーバ２３の出
力は、Ｄ−レベルが、Δｔだけ狭くなり、ハイレベルが
Δｔだけ広くなった歪んだ波形となる。Therefore, as shown in FIG. 4, even if a square wave with a duty ratio of 50% is applied to the input of the driver 28, the output of the receiver 23 will have a D-level narrowed by Δt and a high level widened by Δt. This results in a distorted waveform.
この歪は、ノイズマージンを大きくする為に、バイアス
電圧を大きくする程、また、伝送する波形の周期を短く
する程大きくなり、高速のパルス伝送時には、無視出来
ない値となる．
［課題を解決するための手段］
本発明の目的は、上述した従来技術の課題を解決し、バ
イアス電圧に起因する伝送波形の歪を無くしつつ伝送路
断時にレシーバ出力の確定を行えるフＸイルセ−７回路
を提供することである．本発明は、平衡伝送回路のレシ
ーバ入力側に備えられ、ケーブル抜け等により発生する
伝送路断時に、レシーバ入力に適当なバイアス電圧を与
えレシーバ出力を確定させる為のフェイルセーフ回路に
おいて，平衡伝送路を構成する二線のインタフエースポ
イントにおける電位を監視することにより、平衡伝送路
断状態を検出する伝送路断検出部と、伝送路断検出部の
出力に応じ、伝送路正常時は、伝送路の二線をレシーバ
入力に接続し、伝送路断時は、伝送路の二線をレシーバ
入力に非接続状態とするスイッチ回路と、そして、伝送
路断検出部の出力に応じ、伝送路断時は、レシーバ入力
に出力を確定させる為に必要なバイアスを印加し、また
、伝送路正常時は、レシーバへのバイアスを無印加とす
る伝送路断時バイアス印加回路とを有することを特徴と
する．
本発明のフェイルセーフ回路の作用としては、平衡伝送
路か、正常状態のときは伝送路断検出部の出力は、正常
状態に応じた信号を出力し、この信号により、スイッチ
回路は、平衡伝送路を楕成する二線を、レシーバの入力
端子Ａ，Ｂに接続する．伝送路断時バイアス印加回路は
、伝送路断検出部よりの正常状態信号を受け、レシーバ
の入力端子Ａ，Ｂに対してはバイアスを無印加とする。This distortion increases as the bias voltage is increased and the period of the transmitted waveform is shortened in order to increase the noise margin, and becomes a value that cannot be ignored during high-speed pulse transmission. [Means for Solving the Problems] An object of the present invention is to solve the problems of the prior art described above, and to provide a flexible system that can determine the receiver output when the transmission line is disconnected while eliminating distortion of the transmission waveform caused by the bias voltage. -7 circuits. The present invention is provided on the receiver input side of a balanced transmission circuit, and is used in a fail-safe circuit for applying an appropriate bias voltage to the receiver input and determining the receiver output when the transmission line is disconnected due to cable disconnection, etc. A transmission line disconnection detection unit detects a balanced transmission line disconnection state by monitoring the potential at the interface point of the two wires that make up the transmission line. The two wires of the transmission line are connected to the receiver input, and when the transmission line is disconnected, the two wires of the transmission line are disconnected from the receiver input. is characterized by having a transmission line disconnection bias application circuit which applies a necessary bias to the receiver input to determine the output, and which applies no bias to the receiver when the transmission line is normal. ．． The function of the fail-safe circuit of the present invention is that when the balanced transmission line is in a normal state, the output of the transmission line disconnection detection section outputs a signal corresponding to the normal state, and this signal causes the switch circuit to transmit the balanced transmission. Connect the two wires forming an oval path to input terminals A and B of the receiver. The transmission line disconnection bias application circuit receives a normal state signal from the transmission line disconnection detection section and applies no bias to the input terminals A and B of the receiver.
この様に、伝送路が正常状態の時は、レシーバの入力端
子には何らバイアスは加わらず、この為、バイアス電圧
に起因する波形歪は生じない．一方、伝送路断時には、
伝送路断検出部は、異常状態信号を出力し、この信号に
より、伝送路断時バイアス印加回路は、レシーバの入力
端子Ａ、Ｂに所定のバイアスを印加し、レシーバ出力を
確定させる．同時に、スイッチ回路は、伝送路断検出部
よりの異常状態信号を受け、伝送路を構戒する二線をレ
シーバん入力端子Ａ，Ｂより切断する．これにより、イ
ンターフェースポイントはレシーバ入力より切離され、
伝送路断時バイアス印加回路により、レシーバの入力端
子Ａ，Ｂに印加された電圧がインターフェースポイント
に侵入することによって生ずる伝送路断検出部の誤動作
を防ぐ．［実施例］
次に、本発明のフェイルセーフ回路について図面を参照
して詳細に説明する．
第１図は、本発明に係るフェイルセーフ回路の第一の実
１４例の回路図である．
伝送路断検出部１は、インタフェースポイント１１のＣ
，Ｄ点の電位を常時モニタしており、電位差があれば、
伝送路断検出部１はリレー６を駆動せず、リレー６は不
動作状態となる．一方、電位差かない場合は、伝送路断
検出部１はリレー６を駆動し、リレー６は動作状態とな
る．伝送路が正常な場合は、インタフェースポイント１
１の２点は必ず異なった電位となり、リレー６は、駆動
されない．この為、リレー６のメーク接点７、８はオー
プン状態となり、レシーバ９の入力端子Ａ，Ｂにはバイ
アスは印加されない．方、３、４はブレーク接点である
為、接続状態となり、伝送路１２の信号はレシーバ９の
入力端子Ａ．Ｂに達する．
この様に伝送路１２が正常な状態においては、レシーバ
９の入力端子Ａ．Ｂには伝送＃１１２の信号が直接加わ
る．この時は、レシーバ９の入力端子Ａ，Ｂにはバイア
ス電圧の印加がないことがら、バイアス電圧に起因する
伝送波形の歪は生じない．次に、ケーブル抜け等により
、伝送路１２が断状態となると、インタフェースポイン
ト１１のＣ、Ｄ点は同電位、従って、伝送路断検出部１
の入力は同電位となり、リレー６は駆動される．この為
、リレー６のメーク接点７、８は、接続状態となり、レ
シーバ９の入力端子Ａ，Ｂには、バイアス電圧が印加さ
れる．同時に、プレーク接点３、４はオープン状態とな
り、インタフェースポイント１１１１１はレシーバ９の
入力端子Ａ．Ｂより切離される．これにより、レシーバ
９の入力端子Ａ．Ｂに印加されたバイアス電圧が、イン
タフェースポイント１１ＩＩｍｌへまわり込むことによ
って生ずる伝送路断検出部１の誤動作を防ぐ．第２図は
、本発明に係るフェイルセーフ回路の第二の実施例の回
路図である．
図示された第二の実施例は、スイッチ回路及び伝送路断
時バイアス印加回路を半導体スイッチにより実現したも
のである．
第１図のブレーク接点３は第２図の電子接点１５に、第
１図のブレーク接点４は第２図の電子接点１６に、第１
図のメイク接点７は第２図の電子接点１３に、そして、
第１図のメイク接点８は第２図の電子接点１４に、それ
ぞれ対応する．尚、ｌ７及び１８は、電子接点１３、１
４及び電子接点１５、１６を電子的に開閉制御する制御
線である．
［発明の効果］
以上説明した様に、本発明は、従来回路において、常時
印加されていたレシーバの入力端子へのバイアス電圧を
、ケーブル抜け等による伝送路断が生じた場合にのみ印
加することとし、それ以外の時は無印加としたことによ
り、従来回路において発生していたバイアス電圧に起因
する伝送波形の歪を無くしつつ伝送路断時にレシーバ出
力の確定を行えるという効果がある．
この為、ケーブル抜け等による伝送路断時の出力確定と
いうフェイルセーフ機能を損なう事なく、高速の信号伝
送を可能となった．In this way, when the transmission line is in a normal state, no bias is applied to the input terminal of the receiver, so no waveform distortion occurs due to the bias voltage. On the other hand, when the transmission line is disconnected,
The transmission line disconnection detection section outputs an abnormal state signal, and in response to this signal, the transmission line disconnection bias application circuit applies a predetermined bias to the input terminals A and B of the receiver to determine the receiver output. At the same time, the switch circuit receives an abnormal state signal from the transmission line disconnection detection section and disconnects the two wires that guard the transmission line from the receiver input terminals A and B. This separates the interface point from the receiver input,
The transmission line disconnection bias application circuit prevents the transmission line disconnection detector from malfunctioning due to the voltage applied to the input terminals A and B of the receiver entering the interface point. [Example] Next, the fail-safe circuit of the present invention will be explained in detail with reference to the drawings. FIG. 1 is a circuit diagram of the first 14th example of the fail-safe circuit according to the present invention. The transmission line disconnection detection unit 1
, the potential at point D is constantly monitored, and if there is a potential difference,
The transmission line disconnection detection unit 1 does not drive the relay 6, and the relay 6 becomes inactive. On the other hand, if there is no potential difference, the transmission line disconnection detection unit 1 drives the relay 6, and the relay 6 becomes operational. If the transmission path is normal, interface point 1
The two points 1 are always at different potentials, and relay 6 is not driven. Therefore, the make contacts 7 and 8 of the relay 6 are in an open state, and no bias is applied to the input terminals A and B of the receiver 9. On the other hand, since 3 and 4 are break contacts, they are in a connected state, and the signal on the transmission line 12 is sent to the input terminal A. of the receiver 9. Reach B. In this way, when the transmission line 12 is in a normal state, the input terminal A of the receiver 9. The signal of transmission #112 is directly applied to B. At this time, since no bias voltage is applied to the input terminals A and B of the receiver 9, distortion of the transmission waveform due to the bias voltage does not occur. Next, when the transmission line 12 becomes disconnected due to cable disconnection, etc., points C and D of the interface point 11 have the same potential, so the transmission line disconnection detection unit 1
The inputs of are at the same potential, and relay 6 is driven. Therefore, the make contacts 7 and 8 of the relay 6 are in a connected state, and a bias voltage is applied to the input terminals A and B of the receiver 9. At the same time, the plate contacts 3, 4 are open and the interface point 11111 is connected to the input terminal A. of the receiver 9. Separated from B. As a result, the input terminal A of the receiver 9. This prevents malfunction of the transmission line disconnection detection unit 1 caused by the bias voltage applied to the terminal B being passed around to the interface point 11IIml. FIG. 2 is a circuit diagram of a second embodiment of the fail-safe circuit according to the present invention. In the second embodiment shown in the figure, the switch circuit and the transmission line disconnection bias application circuit are implemented using semiconductor switches. The break contact 3 in FIG. 1 is connected to the electronic contact 15 in FIG. 2, the break contact 4 in FIG. 1 is connected to the electronic contact 16 in FIG.
The make contact 7 in the figure is connected to the electronic contact 13 in FIG. 2, and
The make contacts 8 in FIG. 1 correspond to the electronic contacts 14 in FIG. 2, respectively. In addition, l7 and 18 are electronic contacts 13, 1
4 and electronic contacts 15 and 16 to electronically control opening and closing. [Effects of the Invention] As explained above, the present invention makes it possible to apply the bias voltage to the input terminal of the receiver, which was always applied in conventional circuits, only when a transmission line disconnection occurs due to a cable being pulled out, etc. By applying no voltage at all other times, the receiver output can be determined when the transmission line is disconnected while eliminating the distortion of the transmission waveform caused by the bias voltage that occurs in conventional circuits. As a result, high-speed signal transmission is possible without compromising the fail-safe function of determining the output when the transmission line is disconnected due to a cable being pulled out, etc.
第１図は、本発明に係るフェイルセーフ回路の第一の実
施例の回路図である．
第２図は、本発明に係るフェイルセーフ回路の第二の実
施例の回路図である．
第３図は、従来のフェイルセーフ回路の回路図である．
そして、
第４図は、伝送波形の歪を説明するための波形図である
．
１・・・伝送路断検出部
２・・・スイッチ回路
３、４・・・ブレーク接点
６・・・リレー
７、８・・・メータ接点
９・・・レシーバ
１０・・・伝送路断時バイアス印加回路ｌ１・・・イン
ターフ玉一スポイント
１２・・・伝送路FIG. 1 is a circuit diagram of a first embodiment of a fail-safe circuit according to the present invention. FIG. 2 is a circuit diagram of a second embodiment of the fail-safe circuit according to the present invention. Figure 3 is a circuit diagram of a conventional fail-safe circuit.
FIG. 4 is a waveform diagram for explaining the distortion of the transmitted waveform. 1... Transmission line disconnection detection unit 2... Switch circuit 3, 4... Break contact 6... Relay 7, 8... Meter contact 9... Receiver 10... Bias at transmission line disconnection Application circuit l1...Interface ball point 12...Transmission line
Claims (1)
け等により発生する伝送路断時に、レシーバ入力に適当
なバイアス電圧を与えレシーバ出力を確定させる為のフ
ェイルセーフ回路において、平衡伝送路を構成する二線
のインタフェースポイントにおける電位を監視すること
により、平衡伝送路断状態を検出する伝送路断検出部と
、前記伝送路断検出部の出力に応じ、伝送路正常時は、
前記伝送路の二線をレシーバ入力に接続し、伝送路断時
は、前記伝送路の二線をレシーバ入力に非接続状態とす
るスイッチ回路と、そして、前記伝送路断検出部の出力
に応じ、伝送路断時は、レシーバ入力に出力を確定させ
る為に必要なバイアスを印加し、また、伝送路正常時は
、レシーバへのバイアスを無印加とする伝送路断時バイ
アス印加回路と、 を有することを特徴とする平衡伝送回路におけるフェイ
ルセーフ回路。[Claims] In a fail-safe circuit that is provided on the receiver input side of a balanced transmission circuit and that applies an appropriate bias voltage to the receiver input to determine the receiver output when the transmission line is disconnected due to a cable being disconnected, etc. A transmission line disconnection detection unit detects a balanced transmission line disconnection state by monitoring the potential at the interface point of two wires constituting the transmission line, and according to the output of the transmission line disconnection detection unit, when the transmission line is normal,
a switch circuit that connects two wires of the transmission line to a receiver input and disconnects the two wires of the transmission line from the receiver input when the transmission line is disconnected; , a transmission line disconnection bias application circuit that applies the necessary bias to the receiver input to determine the output when the transmission line is disconnected, and applies no bias to the receiver when the transmission line is normal; A fail-safe circuit in a balanced transmission circuit, characterized by comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18767589A JPH0352436A (en) | 1989-07-20 | 1989-07-20 | Fail safe circuit in equilibrium transmission circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18767589A JPH0352436A (en) | 1989-07-20 | 1989-07-20 | Fail safe circuit in equilibrium transmission circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0352436A true JPH0352436A (en) | 1991-03-06 |
Family
ID=16210183
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18767589A Pending JPH0352436A (en) | 1989-07-20 | 1989-07-20 | Fail safe circuit in equilibrium transmission circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0352436A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000354072A (en) * | 1999-04-23 | 2000-12-19 | Daimlerchrysler Ag | Circuit device provided with reducing circuit capable of reducing interference longitudinal voltage on two- wire line |
| JP2014168181A (en) * | 2013-02-28 | 2014-09-11 | Seiko Instruments Inc | Operational amplifier |
-
1989
- 1989-07-20 JP JP18767589A patent/JPH0352436A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000354072A (en) * | 1999-04-23 | 2000-12-19 | Daimlerchrysler Ag | Circuit device provided with reducing circuit capable of reducing interference longitudinal voltage on two- wire line |
| JP2014168181A (en) * | 2013-02-28 | 2014-09-11 | Seiko Instruments Inc | Operational amplifier |
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