JPH0352267A - Semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PURPOSE:To improve electric characteristic of an EEPROM by continuously extending a field insulating film for isolating memory cells in the direction perpendicular to a work line. CONSTITUTION:A field insulating film 2 for isolating memory cells Qm is extended continuously in the direction perpendicular to a word line WL. Accordingly, the superposing area of a floating gate 3 and a source region become equal for all cells. Thus, the coupling capacity formed between the gate 3 and the source region become equal for all cells Qm, and the floating gate voltage become equal for all cells Qm. Thus, the irregularity in data erasing speed is eliminated and electric characteristic of EEPROM are improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device and a method for manufacturing the same, and particularly to a nonvolatile memory in which data can be electrically erased and rewritten.
sable ProgrammableRead On
The present invention relates to a technology that is effective when applied to lyMemory; EEPROM). More specifically,
The present invention relates to an EEPROM composed of a plurality of single transistor cells suitable for high density storage applications.

[Conventional technology]

Since EEPROM can be highly integrated and densely packed,
EEP whose memory cell is composed of a single MISFET
ROM is the mainstream. The MISFET constituting the memory cell of this EEPROM has a two-layer gate electrode structure consisting of a floating gate and a control gate.

In this EEPROM, writing is performed, for example, by grounding the source region, applying a 0.5 to 5 millisecond pulse with an amplitude of 4 to 6 V to the drain region, and 10 to 12 V to the control gate. By capturing the hot electrons generated in the pinch-off region near the drain region into the 7 loading gate, the threshold value can be set to 3.5~
It becomes 5.5V.

For erasing, for example, the drain region is floating, the control gate is grounded, and the source region is 10 to 13
When a 0.5 to 5 millisecond pulse is applied with an amplitude of V, electrons in the floating gate are extracted to the source region by the Fowler-Nordheim tunneling effect, and the threshold becomes about IV.

FIG. 27 shows a memory cell array of an EEPROM. A source region 31 is provided in the active region of the semiconductor substrate 30.
and drain region 32 are arranged to face each other for each memory cell Qm.

The drain region 32 is separated for each memory cell Qm via a field insulating film (LOCOS film) 33 arranged in the form of an island, and each drain region 32 is connected to the data line DL through a contact hole 34.Data The line DL extends, for example, in the Y direction, and the word line WL extends in the X direction orthogonal thereto.

A two-layer gate electrode consisting of a floating gate 35 and a control gate 36 is provided between the source region 31 and the drain region 32. Word line WL
A control gate 36 that also serves as a gate is arranged so as to overlap the floating gate 35. Each memory cell QffI is provided in a region where a word line WL and a data line DL intersect. All memory cells QITl connected to one word line WL share their source region 31. In this way, in order to form the source region continuously in the X direction, the field insulating film 33 is formed intermittently in the Y direction.

Furthermore, the two memory cells Qm lined up along the direction in which the data line DL extends share a common drain region 32, and are arranged symmetrically to each other with this drain region 32 at the center. .

Regarding such EEPROM, for example, Japanese Patent Application Laid-open No. 61
'-127179.

[Problem to be solved by the invention]

The inventor of the present invention investigated the above-mentioned conventional EEPROM and found the following problems.

A field insulating film that separates EEPROM memory cells in the X direction is designed so that its four corners are at right angles. However, the field insulating film formed on the actual semiconductor substrate gradually deforms as it goes through the phosphorography process and the oxidation process, and its four corners become rounded as shown in FIG. When a floating gate 35 and a control gate 36 (word illWL) are formed on such a field insulating film 33, it may be caused by misalignment or rotational misalignment in the Y direction of the mask for patterning them. Then, either the even-numbered word line (W L2, W L4...>) or the odd-numbered word line 11 (W L +. W Ls...) (in FIG. 28, the even-numbered word line WL
,,WL,> may overlap with the rounded region of the field insulating film 33. In such a case, the area of the region where the floating gate 35 and the source region 31 overlap differs between every other even-numbered word line WL and every other odd-numbered word line WL. Therefore, the coupling capacitance IC formed between the floating gate 35 and the source region 31 is different between every other even-numbered word line WL and every other odd-numbered word line WL. In particular, in the case of Flash-type EEPROMs in which data is electrically erased all at once by applying a high voltage to the source region, the narrow tunnel region where the source region and floating gate overlap is Since data is erased using flowing Fowler-Nordheim current, the coupling capacitance Cs
A memory cell (Qm,, Qm,) with a small value has a relatively high floating gate voltage V, whereas a memory cell with a large coupling capacity I C s (Qm,) has a relatively high floating gate voltage V,
Qm, , QIT+4) l;! , the sono floating gate voltage vP becomes relatively low, so the data erasing speed varies between the memory cells Qm connected to the even-numbered word lines WL and the memory cells Qm connected to the odd-numbered word lines WL. There is a problem with this.

On the other hand, in order to eliminate the above-mentioned variation in coupling capacitance C, the margin for misalignment and rotational misalignment of the mask with respect to the field insulating film when forming the floating gate and control gate (word line WL) by overlapping cutting is In order to increase this, the distance D between the field insulating film 33 and the floating gate 35, which are formed intermittently in the Y direction shown in FIG. 27, must be made larger than the amount of mask misalignment. Therefore, the size of the memory cell Qm becomes large, so the EEP
There is a problem in that high integration of ROM is hindered.

Next 1: In the EEPROM manufacturing process, when forming a floating gate and a control gate, first, as shown in FIG. 29, the first polysilicon film 37 for the floating gate deposited on the substrate 30 is The field insulating film 33 is continuous in the X direction and discontinuous in the X direction.
Etch along the center line. Next, a second layer polysilicon film for a control gate is deposited on the substrate,
The first layer polysilicon film and the second layer polysilicon film are etched in an overlapping manner to form a floating gate 35 and a control gate 36, as shown in FIG.
After shaping (word line WL) with one mask, impurity ions are implanted into the active region of the field insulating film and control gate by self-alignment, and the source region 3
1 and a drain region 32 are formed.

However, in the gate processing process described above, a part of the active region along the center line of the field insulating film (the shaded area in FIG. 30) is covered with the I-layer polysilicon film and the second-layer polysilicon film. When performing layered etching, only the second layer polysilicon film exists in this oblique portion, so the surface of this active region is scraped and a band-shaped 138
There is a problem in that junction leakage current is generated from the defects that occur there. In addition, when the depth of the diffusion layer constituting the source region is shallow, when impurity ions are implanted into the active region to form the source region 31 and the drain region 32, impurity ions are added to the sidewalls of the trench 38 described above. Since the EEPROM is not implanted, there is a problem in that the source regions 31 on both sides of the trench 38 are disconnected, which lowers the manufacturing yield of the EEPROM.

An object of the present invention is to provide a technique that can improve the electrical characteristics of an EEPROM.

Another object of the present invention is to achieve the above object and to
The object of the present invention is to provide a technology that can improve the manufacturing yield of EPROM.

Still another object of the present invention is to provide a technique that can achieve the above object and also improve the degree of integration of EEPROM.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

One invention of the present application is an EE in which a field insulating film separating memory cells is continuously extended in a direction perpendicular to a word line.
It is PROM.

Another invention of the present application is to continuously extend a field insulating film that separates memory cells in a direction perpendicular to a word line, and to connect a source region surrounded by the field insulating film and the word line. This is an EEPROM in which a common source line is provided in the direction in which the line extends.

Another invention of the present application is a method of manufacturing an EEPROM in which the common source line is formed in self-alignment with the gate electrode.

Another invention of the present application is to sequentially deposit a conductive film for a floating gate and a conductive film for a control gate on a field insulating film continuously extending in a direction perpendicular to a word line, and to form a conductive film for a floating gate. After etching the conductive film for the control gate in an overlapping manner to form a double-layer gate electrode, the field insulating film on the region where the source region is to be formed is removed by etching, thereby converting the source region into a control gate. This is a method of manufacturing an EEPROM in which control gates are continuously formed in the extending direction by self-alignment.

[Effect]

According to the invention of the present application in which the field insulating film is continuously extended in the direction orthogonal to the word line, the area of the region where the floating gate and the source region overlap becomes equal in all memory cells. Therefore, the coupling capacitance formed between the floating gate and the source region becomes equal in all memory cells, and as a result, the floating gate voltage becomes equal in all memory cells, so variations in data erase speed are eliminated. The electrical characteristics of EEPROM are improved.

In addition, since the field insulating film is not separated into islands but extends continuously in the direction perpendicular to the word line, it is easier to etch the polysilicon film for the floating gate along the center line of the field insulating film. Active areas of the substrate are not etched.

This prevents the substrate from being scraped, thereby preventing junction leakage current from occurring. Further, disconnection of the source region due to scratching of the substrate can be prevented.

Next, according to the invention of the present application in which the common source line is formed in a self-aligned manner with respect to the two-layer gate electrode, there is no need for a contact hole to connect the common source line to the source region. This eliminates the need for a margin for mask alignment, and the area of the source region can be reduced accordingly.

Next, after forming a two-layer gate electrode on the field insulating film extending continuously in the direction perpendicular to the word line, the field insulating film on the region where the source region is to be formed is removed by etching. According to the invention of the present application, which forms a field insulating film in which the sidewall on the side of the source region is flush with the sidewall of the double-layer gate electrode, the area of the region where the floating gate and the source region overlap can be reduced in all memory cells. can be made equal. Therefore, as a result of the coupling capacitance between the floating gate and the source region being equal in all memory cells, for example, the floating gate voltage when erasing data is the same in all memory cells, so that data Variations in erase speed are eliminated and the electrical characteristics of the EEPROM are improved. Furthermore, since the polysilicon film for the floating gate is etched while the field insulating film extends continuously in the direction orthogonal to the word line, the active region of the substrate is not etched. Therefore, since the substrate is prevented from being scraped, deterioration of the electrical characteristics of the memory cell due to the occurrence of junction leakage current can be prevented. Further, disconnection of the source region due to scratching of the substrate can be prevented.

Hereinafter, the present invention will be explained in detail using Examples. Incidentally, in the purpose of explaining the embodiments, parts having the same functions are given the same reference numerals, and repeated explanation thereof will be omitted.

[Embodiment 1] The semiconductor integrated circuit device of Embodiment 10 is a flash EEPROM that can be electrically erased at once, and FIG. 12 is an equivalent circuit diagram showing its memory cell array and some peripheral circuits.

The memory cell array includes memory cells Qm and word lines WL.
, a data line DL and a common source line SL. The memory cell Qm is composed of an n-channel MISFET with a double-layered gate electrode structure consisting of a floating gate and a control gate, and the word line WL is connected to the control gate. n
A data line DL is connected to a drain region forming one semiconductor region of the channel MISFET, and a common source line SL is connected to a source region forming the other semiconductor region. The common source line SL and word line WL extend in parallel directions, and the data line DL extends in a direction perpendicular to the word line WL and common source line SL.

One end of the word line WL is connected to an X-decoder (word line selection circuit) of the peripheral circuit. One end of the data line DL is connected to the data line drive circuit DR of the peripheral circuit, and the other end is connected to the input circuit DIB and output circuit DIB of the peripheral circuit through an n-channel MISFETQc that constitutes a column switch circuit. . The gate electrode of MISFETQc, which controls the column switch circuit, has Y
The output of one decoder (data line selection circuit) is supplied.

A p-channel MISFET Qs is connected to the common source line SL.
, and an n-channel MISFETQs2.
The output of MIS inverter circuit IV is supplied. CMI
MISFETQ, which is the input terminal of the S inverter circuit TV
A signal φ2 is supplied to each gate electrode of s,,Qs,.

The output circuit DOB including a sense amplifier circuit amplifies the signal supplied to the selected data line DL during a read operation and supplies the amplified signal to the input/output terminal I/O, and the human power circuit DIB amplifies the signal supplied to the selected data line DL during a read operation. The signal supplied from the external circuit to the input/output terminal /○ is supplied to the data line DL.

The above and other peripheral circuits are all configured with CMISFETs, similar to the CMIS inverter circuit IV.

When writing data to the memory cell Q+t+, the circuit reference voltage V's (for example, OV) is applied to the common source line SL through the n-channel MISFET QS2 of the inverter circuit IV, which is turned on by the high-level signal φ2. The data line DL is precharged to the circuit reference voltage VSS by the data line drive circuit DR, and then the predetermined data line DL selected by the Y-decoder is supplied with the power supply voltage VD+ from the input circuit DIB. , [
For example, 5V] is applied. A high voltage VppC, for example 1, is applied to a predetermined word line WL selected by the X-decoder.
2V] is applied. The high voltage v p p is supplied from an external circuit or generated from the power supply voltage vno by a booster circuit built into the chip. As a result, one memory cell Q has the power supply voltage VD+ applied to the data line DL and the high voltage VPP applied to the word line WL.
At m, hot electrons are injected from the drain region to the floating gate, and data is written.

When reading data from memory cell Qm, common source line SL
The power supply voltage VSS of the circuit is applied to through the n-channel MISFET Qs2 of the inverter circuit IV, which is made conductive by the high-level signal φ. All data lines DL are set in advance to the circuit reference voltage V by the data line drive circuit DR.
Precharged to DI1. A predetermined word line WL selected by the X-decoder is supplied with power supply voltages VI, D.
(or lower) high level signal is applied. When the threshold voltage VTN of the memory cell Qm is lower than the selection level of the word line WL, the memory cell Qm becomes conductive and the voltage of the data line DL becomes lower than the power supply voltage V0.

The threshold voltage VTll of memory cell Qm is the same as that of word line WL.
When the selection level is higher than the selection level, memory cell Qm becomes non-conductive, and the voltage of data line DL is maintained at the precharge level. Further, by selecting a specific data line with the Y-decoder, a voltage corresponding to the data of one selected memory cell Qm appears on the data line DL, and data reading is performed.

When erasing data in memory cell Qm, common source line S
A high voltage Vpp (for example, 12 V) is applied to L through the p-channel MISFET Qs of the inverter circuit IV, which is turned on by the low level signal φ8.With the high voltage VPP applied to the common source line SL, all word lines WL
is set to a low level by the X-decoder receiving the signal φ, and all data lines DL are set to the low level by the Y-decoder receiving the signal φE. As a result, electrons are emitted from the floating gates of all memory cells Qm to the source regions through the tunnel regions, and data is erased all at once.

FIG. 1 is a plan view showing the configuration of the memory cell array. Note that insulating films other than the field insulating film are not shown in FIG. 1 to simplify the explanation.

A semiconductor substrate (chip) 1 is made of, for example, p-type silicon single crystal, and a field insulating film 2 made of SiCh is provided on its main surface. Each of the field insulating films 2 extends continuously in the vertical direction of the drawing, that is, the Y direction, and is arranged at a predetermined interval in the horizontal direction of the drawing, that is, the X direction.

A floating gate 3 made of polysilicon, for example, is provided in the upper layer of the field insulating film 2 so as to span adjacent floating gates. A control gate 4 made of polysilicon, for example, is provided above the floating gate 3. Control gate 4 also serves as word 'aWL, and is arranged so as to overlap floating gate 3. Word line W
Each of L extends in the X direction and is arranged at a predetermined interval in the Y direction.

In the active region of the substrate 1 surrounded by the field insulating film 2 and the word line WL, a source region 5 and a drain region 6 made of, for example, an n-type semiconductor region are provided. All source regions 5 and drain regions 6 are separated from each other via field insulating film 2 and word line WL. Source regions 5 and drain regions 6 are alternately arranged along the direction in which field insulating film 2 extends.

A common source line SL and a conductive layer 7 are provided above the word ilWL. The common source line SL and the conductive layer 7 are made of polysilicon, for example. Each of the common source lines SL extends in the X direction and extends in the Y direction in the figure.
They are arranged at predetermined intervals in the direction. The common source line SL is provided so as to cover the source region 5,
It is electrically connected to source region 5 through contact hole 8a. The line width of common source line SL is wider than the width of source region 5 in the Y direction. That is, the common source line SL is provided so as to partially cover the 7-domain line WL. On the other hand, the conductive layers 7 are separated from each other in the X direction, and each covers the drain region 6. Conductive layer 7 connects drain region 6 through contact hole 8b.
electrically connected to. Conductive layer 7 has a larger area than drain region 6. That is, the conductive layer 7 is provided so as to partially cover the word line WL. When forming the common ground line SL and the conductive layer 7 in the same layer,
Both must be spaced apart in the Y direction.

A data wADL made of, for example, an aluminum alloy is provided above the common source line SL and the conductive layer 7. Each of the data RDLs extends in the Y direction and is arranged at predetermined intervals in the X direction of the figure. The data sDL is electrically connected to the conductive layer 7 through a through hole 23 not shown in FIG. That is,
Data line DL is electrically connected to drain region 6 through through hole 23, conductive layer 7, and contact hole 8b.

In this case, the flash of this embodiment 1. The memory cell Q+n of EEPR○M has a gate electrode with a two-layer structure consisting of a floating gate 3 and a control gate 4,
It is composed of a single n-channel MISFET having an n-type semiconductor region consisting of a source region 5 and a drain region 6, and the source region 5 and drain region 6 are
They are separated from each other via a word line WL and a field insulating film 2 extending in a direction perpendicular to the word line WL. Then, the control gate 4 of the memory cell Qm
A word line WL is integrally connected to the source region 5, a source line SL is connected to the source region 5, and a conductive layer 7 is connected to the drain region 6.
A data line DL is connected thereto.

2 is a cross-sectional view of the substrate l taken along the line II-IF in FIG. 1, and FIG. 3 is a cross-sectional view of the substrate l taken along the line
FIG.

As shown in FIGS. 2 and 3, the memory cell Qm is provided on the main surface of a p-well 9 provided in the substrate l.

The source region 5 constituting one semiconductor region of the memory cell Qm is composed of n semiconductor regions 5a having different impurity concentrations.
and n-semiconductor region 5b. That is, the second region 5 has a so-called double diffusion structure. By providing the n+ semiconductor region 5b with a low impurity concentration under the n+ semiconductor region 5a with a high impurity concentration, a high voltage vPP [for example, 12
When V] is applied, the electric field at the end of the semiconductor region 5a is relaxed, so that the junction leakage current of the memory cell Q+n can be reduced.

A p0 semiconductor region 10 doped with impurities of a conductivity type different from that of the drain region 6 is provided below the drain region 6, which is an n semiconductor region surrounding the other semiconductor region of the memory cell Qm.

By providing the P semiconductor region 10 in the lower layer of the drain region 6, when a power supply voltage Voo (for example, 5 V) is applied to the drain region 6 during data writing, the generation of hot electrons is promoted at the end thereof. Therefore, the efficiency of writing data into the memory cell Qm is improved.

Field insulating film 2 separating memory cells QITl from each other
A p-type channel stopper region l1 is provided below. The channel region of memory cell Qm has a threshold voltage V? A p-type channel doped layer l2 is provided for controlling II. For example, Sin. A gate insulating film l3 consisting of the following is provided.

A floating gate 3 is provided in the upper layer of the gate insulating film 13.
A gate electrode having a two-layer structure consisting of a control gate 4 (word line?L) and a control gate 4 (word line?L) is provided. The floating gate 3 and the control gate 4 are insulated from each other via a second gate insulating film 14 formed on the floating gate 3 and made of, for example, Si◯. Floating gate 3 and control gate 4
An insulating film 15 made of, for example, 3i0z by thermal oxidation is provided on the sidewalls of the semiconductor device and the control gate 4 . Sidewall spacers 16 extending in the gate length direction are provided on the sidewalls of the floating gate 3 and the control gate 4. The sidewall spacer 16 is made of, for example, SiO2 deposited by CVD.

An interlayer insulating film 20 made of, for example, S102 is provided above the insulating film 15 and the sidewall baser 16. A common source line S is provided in the upper layer of the interlayer insulating film 20.
L and a conductive layer 7 are provided. Common source line SL
And the upper layer of the conductive layer 7 includes, for example, B P S G (B
oroPhospho Silicate GlaSS
) is provided.

A data line DL is provided in the upper layer of the interlayer insulating film 22. The data line DL is electrically connected to the conductive layer 7 through a through hole 23 provided in the interlayer insulation film 22 . A puffivation film 25 for protecting the surface of the substrate 1 is provided on the upper layer of the data line DL. The puffivation film 25 is made of, for example, PSG (Phos
pho Silicate Glass).

Next, a flash memory consisting of the above-mentioned structure: LEEPROM
The manufacturing method will be explained using FIGS. 4 to 11. Fourth
In each of the figures from FIG.
Cb) is a sectional view of the substrate 1 taken along the line ■--■ in FIG. 1, similar to FIG. 3 above.

Note that here, to simplify the explanation, the memory cell Q
Only the manufacturing process of the n-channel MISFET which constitutes m will be explained, and the explanation of the manufacturing process of the C-MISFET which constitutes the peripheral circuit will be omitted.

First, as shown in FIG. 4, a p-type impurity is introduced into the main surface of a substrate 1 made of p-type silicon single crystal to form a p-well 9. p-well 9 is 5×lQ” ~lXI
Q” (atoms/cd) of BF2 from 50 to
7 After ion implantation with an energy of about QKeV,
Stretch and diffuse BFz to form a precept.

B.F. The ion implantation is performed on the Si formed on the main surface of the substrate 1.
This is done through an insulating film (not shown) made of Ch. Subsequently, a p-type impurity, for example, 5 x l Q
” ~l x l Q After ion implantation of about 13 (atoms/cd) of BF2 with an energy of about 40 to 5 QKeV, the so-called selective oxidation method (LOCOS method) is performed.
A field insulating film 2 is formed on a predetermined main surface of the p-well 9 using
, and at the same time, a p-type channel stopper region 11 is formed therebelow. The film thickness of the field insulating film 2 is 60
Approximately 00 to 8000 people. Next, after removing the insulating film on the main surface of the active region using, for example, a hydrofluoric acid aqueous solution, the substrate 1 is thermally oxidized to form an insulating film 17 made of Sigh on the main surface of the active region. A p-type impurity, for example, B, is ion-implanted into the main surface of the active region through this insulating film 17 to form a channel dove layer 12 for controlling the threshold voltage (Vt).

Next, after removing the insulating film l7 on the main surface of the active region with, for example, a hydrofluoric acid aqueous solution, as shown in FIG. A gate insulating film 13 is formed. The thickness of the gate insulating film l3 is
Approximately 100 to 150 people. Subsequently, a polysilicon film 18 for a floating gate is deposited on the upper layer of the gate insulating film 13 using the CVD method. The thickness of the polysilicon film 18 is about 2000 to 3000. Next, the polysilicon film 18 is coated with, for example, IX10'' (at
After reducing the resistance value by ion-implanting P with an energy of about 30 KeV (about 30 KeV), the polysilicon film 18 is etched along the center line of the field insulating film 2. Since field insulating film 2 extends in a direction perpendicular to word lines WL to be formed later, the main surface of the active region of substrate 1 is not etched when polysilicon film 18 is etched.

Next, as shown in FIG. 6, the substrate 1 is thermally oxidized to form a second gate insulating film 14 made of S l02 on the surface of the polysilicon film 18. The thickness of the second gate insulating film 14 is, for example, about 200 to 300 Å. Next, CVD
Second gate insulation using method! A polysilicon film 19 for a control gate (word line WL) is deposited on the upper layer of 14. The film thickness of the polysilicon film l9 is 2000 to 300
Approximately 0 people.

Next, after the polysilicon film 19 is subjected to phosphorus treatment to lower its resistance value, as shown in FIG.
8. After etching the second gate insulating film 14 and the polyrecon film 19 by overlapping cutting to simultaneously form the floating gate 3 and the control gate 4 (word line WL), the substrate 1 is thermally oxidized to form the floating gate 3.
An insulating film 15 made of S+Ch is formed on each sidewall of the control gate 4 (word line WL) and on the control gate 4 (word line WL).

The thickness of the insulating film 15 is approximately 70 to 80 Å. In addition,
The control gate 4 (word line WL) is made of a composite film with a so-called polycide structure, in which a silicide film of a high melting point metal such as W, Ta%TiSMO, etc. is laminated on a polysilicon film, or a composite film of the above high melting point metal (or its silicide). It may be composed of a single layer film.

Next, as shown in FIG. 8, impurities are introduced into the main surface of the active region to form a source region 5 and a drain region 6. To define the source region 5 and drain region 6,
First, n-type impurities are introduced into the main surface of the active region where source region 5 is to be formed in order to form source region 5b. In order to introduce an n-type impurity, for example, I
1 X O” [atoms/cII1] of P is 5
Ion implantation is performed with an energy of approximately 0 KeV. The n-type impurity is introduced into floating gate 3 and control gate 4 (word line WL) in a self-aligned manner. Subsequently, p-type impurities are introduced to form a region 10 on the main surface of the active region where the drain region 6 is to be formed.

In order to introduce p-type impurities, for example, 5810'3~1,
Ions of BF2 of about 5 x l Q 1 (atoms/c++f) are implanted at an energy of about 60 KeV. The p-type impurity is introduced into the floating gate 3 and the control gate 4 (word line WL) in a self-aligned manner. Thereafter, the substrate 1 was placed in nitrogen gas for 100
Heat treatment is performed at approximately 0° C. to stretch and diffuse the n-type impurity and p-type impurity, thereby forming an n-semiconductor region 5b on the main surface of the active region where the source region 5 is to be formed, and forming the drain region 6. A p° semiconductor region 10 is formed on the main surface of the desired active region. Pull-in semiconductor regions 5b and p
The junction depth of each semiconductor region 10 is about 0.5 μm.

Next, n-type impurities are introduced into the main surface of the active region in which the n-semiconductor region 5b is formed. In order to introduce an n-type impurity, for example, 5 X 10" to I X 10" (atom
s/cj) is ion-implanted with an energy of about 5 QKeV. The n-type impurity is applied to the bloating gate 3 and control gate 4 (word line WL).
is introduced in a self-consistent manner.

Subsequently, n-type impurities are introduced into the upper surface of the active region in which the p' semiconductor region 10 is formed. To introduce n-type impurities,
For example, I X 10" to 5 X 10" (at
OmS/cII! ] of As is ion-implanted with an energy of about 60 KeV. The n-type impurity is introduced into floating gate 3 and control gate 4 (word line WL) in a self-aligned manner.

Thereafter, the substrate l is heat-treated at about 1000° C. in nitrogen gas to stretch and diffuse each of the n-type impurities described above, and the n-semiconductor region 11j! n semiconductor region 5 on 5b
At the same time, an n semiconductor region 6 is formed on the p semiconductor region 10. The junction depths of n' semiconductor region 5a and n semiconductor region 6 are each about 0.3 μm.

Next, as shown in FIG. 9, a sidewall spacer 16 is formed on the sidewall of the floating gate 3 and the control gate 4 (word line WL). channel MISFET and p-channel MISFET
)D (Lightly Doped Drain) When preparing the side wall spacer for the structure, use the same method. The sidewall spacer l6 is, for example, an insulating film made of Sin2 deposited using the CVD method (
(not shown) to RI E (Reactive Ion E
tching). Subsequently, an interlayer insulating film 20 is formed on the insulating film 15 and sidewall spacers 16 formed by thermal oxidation.
Deposit. The interlayer insulating film 20 is made of, for example, SiO formed by thermal decomposition of organic silane, and has a thickness of 150 mm.
Approximately 0 people.

Next, as shown in FIG. 10, the interlayer insulating film 20 and the gate insulating film 13 are etched to simultaneously form a contact hole 8a reaching the main surface of the source region 5 and a contact hole 8b reaching the main surface of the drain region 6. After admonishing
A polysilicon film 21 for the common source line SL and the conductive layer 7 is deposited on the interlayer insulating film 20 using the CVD method. The thickness of the polysilicon film 21 is 1000 to 1500A.
That's about it. Subsequently, the polysilicon film 21 is subjected to phosphorus treatment to reduce its resistance value, and then the polysilicon film 21 is etched to form a common source line SL connected to the source region 5 and a conductive layer connected to the drain region 6. 7 is formed at the same time. Each of the common source line SL and the conductive layer 7 is formed to cover a part of the control gate 4 (word line WL). Note that the common source line SL and the conductive layer 7 are made of WSTa, Ti, M on the polysilicon film.
It may be constructed of a composite film having a polycide structure in which silicide films of high melting point metals such as silicide films of high melting point metal such as o are laminated, or a single layer film of the above high melting point metal (or its silicide).

Next, as shown in FIG. 11, an interlayer insulating film 22 made of, for example, BPSG is deposited on the common source line SL and the conductive layer 7 using the CVD method, and then the substrate 1 is heat-treated to form a glabellar insulating film. 22 is flattened. The thickness of the interlayer insulating film 22 is about 5000 to 6000. Subsequently, after etching the glabellar insulating film 22 to form a through hole 23 that reaches the conductive layer 7, the interlayer insulating film 2 is etched using a spatter method.
An Al alloy film 24 for the data line DL is deposited on the upper layer of the data line DL. The thickness of the Al alloy film 24 is about 8,000.

Finally, after etching the A1 alloy film 24 to form a data line DL connected to the conductive layer 7, a puffivation film 25 made of, for example, PSG is deposited on the upper layer of the data line DL. The memory cell Qm shown in FIGS. 1 to 3 is completely cured.

According to the first embodiment configured as described above, the following effects can be obtained.

(l). The field insulating film 2 is continuously extended in the direction perpendicular to the word line WL, and the area of the region where the floating gate 3 and the source region 5 overlap is the same as that of all the memory cells Q.
It becomes equal at m. Therefore, as a result of the coupling capacitance between the floating gate 3 and the source region 5 being equal in all memory cells Qm, the floating gate voltage V, when a high voltage is applied to the source region during erasing, is Since all memory cells Qm are equal, variations in data erase characteristics are eliminated and flash EEPR
The electrical characteristics of OM are improved.

(2). The field insulating film 2 is continuously extended in the direction orthogonal to the word line WL, and when etching the polysilicon film 18 for the floating gate 3, the polysilicon film 19 for the control gate 4, and the polysilicon film 19 for the floating gate 3. Since the active region of the substrate 1 is not etched when the silicon film 18 is etched by overlapping cuts, it is possible to prevent the occurrence of junction leakage current due to scraping of the substrate 1.
The electrical characteristics of ROM are improved. Further, since disconnection of the source region 5 due to scratching of the substrate 1 can be prevented, the manufacturing yield of the flash EEPROM is improved.

(3). Since the upper layer of the word line WL is covered with the common source line SL and the conductive layer 7, the puffivation film 2
The common source line SL and the conductive layer 7 can block foreign substances such as moisture that reach the gate electrode through the common source line SL and the interlayer insulating film 22. As a result, diffusion of electrons injected into the floating gate 3 during data writing can be prevented, so that the flash. The data retention characteristics of EEPROM are improved.

(4). Since the data line DL is connected to the drain region 6 via the conductive layer 7 formed on the upper layer of the drain region 6, the through hole 23 formed in the interlayer insulating film 22
As a result, the coverage of the data line DL Al alloy film 24 deposited in the through hole 23 is improved, so the data line DL connection reliability is improved.

[Example 2] This Example 20 semiconductor integrated circuit device is a flash EEP
This is a ROM, and FIG. 13 is a plan view showing the configuration of its memory cell array. Note that, in FIG. 13, insulating films other than the field insulating film are not shown in order to simplify the explanation.

As shown in FIG. 13, the memory cell Qm is provided in a region where a field insulating film 2 extending continuously in the Y direction of the figure and a word line WL extending in the X direction of the figure intersect. There is. The memory cell Qm is a single n-channel having a gate electrode with a two-layer structure consisting of a floating gate 3 and a control gate 4 (word line WL), and an n-type semiconductor region consisting of a source region 5 and a drain region 6. It is composed of MISFET. The source region 5' and the drain region 6 are separated from each other via the field insulating film 2 and the word line WL, a common source line SL is connected to the source region 5, and a common source line SL is connected to the drain region 6 via a conductive layer 7. A data line DL is connected thereto. The common source line SL extends in the X direction in the figure and is connected to the data line DL.
extends in the Y direction of the figure.

In the flash LEEPROM of Example 1, the common source line SL is connected to the source region 5 through a contact hole 8a provided in a part of the interlayer insulating film 20, and a contact hole 8b also provided in a part of the interlayer insulating film 20. The conductive layer 7 is connected to the drain region 6 through the flash EEPROM of the second embodiment.
The common source wAsL is directly connected to the source inertial region 5, and the same conductive layer 7 is also directly connected to the drain region 6.

FIG. 14 is a sectional view of the substrate 1 taken along the line XrV-XIV in FIG. 13. As shown in FIG. 14, the memory cell Qm is provided on the main surface of a p-well 9 provided in the substrate l. The source region 5 of the memory cell Qffl has a double diffusion structure consisting of an n' semiconductor region 5a and an n1 semiconductor region 5b, and a p' semiconductor region 10 is provided below the drain region 6. . A channel dove layer 12 is provided in the channel region of the memory cell Qm, and a gate insulating film 13 is provided above the channel dove layer 12.

Floating gate 3 and control gate 4
(Word lines WL) are insulated from each other via a second gate insulating film l4 provided on the floating gate 3. An insulating film 15 and a sidewall baser 16 are provided on the sidewalls of the floating gate 3 and the control gate 4 (word IWL). An interlayer insulating film 20 is provided on the control gate 4 (word line WL).

A common source line SL and a conductive layer 7 are provided above the sidewall spacer 16 and the interlayer insulating film 20. Common source line SL is directly connected to source region 5 , and conductive layer 7 is directly connected to drain region 6 .

Common source line SL and conductive layer 7 are provided in a self-aligned manner with respect to sidewall spacers 16 of memory cells Qm adjacent in the Y direction.

A glabellar insulating film 22 is provided above the common source line SL and the conductive layer 7, and an upper layer of the interlayer insulating film 22 includes:
A data line DL is provided.

Data line DL is electrically connected to conductive layer 7 through a through hole 27 provided in interlayer insulating film 22 .

A puffivation film 25 is provided on the upper layer of the data line DL.

Next, a flash having the above-mentioned configuration. A method for manufacturing an EEFROM will be explained using FIGS. 15 to 18. 1st
Figures 5 to 18 correspond to XI in Figure 13, same as Figure 14 above.
FIG. 2 is a cross-sectional view of the substrate 1 taken along the line V-XIV.

FIG. 15 shows an intermediate stage of the manufacturing process of this flash 5EEPROM, and corresponds to the manufacturing process shown in FIG. 76 of the embodiment 1. That is, p is on the main surface of the substrate 1.
After introducing type impurities, the so-called selective oxidation method (LOCO) is carried out.
A field insulating film 2 is formed using the S method (S method), and at the same time, a p-type channel stopper region 11 is formed below it.

Field insulating film 2 is shaped so as to extend in a direction perpendicular to word line WL. Subsequently, after forming a gate insulating film l3 on the main surface of the active region, a polysilicon film 18 for a floating gate is deposited on the upper layer of the field insulating film 2 and the gate insulating film l3, and the polysilicon film 18 on the field insulating film 2 is Membrane 18 is etched along its centerline. The field insulating film 2 is a word line W formed later.
Since it extends continuously in the direction perpendicular to L, the main surface of the active region of the substrate 1 is not etched when the polysilicon film 18 is etched. Subsequently, after thermally oxidizing the substrate 1 to form a second gate insulating film 14 on the surface of the polysilicon film 18, a control gate (
A polysilicon film 19 for word line WL) is deposited and subjected to phosphorus treatment to reduce its resistance value. The steps up to this point are the same as in Example 1 above. Next, in this second embodiment,
An interlayer insulating film 2o is deposited on the polysilicon film 19.

Interlayer insulating film 20 is formed to insulate control gate 4 (word line WL) from common source line SL and conductive layer 7. The interlayer insulating film 2o is formed, for example, by thermal decomposition of organic silane.

Next, as shown in FIG. 16, the polysilicon film 18, second gate insulating film 14, polysilicon film 19, and interlayer insulating film 20 are etched in an overlapping manner to remove the floating gate 3 and control gate 4 (word line WL). ) are formed at the same time, the substrate l is thermally oxidized to form a floating gate 3 and a control gate 4 (word line WL).
) is coated with an insulating film 15 made of Si. Next, impurities are introduced into the main surface of the active region to form the source region 5.
and drain region 6 is formed. The source region 5 and the drain region 6 may be formed by the same method as in the first embodiment, so their explanation will be omitted.

Next, as shown in FIG. 17, the floating gate 3
A sidewall spacer 16 is then formed on the sidewall of the control gate 4 (word line WL). For example, the sidewall spacer 16 connects an n-channel MISFET and a p-channel MISFET of a scrap circuit (not shown) to an LD.
It is formed at the same time as forming the sidewall spacer for forming the D structure. Sidewalls base 16 is
For example, an insulating film made of Sin deposited using the CVD method is processed by anisotropic etching such as RIE. In the second embodiment, in the etching process when forming the sidewall baser 16, the gate insulating film 13 on the main surfaces of the source region 5 and drain region 6 is over-etched and removed.

In this etching step, the interlayer insulating film 20 on the control gate 4 (word line WL) is also etched at the same time.
In order to prevent the surface of L) from being exposed, the interlayer insulating film 2 is
The film thickness of 0 is set to be about 2000 to 3000A.

Next, as shown in FIG. 18, a polysilicon film 21 is deposited on the interlayer insulating film 20 and the side-all spacer l6 using the CVD method, and a phosphorus treatment is performed to reduce its resistance value. The common source line SL and the conductive layer 7 are simultaneously etched by etching the silicon film 2l. Common source line SL and conductive layer 7 are each formed to cover part of control gate 4 (word l[WL). The control gate 4 (word line WL) and the common source line SL (conductive layer 7) are made of a composite structure with a so-called polycide structure, in which a silicide film of a high-melting point metal such as W, Ta1Ti, or Mo is laminated on a polysilicon film. It may be composed of a film or a single layer film of a high melting point metal (or its silicide). The steps after forming the common source line SL and the conductive layer 7 may be the same as those in Example 1, so the description thereof will be omitted.

In this way, the control gate 4 (word line WL>
An interlayer insulating film 20 is deposited thereon, and then a bloating gate 3 and a control case }4 (word 1l!WL
), and at the same time remove the gate insulating film 13 on the main surfaces of the source region 5 and drain region 6, the main surfaces of the source region 5 and drain region 6 are exposed. According to the manufacturing method of the second embodiment in which the polysilicon film 21 for the common source line SL is deposited in a state where the common source line SL and the conductive layer 7 are
word line WL) and sidewall baser 16 in a self-aligned manner.

Therefore, according to the second embodiment, there is no need for a margin for mask alignment when forming the contact holes 3a and 8b as in the first embodiment, and the areas of the source region 5 and the drain region can be reduced accordingly. Therefore, memory cell Q
The size of m can be reduced and the degree of integration of the flash EEPROM can be improved.

[Example 3] The semiconductor integrated circuit device of Example 3 has a flash: LEE.
This is a PROM, and FIG. 19 is a plan view showing the configuration of its memory cell array. Note that in FIG. 19, insulating films other than the field insulating film are not shown to simplify the explanation.

In the memory cell arrays of the first and second embodiments, the field insulating film 2 separating the memory cells Qm is connected to the word I.
This field insulation IN extends in a direction perpendicular to WL.
The memory cell array of the third embodiment has a structure in which a common source line SL is connected to a source region 5 surrounded by a word line WL and a word line WL, as shown in FIG.
Each of the field insulating films 2 is formed separately and arranged in an island shape. Therefore, since all the memory cells Q+n connected to one word line WL share their source regions 5, there is no common source line SL for connecting the source regions 5.

On the other hand, the drain region 6 is connected to the field insulating films 2 and 7.
- data lines D@WL, and each drain region 6 is connected to a data line D through a contact hole 28.
L is connected.

20 is a sectional view of the substrate 1 taken along line xx-xx in FIG. 19, and FIG. 21 is a sectional view taken along line XXI-XXI in FIG. 19.
22 is a sectional view of the substrate 1 taken along the line xxn-xxn in FIG. 19. FIG.

As shown in FIGS. 20 and 21, memory cell Qm
is provided on the main surface of the p-well 9 provided on the substrate l. The source region 5 of the memory cell Qm is the n゛ semiconductor region 5
It has a double expansion structure consisting of a and n semiconductor regions 5b. A p° semiconductor region 10 is provided below the drain region 6 . A p-type channel stopper region 11 is provided under the field insulating film 2 that separates the memory cells Qm from each other.

As shown in FIG. 20, the field insulating film 2 has a sidewall of the source region 5m perpendicular to the main surface of the substrate 1, and a sidewall of the bloating gate 3 and the control gate 4 (word line WL). are on the same plane. Therefore, at the end of the field insulating film 2 on the source region 5 side, there is a so-called bird's peak.
k) There is no overhang called .

On the other hand, as shown in FIG. 21, a bird's peak exists at the end of the field insulating film 2 in the X direction. In other words, the thickness of the field insulating film 2 at the ends in the X direction is smaller than that at the center.

Bloating gate 3 and control gate 4
(words IIWL) are isolated from each other via a second gate insulating film 14 formed on the floating gate 3. An insulating film 15 formed by thermal oxidation is provided on the side walls of the floating gate 3 and the control gate 4 (word line WL). The insulating film 15 is also provided on the substrate surface of the control gate 4 (word line WL) and source region. The side wall base 16 is attached to the floating gate 3 as shown in FIG.
, the control gate 4 (word line WL) and the side wall of the field insulating film 2.

An interlayer insulating film 20 is provided above the insulating film 15 . A data line DL is provided in the upper layer of the interlayer insulating film 20. As shown in FIGS. 21 and 22, the data line DL is connected to the drain region 6 through the contact hole 28 provided in the interlayer insulating film 22 and the gate insulating film 13.
electrically connected to. In the upper layer of the data line DL,
A puffivation film 25 is provided.

Next, a method for manufacturing a flash EEPROM having the above-described structure will be explained using FIGS. 23 to 26. Second
3 to 25, (a) is a cross-sectional view of the substrate 1 taken along line xx-xx in FIG. 19 as in FIG. XX of
FIG. 2 is a cross-sectional view of the substrate l taken along the I-XX T line.

FIG. 23 shows an intermediate stage of the manufacturing process of this flash EEPROM, which corresponds to the manufacturing process shown in FIG. 6 of the first embodiment. That is, after introducing p-type impurities into the main surface of the substrate 1, a so-called selective oxidation method (LOCOS) is applied.
A field insulating film 2 is formed using a method (method), and at the same time, a p-type channel stopper region 11 is formed under the field insulating film 2. The field insulating film 2 is formed so as to extend continuously in the direction perpendicular to the word line WL, as in the first embodiment. Subsequently, after forming a gate insulating film 13 on the main surface of the active region, a field insulating film 2 and a gate insulating film l are formed.
Polysilicon film l for 7 loading gates on top of 3
8 is deposited, and this polysilicon film 18 is etched along the center line of the field insulating film 2. Since field insulating film 2 extends in a direction perpendicular to word line WL, the main surface of the active region of substrate 1 is not etched when polysilicon film 18 is etched.

After that, the substrate 1 is thermally oxidized to form a second gate insulating film 14 on the surface of the polysilicon film 18, and then a polysilicon film 1 for the control gate (word line WL) is formed on the second gate insulating film 14.
9 is deposited and subjected to phosphorus treatment to reduce its resistance value.

The steps up to this point are the same as in Example 1 above.

Next, as shown in FIG. 24, the polysilicon film 18, second gate insulating film l4, and polysilicon film 19 are etched in an overlapping manner to simultaneously form floating gates 3 and control gates 4 (word lines WL>). In the third embodiment, the photoresist mask 29a used in this etching step is left on the control gate 4 (word line WL) and the process moves to the next step.

Subsequently, as shown in FIG. 25, a photoresist mask 2 is applied.
After forming a second photoresist mask 29b on 9a, the field insulating film 2 on the region where the source region 5 is to be formed is removed by etching. As the etching gas, for example, CF. , CHF3, and Ar into the chamber at a ratio of 1:2:40, the selectivity with silicon can be increased to 10 or more. As a result, the field insulating film 2, which had been extending in the direction perpendicular to the word line WL, is separated into islands, and the sidewalls on the source region 5 side of each of the loading gates 3 and control gates 4 (word lines WL ) is flush with the side wall of the

Next, after removing the photoresist masks 29a and 29b, as shown in FIG. control gate 4
An insulating film 15 is formed on the side walls of (word line WL) and control gate 4 (word line WL), and then impurities are introduced into the main surface of the active region to form source region 5 and drain region 6. The source region 5 and the drain region 6 may be formed by the same method as in the first embodiment, so their explanation will be omitted. Note that the field insulating film 2
The channel stopper region 11 formed in the lower layer has a higher concentration of p-type impurities than the channel stopper region 1l in the bird's peak portion. Therefore, the end of the source region 5 formed in the region where the field insulating film 2 is removed is in contact with the channel stopper region 11 having a high impurity concentration, so there is a problem that the junction breakdown voltage is likely to decrease. By forming the source region 5 into a double diffusion structure of the n' semiconductor region 5a and the n1 semiconductor region 5b, a reduction in the junction breakdown voltage at the end of the source region 5 can be effectively prevented.

Next, after etching the interlayer insulating film 22 deposited on the upper layer of the insulating film 15 to form a contact hole 28 that reaches the drain region 6, the data line D is formed on the upper layer of the interlayer insulating film 22.
20.L is formed, and finally, a puffivation film 25 is deposited on the upper layer of the data line DL, as shown in FIG. Second
The memory cell Qm shown in FIGS. 1 and 22 is completed.

According to the third embodiment configured as described above, the following effects can be obtained.

(1). The field insulating film 2 is extended in a direction orthogonal to the word line WL, the polysilicon film 18 for the floating gate 3 is etched, and the polysilicon film 19 for the control gate 4 and the polysilicon film 18 for the floating gate 3 are etched. Since the active region of the substrate 1 is prevented from being etched when etching is performed by overlapping cutting, the substrate 1 can be prevented from being scraped. the result,
Since the occurrence of junction leakage current due to scratching of the substrate 1 can be prevented, the electrical characteristics of the flash EEPROM are improved. Further, since disconnection of the source region 5 due to scratching of the substrate 1 can be prevented, the manufacturing yield of the flash EEPROM is improved.

(2) After forming the floating gate 3 and the control gate 4 (word line WL) on the field insulating film 2 extending continuously in the direction perpendicular to the word line WL, the source region 5 should be formed. By removing the field insulating film 2 in the region, the sidewall of the field insulating film 2 on the source region 5 side is made to be flush with the sidewalls of the floating gate 3 and the control gate 4 (word line WL). The area of the area where 3 and source region 5 overlap is the area of all memory cells Q
It becomes equal at m. Therefore, the coupling capacitance formed between the floating gate 3 and the source region 5 becomes equal in all memory cells Qm, and as a result, the floating gate voltage , becomes the same in all memory cells Qm, so the data erase characteristics Flush E
The electrical characteristics of EPROM are improved.

(3). As shown in FIG. 27, since there is no need to secure an alignment margin between the end of the field insulating film 2 in the Y direction and the floating gate 3, the interval between each memory cell in the Y direction can be reduced. As a result, the degree of integration of the flash: LEEPROM can be improved.

(4). A second photoresist mask 29 is placed on the photoresist mask 29a used when forming the floating gate 3 and control gate 4 (word line WL).
Since the field insulating film 2 is etched after forming the second photoresist mask 29b, the control gate 4 (word line WL
) can prevent the side walls from being scraped.

As above, the invention made by the present inventor has been specifically explained based on Examples, but it should be noted that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Not even.

In the first to third embodiments described above, a flash memory device that electrically erases data all at once is used. Although we have explained the case where it is applied to EEPROM, this type of flash EEFROM
It can also be applied to a microcomputer with a built-in.

〔Effect of the invention〕

Among the inventions disclosed in this application, the effects obtained by typical inventions are briefly described below.

(l). According to the present invention, a field insulating film separating memory cells is continuously extended in a direction perpendicular to the word line, and a common source line is connected to a source region surrounded by the field insulating film and the word line. Since the area of the region where the floating gate and the source region overlap is the same for all memory cells, variations in data erase characteristics are eliminated and the electrical characteristics of the EEPROM are improved.

In addition, a field insulating film that separates memory cells is arranged to extend continuously in a direction perpendicular to the word line, and at least the polysilicon film for the floating gate and the polysilicon film for the control gate are etched in an overlapping manner. Since the field insulating film remains until the process, the substrate is prevented from being scraped when etching the polysilicon film for the floating gate, preventing junction leakage current and improving the electrical characteristics of the EEPROM. do. Furthermore, since disconnection of the source region due to scratching of the substrate can be prevented, the manufacturing yield of the EEPROM is improved.

(2). According to the invention of the present application in which the common source line is formed in a self-aligned manner with respect to the gate electrode, a contact hole connecting the common source line to the source region is not required, so the size of the memory cell is reduced and the size of the EEPROM is reduced. The degree of integration is improved.

[3). After forming a two-layer gate electrode on a field insulating film extending in a direction perpendicular to the word line, the field insulating film in the area where the source region should be formed is removed by etching, and the sidewall on the source region side becomes a two-layer gate electrode. According to the invention of the present application, which forms a field insulating film flush with the sidewalls of the gate electrode, the area of the region where the floating gate and the source region overlap is the same for all memory cells, so variations in data erase characteristics can be reduced. is eliminated, and the electrical characteristics of the EEPROM are improved.

Further, since the polysilicon film for the floating gate is etched while the field insulating film separating the memory cells extends in a direction perpendicular to the word line, the substrate is prevented from being scraped. As a result, the occurrence of junction leakage current due to abrasion of the substrate is prevented, and the electrical characteristics of the EEPROM are improved. Furthermore, disconnection of the source region due to scratching of the substrate is prevented, and the manufacturing yield of the EEPROM is improved.

Furthermore, since no bird peak exists at the end of the field insulating film on the source region side, the size of the memory cell is reduced and the degree of integration of the EEFROM is improved.

[Brief explanation of drawings]

FIG. 1 is a plan view of a main part of a semiconductor substrate showing a memory cell array of a semiconductor integrated circuit device according to an embodiment of the present invention, FIG. 2 is a sectional view taken along the line 4(a), (b) to 11(a), (b) are sectional views of essential parts of a semiconductor substrate showing the manufacturing method of this semiconductor integrated circuit device. FIG. 12 is a circuit diagram of a memory cell array and some peripheral circuits of this semiconductor integrated circuit device, and FIG. 13 is a plan view of a main part of a semiconductor substrate showing a memory cell array of a semiconductor integrated circuit device according to another embodiment of the present invention. , FIG. 14 is a sectional view taken along the XrV-XrV line of FIG. 1, and FIGS. 15 to 181! 119 is a sectional view of a main part of a semiconductor substrate showing a method of manufacturing this semiconductor integrated circuit device; FIG. 119 is a plan view of a main part of a semiconductor substrate showing a memory cell array of a semiconductor integrated circuit device according to another embodiment of the present invention; 20 is a sectional view taken along the line xx-xx of FIG. 19, FIG. 21 is a sectional view taken along the line XXI-XXI of FIG.
xxn-xxn line sectional view of the figure, Fig. 23 (a), (b)
26(a) and 26(b) are cross-sectional views of essential parts of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device, and FIG. 27 is a main part of a semiconductor substrate showing a memory cell array of a conventional semiconductor integrated circuit device. 28 to 30 are plan views of main parts of a semiconductor substrate showing a conventional method of manufacturing a semiconductor integrated circuit device. 1.30... Semiconductor substrate, 2.33... Field insulating film, 3.35... Floating gate, 4.3
6... Control gate, 531... Source region, 6.32... Drain region, 7... Conductive layer, 8
a+ 8 b+ 4 u+ J'j...Contact hole, 9...P well, 10...p° semiconductor region, l1...Channel stopper region, l2...
Channel doped layer, 13... Gate insulating film, 14...
・Second gate insulating film, 15.17... Insulating film, 16・
・・Side wall spacer, 18, 19.21.37
...Polysilicon film, 20.22...Interlayer insulating film,
23.27... Through hole, 24... Aluminum alloy film, 25... Passivation film, 29a, 2
9b...Photoresist mask, 38...Groove, DL・
...Data line, SL...Common source line, W L...
word line.

Claims (1)

[Claims] 1. Comprised of a MISFET with a double-layer gate electrode structure consisting of a floating gate and a control gate,
A semiconductor integrated circuit device having a nonvolatile memory cell that erases data by applying a high voltage to a source region,
A field insulating film separating the memory cells is continuously extended in a direction perpendicular to the word line, and a common source line is connected to a source region surrounded by the field insulating film and the word line. semiconductor integrated circuit devices. 2. The semiconductor integrated circuit device according to claim 1, wherein a part of the common source line covers the word line. 3. The semiconductor integrated circuit according to claim 1, wherein the source region of the MISFET constituting the memory cell has a double diffusion structure consisting of a semiconductor region with a high impurity concentration and a semiconductor region with a low impurity concentration. Device. 4. The semiconductor integrated circuit device according to claim 1, further comprising a semiconductor region of a conductivity type different from that of the drain region provided below the drain region of the MISFET constituting the memory cell. 5. The semiconductor integrated device according to claim 1, wherein a conductive layer made of a conductive film for a common source line is connected to the drain region of the MISFET constituting the memory cell, and a data line is connected to the conductive layer. circuit device. 6. The semiconductor integrated circuit device according to claim 5, wherein a part of the conductive layer covers the word line. 7. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the common source line is formed in a self-aligned manner with respect to the two-layer gate electrode consisting of the floating gate and the control gate. 8. After forming a sidewall spacer on the sidewall of a two-layer gate electrode consisting of a floating gate and a control gate, a common source line is formed in a self-aligned manner with respect to the two-layer electrode and sidewall spacer. The method for manufacturing a semiconductor integrated circuit device according to claim 7. 9. A semiconductor integrated circuit device having a nonvolatile memory cell constituted by a MISFET with a double-layered gate electrode structure consisting of a floating gate and a control gate, wherein the sidewall on the source region side of the field insulating film separating the memory cells is . A semiconductor integrated circuit device, wherein the semiconductor integrated circuit device is flush with a side wall of the two-layer gate electrode. 10. The semiconductor integrated circuit according to claim 9, wherein the source region of the MISFET constituting the memory cell has a double diffusion structure consisting of a semiconductor region with a high impurity concentration and a semiconductor region with a low impurity concentration. Device. 11. The semiconductor integrated circuit device according to claim 9, further comprising a semiconductor region of a conductivity type different from that of the drain region provided below the drain region of the MISFET constituting the memory cell. 12. Sequentially deposit a conductive film for a floating gate and a conductive film for a control gate on the field insulating film extending in a direction perpendicular to the word line, and deposit the conductive film for the floating gate and the conductive film for the control gate in sequence. 10. The method according to claim 9, wherein the field insulating film in a region where a source region is to be formed is removed by etching after a two-layer gate electrode consisting of a floating gate and a control gate is simultaneously formed by overlapping etching. A method for manufacturing a semiconductor integrated circuit device. 13. Claim characterized in that the field insulating film is etched by forming a second photoresist mask on the photoresist mask used when etching the conductive film for the floating gate and the conductive film for the control gate by overlapping cutting. 13. The method for manufacturing a semiconductor integrated circuit device according to 12.