JPH0352050A - Bus address setting system - Google Patents

Abstract

PURPOSE:To simplify the constitution, to eliminate trouble due to human error, and to easily construct an optional system by providing an address storage means, an address setting completion storage part, and an address decision part. CONSTITUTION:This system is provided with the address setting completion storage part 35 which holds a state signal indicating that address setting to the address storage means 31 is completed and sends out the state signal to a trailing-stage board through an address setting completion signal line Li. Further, the system is provided with the address decision part 34 which compares a set address held in the address storage part 31 after the address setting completion with an address on a bus 4 to decide whether or not the address on the bus is an address for its board access. Consequently, troublesome manual address setting operation and human error pertaining thereto are eliminated to improve the reliability and simplify the hardware constitution and an optional system is easily constructed.

Description

Detailed Description of the Invention [Object of the Invention] (Industrial Application Field) The present invention provides a bus having an address setting function in which addresses are set for a plurality of slave boards connected to the same boat under the control of a master board. Related to Address Setting Method (Prior Art) Conventionally, in a device configuration in which a plurality of daughter boards are connected to a motherboard via a bus via connectors, it is generally necessary to set a unique address range for each board. Conventionally, as an address setting means for this type of address setting, there has been a means for providing an address setting switch for each board and setting a unique address for each board by operating the switch.However, this type of address setting When configuring the device, it is necessary to manually operate a switch for each board to set a unique address for that board, which is prone to human error, and requires a switch for setting the address for each board. However, due to the switch structure, there were problems in terms of reliability and mounting space.As a means to overcome the disadvantages of providing this address setting switch, a daughter board was connected to the bus. Provide multiple address range specification bins on the connector for
In order to have a unique value for each daughterboard, the upper bit of the address on the motherboard for each slot is set to 1° and 0. There is a method for recognizing addresses. However, this method requires increasing the number of address range designation pins on the connector according to the number of daughter boards, and therefore, as the system configuration becomes larger, This has the disadvantage that the number of usable bins decreases and there are significant restrictions on the system configuration and circuit.Also, since the address is fixed at the mounting position Wt. (mounting slot position), If boards with different exclusive address ranges coexist, there will be no flexibility in the mounting position (for example, there will be restrictions such as having to create a space for one board for a board with a wide address range).
It had the following drawback. (Problem to be Solved by the Invention) As mentioned above, in a device configuration in which multiple daughter boards are connected to a motherboard via a bus through connectors, when setting a unique address range for each board, conventional Then, we will provide a switch for setting an address for each board, and set a unique address for each board by operating this switch, or we will set a bin for specifying an address range on the connector for connecting the daughter board to the bus. Provide multiple
means for setting the upper bits of the address for each slot so that each daughter board has a unique value;
However, the method of providing a switch for setting an address has problems in terms of reliability and mounting space due to the switch structure, and requires manual operation to set a unique address for each board. Therefore, there are problems such as the possibility of human error, and the method of providing multiple address range specification bins on the connector requires increasing the number of address range specification bins on the connector according to the number of daughter boards mounted. As the system configuration becomes larger, the number of bins used for original board-to-board circuit connections decreases, which has the disadvantage of being subject to significant system configuration and circuit constraints, and the address is fixed at the mounting position. Therefore, there is a drawback that there is no flexibility in the mounting position, especially when boards with different address exclusive ranges are mixed. The present invention has been made in view of the above-mentioned circumstances.In a device configuration in which a plurality of daughter boards are bus-connected to a motherboard via connectors, when setting a unique address range for each board, it is necessary to use hardware for address setting. By reducing the need for switches and requiring only one set of daisy chain connection signals to assign addresses to the connectors, it is possible to simplify the configuration, eliminate troubles caused by human error, and improve system performance. It is an object of the present invention to provide a bus address setting method that can easily construct an arbitrary system by eliminating constraints on the hardware of the configuration. [Structure of the Invention] (Means and Effects for Solving the Problems) The present invention relates to a bus address setting method in which a master board and a plurality of slave boards are connected via a bus, and the master board sets the address of each slave board. The above bus is provided with an address setting completion signal line that is daisy-chain connected to each of the boards and sequentially transmits the completion of address setting to the next board, and each of the slave boards has an address setting completion signal line. address storage means that holds the set address on the bus when the input/output and signal relationships of the bus are in a specific state; and an address storage means that holds a status signal indicating that the address setting to this address storage means has been completed and outputs the same status signal. The address setting completion storage unit sends the data to the subsequent board via the address setting completion signal line, and after the address setting is completed, the set address held in the address storage unit is compared with the address on the bus. is an address for accessing the own board, thereby eliminating the need for a hardware switch for address setting, and using a set of daisy. The configuration allows a unique address range to be set for each board simply by providing a chain connection signal line. This eliminates the troublesome manual address setting work and the human errors that come with it, improving reliability. , the hardware configuration can be simplified and any system can be easily constructed. (Example) An example of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a master board that is equipped with a CPU that controls the system and has a processing function that controls reading/writing of slave boards via a bus under the control of a built-in program. 2A, 2B. ...2N are slave boards (SBI, SB
2, -SBn), and each unique address range is set under the control of the master board 1. 3 is each of the above slave boards 2^, 2B. ...Address setting tF1 control circuit (ASC) provided in 2N, under the control of master board t, sets the address range of the own board using the address setting completion signal line by daisy chain connection, which will be described later. It has a transmission function that prompts the next board to set an address range, and a function that recognizes access to its own board (address specification) according to the set address. Its specific configuration is shown in Figure 2. will be described later with reference to. 4 is the master board 1 and slave board 2A. A bus (BU) that connects 2B,...2N
S), and here, in addition to the normal transfer lines for data, addresses, control signals, etc., there are address setting completion signal lines Ll, which are connected by a daisy chain connection and which sequentially notify the next board of the completion of address range setting. L2,...
Has Ln. FIG. 2 shows each slave board 2A. 2B,...2
3 is a block diagram showing the configuration of an address setting control circuit (ASC) 3 provided in N. FIG. Here, the address line (ADD) and data line (DATA) of bus 4 are each configured as 16 bits, and the address line (A
DI)) address on Al5~AO, data line (
DATA) is shown as D15 to DO. In FIG. 2, 31 is an address storage unit that stores addresses (A15 to AI) indicating a set address range on the bus of the own board, and an enable signal (EN1) obtained from an address decoding unit 33, which will be described later. and the write timing signal (νT) included in the control signal line of bus 4.
Accordingly, information indicating the set address (Al5 to AI) on the data line (DATA) is stored. Here, among the setting addresses AI5 to AI, Al5 is the most significant address bit, and AI is an address bit at a digit position determined by the setting address range. That is, as an example, 0 0 0 0 (H) to 0 O
Set the address range of F F (1) and send it to the slave board 2B from 0 1 0 0 (H) to O I F
(H), of the 16-bit addresses AI5 to AO, the upper 8 bits of the address AI. 5 to 88 are the above setting addresses (Ai -A
8”). 32 is the address line (
ADD) and the addresses (A15 to A1) set in the address storage section 3l are compared to determine whether the address output from the master board l is included in the address range set for the own board. This is an address comparison section. 33, when receiving an enable signal (ENO) from the address decode control unit 34, which will be described later, lower bits c A i of the address (Al5 to AO) on the address line (ADD) correspond to the address range of the own board. −
i to AO), that is, according to the above example, it is an address decoding unit that receives the lower 8 bits of the address (A7 to AO) and decodes the same address. Here, the lower 8 bits of the address (A7 to AO) are the 1 specific address (for example, 0 0 (H)), an enable signal (ENI) is output to the address storage section 31, and when it is a second specific address (for example, 0 2 (H)), the enable signal (ENI) is output to the address storage section 31. ), an enable signal (EN2) is output to the address setting completion storage section 35, which will be described later. 34 receives the determination output of the address comparison unit 32 and each signal of the address setting completion signal lines Ll and Li+1 on the input side and output side, and determines that the signal of the address setting completion signal line L1 on the input side is in the setting completion state (e.g. “1”), and when the signal on the output side address setting completion signal line Li+1 indicates the setting incomplete state (゜0“), and when the signal on the output side address setting completion signal line L1◆1 Setting completed state (“1
This is an address decode control section that outputs an enable signal (END) to the address decode section 33 when the address comparison section 32 outputs an address match judgment output when the address is shown as .degree.). 35 outputs data indicating completion of address setting on the data line (DATA) in accordance with the enable signal (EN 1) obtained from the address decoding unit 33 and the write timing signal (WT) included in the control signal line of the bus 4. This is the address setting completion storage section that stores 0 0 0 1 (}I)), and this least significant bit (
Do-LSB) signal (or stored data 0 0 0 1
(H) decode output) is output as an address setting completion signal to the address setting completion signal line Ll+1 on the output side, and sent to the next stage slave board. FIG. 3 shows the address setting completion signal line LX. L2.・
...This is a time chart showing the state of the address setting completion signal above. In the initial state, only the address setting completion signal line Ll is "1" indicating the address setting completion state,
When the address setting of the slave board (SBI) 2A is completed, the address setting completion signal line L2 becomes '1'', and it becomes possible to set the address of the slave board (SB2) 2B. The operation of an embodiment of the present invention will be explained with reference to the drawings.
Set the address range of
Let us take as an example the case of setting the address range of 1 F F (H). At this time, the address storage section 31 of the address setting control circuit 3 follows the enable signal (ENI-"1") obtained from the address decoding section 33 and the write timing signal (WT) included in the control signal line of the bus 4. Data indicating the upper 8 bits (Al5 to A8) of the address is stored. Further, the address comparison unit 32 compares the upper addresses A15 to A on the address line (ADD) of the bus 4.
8 and the set address in the address storage section 3l. Further, when the address decode unit 33 receives an enable signal (ENO-'1'') from the address decode control unit 34, it decodes the lower address (A7 to AO) on the address line (ADD) and outputs the same address ( A7~AO
) is 0 0 (H), an enable signal (ENI-“1”) is output to the address storage unit 3l, and 0 2 (
H), an enable signal (EN2-"1") is output to the address setting completion storage section 35. Further, the address decode control unit 34 outputs the judgment output of the address comparison unit 32 and the address setting completion signal lines Ll, LI+ on the input side and the output side.
1, the signal on the input side address setting completion signal line L1 is "1" indicating the setting completion state, and the signal on the output side address setting completion signal line LI+1 is "0" indicating the setting incomplete state. , and the signal on the address setting completion signal line L 1 + 1 on the output side indicates the setting completion state.
1", the address comparison section 32 outputs an enable signal (ENO-"1.degree.) to the address decoding section 33 each time there is an address match determination output. Further, the address setting completion storage unit 35 receives an enable signal (ENI-“1”) obtained from the address decoding unit 33.
) and the write timing signal (WT) included in the control signal line of bus 4, the data line (DA
Data indicating completion of address setting on TA) 0 0 0
1 (H) and its least significant bit (Do − '
1') is output as an address setting completion signal to the address setting completion signal line Ll+1 on the output side. Also, when the master board l is initialized, the address storage section 31
, and the address setting completion storage unit 35, it is necessary to use an address that is not used by any board after the initial setting is completed, and this address is used here as FFOO(}I) and FFOO(}I). F 0
2 (H). In the initial state, as shown in FIG. 3, among the address setting completion signal lines Ll, L2, . . . Ln included in the bus 4, only the address setting completion signal line Ll connects the master board 1 and the two slave boards. is "1", so that only the slave board 2A can set its own address range. That is, at this time, the signal on the address setting completion signal line Ll on the input side connected to the two slave boards is "1 degree", and the signal on the address setting completion signal line L2 on the output side is '0' indicating that the setting is not completed. From what is shown, slave board 2A
In the address setting #Ja1 circuit 3 provided in the address setting #Ja1 circuit 3, the address decode control unit 34 outputs an enable signal (ENO-“1”) to the address decode unit 33. In this state, first, from the master board l, write the address F F O O (
When data 0 0 0 0 (H) is sent on the data line (DATA), the address setting control circuit 3 of the two slave boards sets the address FFOO on the address line (ADD). (H) is decoded by the address decoding section 83, and an enable signal (ENI) is sent from the address decoding section 33 to the address storage section 3l.
-“1”) is sent. As a result, the data 0 0 0 0 (H) on the above data line (DATA) becomes
According to the write timing signal (WT), it is stored in the address storage section 31 as the set address of the own board. Next, from master board l, address line (ADD)
Address FFO 2 (H) is sent out on the top line, and data 0 0 0 1 (H) is sent on the data line (DATA).
When H) is sent out, in the address setting control circuit 3 of the slave board 2A, the address F F O 2 (H) on the address line (ADD) is decoded by the address decoding section 33, and the address is sent from the address decoding section 83. An enable signal (EN2-'
1") is sent out. This causes the above data line (
The data O 0 1 (H) on the data (DATA) is stored in the address setting completion storage unit 35 in accordance with the write timing signal (VT), and its lowest bit "1" is used as an address setting completion signal to indicate completion of address setting on the output side. It is output to signal line L2. In this way, the address setting control circuit 3 of the two slave boards has an address range of 0000 (H) to 0 0.
Setting address of own board as F F (H) 0 0
0 0 (H) is stored in the address storage unit 3l, and the address setting completion signal “1°” of the own board is stored in the address setting completion storage unit 35 and output to the address setting completion signal line L2, and As a result, the input side address setting completion signal line LL of the slave board 2B becomes "1", the output side address setting completion signal line L2 becomes "0°", and the slave board 2B address can be set. At this time, an enable signal (EN O) is sent from the address decode control section 34 to the address decode section 33 in the address setting control circuit 3 of the slave board 2B. In this state, the address line (A
DD) sends the address F F O O (H),
Data 0 1 0 0 on data line (DATA)
(H), the address storage unit 3 provided in the address setting control circuit 3 of the slave board 2B
The setting address 0 1 0 0 (H) of the own board is stored in l, and the address FFO 2 (H) is sent from the master board l onto the address line (ADD), and the address F FO 2 (H) is sent onto the data line (DATA). Data O O 0
1 (H), data 0 0 0 1 (H) indicating address setting completion is stored in the address setting completion storage section 35, and its lowest bit "1" is sent to the output side as an address setting completion signal. This signal is output to the address setting completion signal line L3.This causes the address setting control circuit 3 of the slave board 2B to set the address range from 0 1 0 0 (H) to O.
Setting address 0 of own board to be IFF (H)
1 0 0 (H) is stored in the address storage unit 31, and the address setting completion signal “]” of the own board is stored in the address setting completion storage unit 35, and is output to the address setting completion signal line L3, and Slobboard 2
Sent to C. In this way, the address setting completion signal lines Ll, L2 .
. . . to each slave board 2A, 2B via Ln.・
・Notifications prompting 2N to set addresses are sent one after another,
Each slave board that receives the notification sets a unique address range according to the designation of master board l. Address setting completion signal line LL of bus 4 as described above,
L2. ...By the address setting means using Ln,
A unique address range can be set for each board by simply providing one set of daisy chain connection signal lines. This eliminates the need for address setting hardware switches, eliminates troublesome manual address setting work and human errors associated with it, improves reliability, and simplifies the hardware configuration. Also, as long as it is compatible with the software of master board 1, slave boards 2A, 2B, . . .
The mounting position of ... can be selected arbitrarily, and any system can be easily constructed even when boards with different exclusive address ranges are mixed. In the embodiment described above, the address setting completion storage section 35 receives the enable signal (EN 1) obtained from the address decoding section 33 and the write timing signal (WT) included in the control signal line of the bus 4. Accordingly, data 0 0 0 1 (H) indicating completion of address setting on the data line (DATA) is stored, and the signal of its least significant bit (DO) (or stored data 0 0 0 1 (
Although the configuration is such that the decode output of H) is output as an address setting completion signal to the address setting completion signal line L1 on the output side, the present invention is not limited to this. ,0 0 0
1 (H), the address setting completion signal "1" is obtained and this signal is output to the address setting completion signal line L1 on the output side, or the address decoding unit 33 outputs the address setting completion signal according to the write timing signal (WT). A structure may also be used in which the output enable signal (EN2-"1") is latched. [Effects of the Invention] As detailed above, according to the bus address setting method of the present invention, a master board and a plurality of slave boards are connected to each other in a daisy chain on a bus that interconnects each other, and the address setting method is An address setting completion signal line is provided to sequentially transmit completion to the next board, and each slave board retains the set address on the bus when the input/output signal relationship of the address setting completion signal line is in a specific state. an address storage means; an address setting completion storage unit that holds a status signal indicating that the address setting to the address storage unit has been completed and sends the status signal to a subsequent board via the address setting completion signal line; an address determination unit that compares the set address held in the address storage unit with the address on the bus after completion of address setting and determines whether or not the address on the bus is an address for accessing the own board; This structure eliminates the need for hardware switches for address settings and allows each board to be set with a unique address range by simply providing a set of daisy chain connection signal lines. Reliability can be improved by eliminating the troublesome address setting work and accompanying human errors, and the hardware configuration can be simplified, making it possible to easily construct any system.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a block diagram showing the configuration of the address setting control circuit (ASC) in the above embodiment, and Fig. 3 is a block diagram showing the configuration of the address setting control circuit (ASC) in the above embodiment. 5 is a time chart showing the state of an address setting completion signal on a setting completion signal line. 1...Master board, 2A, 2B,...2N...
・Slave board (SBl, SB2...SBn)
, 3...address setting control circuit (ASC), 4.
... bus CBUS), 31 ... address storage section, 32
. . . Address comparison section, 33. Address decoding section, 34. Address decoding control section, 35. Address setting completion storage section, Ll, L2. ...Ln4...
・Address setting completion signal line, wT...Write timing signal, ADD...Address line, DATA...
Data line, EN O, EN l. EN2...
・Enable signal.

Claims (1)

[Claims] A system having an address setting function in which a master board and a plurality of slave boards are connected via a common bus, and the address of each slave board is set under the control of the master board. Each board has an address setting completion signal line that is connected in a daisy chain and sequentially transmits address setting completion to the next board, and each slave board has a specific input/output signal relationship of the address setting completion signal line. address storage means for holding the set address on the bus when in the state, and a state signal indicating that the address setting to the address storage means has been completed, and transmitting the same state signal via the address setting completion signal line. The address setting completion storage unit that sends out to the subsequent board compares the set address held in the address storage unit after the address setting is completed with the address on the bus, and determines whether the address on the bus is the one for accessing the own board. 1. A bus address setting method, comprising: an address determination section that determines whether or not the address is an address.