JPH0351933A - Memory addressing system - Google Patents

Abstract

PURPOSE:To attain the dynamic use of the given full address width and to effectively use all entries by securing an exclusive OR among the bits of all factors in the ascending order or in the reversed order. CONSTITUTION:In an addressing state of an address conversion index buffer mechanism TLB 1, the 8 bits (12th - 19th bits) of a virtual space identifier STO register 3 are inverted vertically by a bit train inverting circuit 41 of an address generating circuit 4. Then an exclusive OR circuit 42 secures an exclusive OR among 8 bits of a page index, i.e., the 12th - 19th bits of a logical address register 2. This result of the exclusive OR is used as the reference address of the TLB 1. As a result, the number of entries are dynamically assigned in response to the fluctuation of each factor to ensure the effective use of all entries.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory addressing system for information processing equipment, and in particular to a memory addressing system suitable for an address conversion index buffer mechanism in an information processing equipment that employs a multiple virtual space system. Concerning addressing schemes.

[Conventional technology]

Generally, in information processing devices using virtual memory, this is used to speed up address translation. It has an address translation index buffer that holds a correspondence table between virtual addresses and real addresses that have been translated in the past, but when using multiple virtual spaces, virtual space identifiers are considered in addition to logical addresses when using a single virtual space. There is a need. When virtual space identifiers are not considered in the case of multiple virtual spaces, addresses in the address index buffer are generated using logical addresses. In this case, when dealing with multiple virtual spaces, entries will be overwritten in the case of logical address conflicts. Logical addresses tend to be allocated starting from the lowest address, and all programs have this tendency. In other words, since each program attempts to register an entry at a lower address in the address translation index buffer mechanism, in the case of multiple virtual spaces, each time a program switches tasks, the address of the entry used by the previous task is registered. conflicts, and an entry for a new task is re-registered. As a result, when the previous task is dispatched again, the previously registered contents have been rewritten by another task, and the address translation must be performed again and registered in the address translation index buffer mechanism, which is not efficient. There is a problem.

Another problem in this case is that the multiple programs you are trying to process are all relatively small programs that only need entries on the low address side of the address translation index buffer, and the entries on the high address side are This means that it is not used effectively at all.

Conventionally, in this type of address translation index buffer mechanism, when considering two address factors, the virtual space identifier in multiple virtual spaces and the logical address in a single virtual space, for example, Japanese Patent Laid-Open No. 56 As described in Publication No. 19573, a flag indicating which spatial mode is used is prepared, and an address conversion index M! This has been dealt with by separating the address of the conflict mechanism into a field for a virtual space identifier and a field for a logical address when multiple virtual spaces are used.

[Problem to be solved by the invention]

The first problem with the above conventional technology is that when multiple virtual spaces are used, all entries in the address translation index buffer mechanism are statically allocated and the number of entries for each virtual space is always fixed. This means that entries cannot be used flexibly between a virtual space that uses many entries and a virtual space that uses few entries. In other words, in a virtual space range that requires many entries, entries are rewritten many times, and in a virtual space range that uses few entries, there are unused entries.
The second problem is that the address generation method is selected by setting a flag for single virtual space time and multi-virtual space time. The same problem as in the prior art described above also exists in the addressing of the access register conversion index buffer mechanism. In this case, Dispatchable in the second control register
Unit C: control Table Orig
in (hereinafter abbreviated as DUCTO) or Primary ASN S econd in the fifth control register
Table EntryOrigin (hereinafter P
ASTEO) is the first change factor, and Acea
ss List Entry Token (hereinafter referred to as ALE
A ceess List Ent in (abbreviated as T)
ryNumber (hereinafter abbreviated as ALEN) is the second change factor. In other words, in one program, many ′
! I! If you want to handle many programs at the same time without using too much time, use the first change factor, DUCTO or PASTE.
O mainly changes, and if this is reflected in the address of the access register conversion index buffer mechanism, entries can be used efficiently. On the other hand, if only a small number of programs are handled, but each program uses a large amount of space, the second change factor, ALEN, will mainly change, and this will be reflected in the address of the access register conversion index buffer mechanism. This allows entries to be used efficiently.

In order to consider the above two change factors as the addressing method of this access register conversion index buffer mechanism,
If the number of entries for each change factor is fixedly allocated, problems with the address translation index buffer mechanism will still exist.

An object of the present invention is to dynamically allocate the number of entries in response to fluctuations in various factors in an address translation index buffer mechanism, an access register translation index buffer mechanism, etc., thereby making it possible to use all entries effectively. Another object of the present invention is to provide a memory addressing method that does not require a flag indicating which change factor is dominant.

[Means to solve the problem]

In order to achieve the above-mentioned object, the present invention provides a method for addressing a memory such as an address translation index buffer mechanism or an access translation mechanism using two or more variation factors as an address, when the variation factors that are dominant in address determination are The exclusive OR is performed on some or all of the bits in the ascending order of the bits, or in reverse order, and the entire address width of the memory is addressed using the exclusive OR result as an address.

Also, even in the case of l address factors as a whole, new multiple address factors are generated as a result of dividing the factor into multiple partial fields and considering each partial field as a new single address factor. , some or all of the factors that are dominant in determining the address are subjected to an exclusive OR with the ascending order of the bits unchanged or reversed, and the memory is addressed using the exclusive OR result as an address.

[For production]

Now, the first change factor called A (for example, logical address)
and a second change factor B (e.g. virtual space identifier)
Suppose there is. For example, when generating addresses for 256 entries, the change factor A is A(
01) to A(19) should be considered as an address, and the change factor B has bits from B(01) to B(19), but B(12) to B(19) should be considered as an address. Assume that

As an example, by reversing the above B(12) to B(19), i.e., B(12) to the least significant bit, B(19)
is set as the most significant bit, and exclusive OR is performed for each bit of A(12) to A(19) to obtain the address of 256 entries. As a result, if the change factor A changes dominantly and the change factor B hardly changes, the lower bits of the generated address are switched by the change factor A. This allows the entire available address width to be used effectively. On the other hand, if change factor A hardly changes but change factor B changes dominantly, the upper bits of the generated address are switched by change factor B. In this case as well, all available address widths can be used effectively. [Example] Hereinafter, an example of the present invention will be explained in detail with reference to the drawings. FIG. 1 is a block diagram of a first embodiment of the present invention, showing the case where the present invention is applied to addressing of an address translation index buffer mechanism. In FIG. 1, 1 is an address translation lookaside buffer (hereinafter referred to as TLB);
Here, the TLB is assumed to have a 256-entry configuration.
Each entry in I consists of a valid bit V, a part of a logical address, a virtual space identifier STO, a part R of a real address, and a parity P. 2 is the logical address L of the memory request
A logical address register 3 stores A, and a virtual space identifier register (hereinafter referred to as STO register) stores a virtual space identifier ST○ currently being executed. 4 is an address control circuit according to the present invention, and a bit string inversion circuit 41
and an exclusive OR circuit 42. 5 and 6 are comparison circuits,
7 and 8 are AND circuits. The operation of FIG. 1 is as follows. Of the logical address LA in the logical address register 2, the 01st bit to the 11th bit is the segment index, the 12th bit to the 19th bit is the page index, and the 2nd bit is the segment index.
The 0th bit to the 31st bit is a byte index. Here, within one virtual space, the logical address L
A is generally used from the lowest level (from address O),
When dealing with multiple virtual spaces, ST○ is also set from the lower level (ST○=0
) is used. Target TLB1 is 256
Since it is an entry, it is addressed using an 8-bit address. Therefore, among the bits used in dynamic address translation, the bits that change the most are used for TLBI address generation, and the logical address LA is the lower 68 bits (12th to 19th bits) of the page index. , STO is also the lower 8 bits (↓2nd bit to lth bit)
9 bits).

During TLBI addressing, the 8 bits from the 12th bit to the 19th bit of the ST○ register 3 are vertically inverted by the bit string inverting circuit 41 of the address control circuit 4. That is, the least significant bit, the 19th bit, is replaced with the most significant bit, and the most significant bit, the 12th bit, is replaced with the least significant bit. Replace the other bits in the same way. After performing this processing, an exclusive OR circuit 42 performs an exclusive OR with the 8 bits of the page index, which are the 12th bit to the 9th bit of the logical address register 2. This exclusive OR result is used as the reference address of TLB1. Among the entries obtained by addressing TLB1, the L field is compared with bits 01 to 19 of logical address register 2 in comparison circuit 5, and the STO field is compared with all bits of STO register 3 in comparison circuit 6. Then, the AND circuit 7 performs the above 2
The two comparison results are ANDed with the valid bit ■. As a result, when the valid bit V is 1 and the two match comparisons are both established, the AND circuit 8 is opened. Part R of the real address of TLB1 is read. In addition, if either of the two matching comparisons is not satisfied, TLBL
In the L field and STO field of the corresponding entry,
Bits 01 to 19 of logical address register 2. All bits of STO register 3 are newly registered.

First, consider a long program. In this case, the logical address LA and virtual space identifier ST
When performing an exclusive OR with O, since ST○ always remains unchanged, a change in LA appears as a result. In other words, TLBI addressing is determined by LA, and all changes in the 12th to 19th bits of logical address register 2 can be used as TLB 1 addresses, so all 256 entries of TLB 1 can be used as ST in this case. This means that it is specified and used by an arbitrary logical address in one virtual space indicated by a circle.

Next, consider eight relatively small programs as the second case. In this case, in order to identify the eight virtual spaces, the lower three bits of the virtual space identifier STO in the STO register 3 are changed. In the address control circuit 4, the 12th to 19th bits of the ST○ register 3
Since the bit string of the lower 8 bits is inverted, as a result of exclusive ORing with the logical address LA of logical address register 2, the address of TLB 1 that changes when ST○ changes is only the upper 3 bits. be. Therefore, of the 8 bits of the address for addressing the 256 entries of the TLBI, the lower 5 bits can be used for changing the actual LA. Therefore, if 32 entries in TLB1 are sufficient for each program, LA
Since the bits that change when taking the exclusive OR of and STO do not overlap, 32
TLBI can be used effectively up to entry. As a third case, consider a case where one of the eight programs in the second case is a long program, and 312 entries in the TLBI are insufficient. If the logical address of this long program is not enough for the 32 pages of 5 bits from the lower page index and reaches the 6th bit or more from the lower page index, the exclusive OR result with ST○ will be the lower STO where only the upper 3 bits change. This will cause overlap with the bit. Therefore, for example, if you use only the 6th bit from the bottom of the page index and 64 pages are sufficient, you can use the T used by the other 7 programs.
The entry used by one of the LB entries will be rewritten. However, even in this case, the TLB entries of the other six programs remain without being rewritten and can be used effectively. In addition, if the address generation circuit 4 according to the present invention is not used, the TLB entries of all programs are originally addressed only from logical addresses, and there is a possibility that the entries are rewritten each time the task is switched. It can be said that the fact that the TLB entries for the programs remain contributes to improving the performance of the system. Furthermore, in the long program, when 64 pages were insufficient for addressing the 6th bit from the bottom and 128 pages were required, including the 7th bit, this was used in 3 of the other 7 programs. Although the TLB entry is rewritten, the TLB entries for the other four programs remain valid.

FIG. 2 is a block diagram of a second embodiment of the present invention, showing the case where the present invention is applied to addressing of an access register conversion index buffer mechanism.

In FIG. 2, the functions 4 to 8 are the same as in FIG.

9 is an access register conversion index buffer mechanism (hereinafter referred to as LAB).
), and has a 256-entry configuration similar to TLB1 in FIG.

Each entry in ALB9 consists of a valid bit ■, an ALFT field, an ALDSO field, an STO field, and a parity P. 10 is ALET register, king 1
12 is DUCT○ in the second control register (CR2), and PASTE0.13 is the ALDSO register in the fifth control register (CR5).

ALET register 1 of the access register, which is the same number as the general-purpose register number selected as the pace register
ALET is stored in 0.

In this ALET, P is a Privata bit, and when this bit is O, DUCTOII is set to
Select PASTE ○ work 2 at the time of . AL during ALET
EN is the entry number in the space management table. The address for STO access is stored in the entry of this space management table. In the access register conversion mode, access register conversion is performed using this ALET, and the virtual space identifier STO is obtained. AL
B9 stores the result of the above conversion. On DUCTOl, PASTEO is a means of accessing the top of the space management table given to each task.
I2 stores means for accessing the top of the space management table given to each program.

The operation shown in FIG. 2 is as follows. ALET in the access register is stored in ALET register 10, and this ALET
DUCT○11 or PASTEOR12 is selected by the Privata bit, which is the seventh bit of ET. The result of this selection is stored in the ALDSO register 13.

The contents of both ALEN and ALDSO change starting from the lower bit side. Therefore, when using ALB9 with 256 entries,
The 8 bits from the least significant bit are used for addressing ALB9. The 18th to 25th bits of ALDS○ undergo bit string inversion in the bit string inversion circuit 41 in the address generation circuit 4. For example, the 18th bit, which is the most significant bit, becomes the least significant bit, and the least significant bit becomes the least significant bit. The 25th bit becomes the most significant bit. This ALD
The data obtained by inverting the bit string of SO and the data of ALEN are subjected to an exclusive OR of each bit in an exclusive OR circuit 42, and the result is used as a reference address for ALB9. Further comparisons, A
The ND processing is basically the same as in the first embodiment.

If a program or task uses many virtual machines, the contents or bits of ALEN change. For example, 256′! I! For programs or tasks that use
Address all 256 entries of LB9. Furthermore, if there are many programs or tasks that only use time, the contents of ALDSO, that is, the bits, change. For example, when 256 programs or tasks are processed, the lower 8 bits of ALDSO are used,
Address all 256 entries of ALB9.

In the address generation circuit 4, the lower 8 bits of ALDSO are inverted and exclusive ORed with the 8 bits of ALEN over the entire bit width, so in the above two cases, the AL
256 entries of B9 are available. Furthermore, a mixed case where a plurality of programs or tasks are processed and each uses a large number of spaces or a small number of spaces is also considered so that ALB entries can be used effectively. In other words, as the number of programs or tasks to be processed increases, the entry address starts to change from the upper bits (as the number of programs or tasks increases, the count is increased from the lower bits of ALDSO, but the information in ALDS○ changes from the address generation (The bit string is inverted in circuit 4). Furthermore, as the number of virtual machines used by each program or task increases, the entry address begins to change starting from the lower bits. Therefore, ALE on a somewhat small scale
Even if there are multiple tasks or programs that require a small number of entries (!number of entries) indicated by N, entries for other tasks or programs will not be rewritten. Also,
Even if some of the tasks or programs use a lot of space, it does not overwrite all the entries for other tasks or programs that are being processed at the same time; All you have to do is rewrite the entry. Therefore, the remaining entries that have not been rewritten can be effectively used by other tasks or programs. FIG. 3 is a block diagram of a third embodiment of the present invention, showing a case where the present invention is applied to addressing of a buffer memory that stores part of data in the main memory.

In FIG. 3, 2 is an address register and 14 is a buffer memory. It is assumed that the buffer memory 14 manages 32 bytes as 1 block. That is, bits 24 to 28 of address register 2 are intra-block addresses,
Indicates whether it is the {th byte out of 32 bytes. Also, bits 01 to 23 are block addresses, and the address stored in address register 2 is, when viewed in block units,
Indicates whether it corresponds to the detective block. There is a limit to the size of the buffer memory 14, and bit 01 of address register 2
It is not possible to store all 223 entries indicated by -23. In FIG. 3, the buffer memory 14 stores 256 blocks, that is, 256 entries×32 bytes=8192 bytes. This battle memory 1
By using bits 16 to 23 of the address register 2 when addressing the 4th block, the 1st to 256th blocks can be stored in the buffer memory 4. However, by addressing only by bits 16 to 23 of address register 2, it is not possible to store blocks 1 to 64 and blocks 257 to 320 at the same time in buffer memory 14. This case corresponds to the case where an address space as shown in FIG. 4 is used.

In such a case, as shown in FIG. Used for the upper two bits of the address during addressing. As a result, the 1st to 64th blocks start from the address "oooooooo" in the buffer memory 14, and the 257th to 320th blocks start from the address "0 1 0 0 0".
0 0''. Moreover, the 1st block to the 256th block can be stored in the buffer memory l4 at the same time.
A conventional storage method is also possible. In this case, bits 4 to 15 and bits 16 to 17 of the address register are defined as each factor of the plurality of factors.

〔Effect of the invention〕

As explained above, according to the present invention, when addressing an address or access register conversion index buffer mechanism or buffer storage, etc., when there are multiple factors,
Rather than statically separating and using the address bits for each factor, the entire given address width can be operated by taking exclusive OR of the bits of all the factors to be considered, either in ascending order or in reverse order. can be used for,
It becomes possible to use all entries to the right.

Furthermore, even when only one of the multiple factors that determine an address is affected, addresses can be used and created effectively.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a first embodiment in which the present invention is applied to addressing of an address translation index buffer mechanism, and FIG. 2 is a block diagram of a second embodiment in which the present invention is applied to addressing of an access register translation index buffer mechanism. The block diagram, FIG.
FIG. 2 is a block diagram of an embodiment of the invention. l...TLB memory, 2...address register, 3...virtual space identifier register, 4...address generation circuit, 5, 6...comparison circuit,
7, 8...AND circuit, 9...ALB memory,
10...ALET register, 11...DUCT
O register, 12...PASTEO register, 1
3...ALDSO register, 14...Buffer storage, 41...Bit string inversion circuit, 42...Exclusive OR circuit. Figure 3 Figure 4

Claims (3)

[Claims] (1) In a method of addressing memory using two or more change factors as addresses, find the mutual exclusive OR of some or all of the two or more change factors, and calculate the exclusive OR result. A memory addressing method characterized by addressing the entire address width of the memory as an address. (2) In a method in which the factor is one address factor as a whole, but the factor is divided into a plurality of partial fields, and each partial field is used as a new single address factor to address the memory, the divided A mutual exclusive OR of some or all of the two or more partial fields obtained is calculated, and the exclusive OR result is used as an address to address the entire address width of the memory. A memory addressing method that uses (3) At least one address factor or part or all of its partial field is exclusive ORed with another address factor or part or all of its partial field by inverting its upper and lower parts. The memory addressing method according to claim 1 or 2, characterized in that: