JPH0351895A - Scroll display device for still image - Google Patents

Abstract

PURPOSE:To make a smooth scroll display by delaying bit-series image data which are outputted from a shift register in picture element units of a monitor when the scroll display is made with a preset signal and a load signal which are delayed by an integral multiple of a clock. CONSTITUTION:A horizontal address register 16 specifies a horizontal address of an image memory 14 and an initial value register 20 sets an initial value in the horizontal address counter 16. A preset means 24 supplies to the horizon tal counter 16 with the preset signal which is delayed by an integral multiple of the clock at intervals of a horizontal line on the monitor 34 and a load means 30 supplies a shift register 32 with the load signal which is delayed by an integral multiple of the clock. The bit-series image data outputted from the shift register 32 are delayed in picture element units. Consequently, smooth scroll display can be performed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a scroll display device for still images, and in particular reads image data from an image memory in bit parallel and converts the image data into bit serial data using a shift register. The present invention relates to a still image scrolling display device that displays a still image on a monitor.

[Prior art]

Although high-definition images can reproduce high-definition images,
One screen requires approximately 6MB of data. Therefore, in order to perform data processing at high speed in a high-definition image file device, for example, four pixels worth of image data read out from an optical disk device are stored in one address of a display memory, and shifted from the display memory in bit parallel. The data is loaded into a register, converted into bit-serial data by the shift register, and provided to the monitor.

On the other hand, the scroll display is, for example,
As disclosed in Japanese Patent No. 88, this is done by changing the initial address value of the image memory.

[Problems to be solved by the invention] In conventional scroll display devices, the horizontal direction (
It was not possible to display smooth scrolling in the horizontal direction. In other words, since image data is read from the image memory to the shift register in parallel bits, even if the initial address is changed one by one, the display position on the monitor screen can only be changed by the number of stages (N) of the shift register. Therefore, it is only possible to shift by N increments on the scanning line, and smooth scrolling cannot be performed.

Therefore, a main object of the present invention is to provide a still image scrolling display device that can perform smooth scrolling display even when image data is read out bit-parallel from an image memory.

(Means for Solving the Problems) Simply put, the present invention provides a still image that is equipped with a shift register for loading bit-parallel image data read out from an image memory according to a clock and then converting it into bit-serial data. In a scroll display device, a horizontal address counter is used to specify the horizontal address of the image memory, an initial value register is used to set an initial value to the horizontal address counter, and an integer multiple of the clock is stored in the horizontal counter for each horizontal line of the monitor. A scroll display device for still images, characterized by comprising a preset means for giving a delayed preset signal, and a load means for giving a load signal delayed by an integral multiple of a clock to a shift register.

[Effect]

The horizontal address of the image memory is specified by a horizontal address counter. The initial value of the horizontal address counter is
Set by the initial register, the horizontal address counter is incremented according to the clock. The initial value of the horizontal address counter is preset loaded by a preset signal applied to each horizontal line, and the preset signal is delayed by an integral multiple of the read clock by the presetting means and then applied to the horizontal address counter. Therefore, the horizontal address data applied from the horizontal address counter to the image memory is delayed by the clock, that is, by the pixel of the monitor screen, in addition to its initial value.

At the same time, the shift register is given a load signal that is delayed by an integral multiple of the Cronk preset signal for each horizontal line from the load means. Therefore, bit-serial image data output from the shift register is delayed pixel by pixel.

〔Effect of the invention〕

According to this invention, when scroll display is performed using the preset signal and the load signal delayed by an integral multiple of the clock, the bit-serial image data output from the shift register can be delayed in units of pixels of the monitor.
Smooth scrolling can be performed in the horizontal direction (horizontal line direction) of the screen.

The above objects, other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

〔Example〕

FIG. 1 is a block diagram showing one embodiment of the present invention.

The scroll display device 10 of this embodiment includes a microcomputer 12, and the microcomputer 12 includes a C
It includes a PU, ROM, RAM, etc., and the RAM is provided with various flag areas and counter areas necessary for control, and also temporarily stores data.

Image data read from, for example, an optical disk device (not shown) is written into the image memory 14 so that four pixels are included in one address. Its write or read address is specified by horizontal address counter I6 and vertical address counter 18. That is, CR
The horizontal address of T34 is specified by the horizontal address counter 20, and the vertical address is specified by the vertical address counter 22. The initial values of horizontal address counter 16 and vertical address counter 18 are set by initial value registers 20 and 22, respectively.

Initial value data is given to initial value registers 20 and 22 from microcomputer 12, respectively. Therefore, once initial values are set in initial value registers 20 and 22, horizontal address counter 16 and vertical address counter 18 are incremented in response to a clock signal from microcomputer l2. Note that the horizontal address counter l6 and the vertical address counter 18 are loaded with horizontal addresses and vertical addresses in an initial state in which no preset signals from the delay circuit 26 and vertical preset signal generation circuit 28, which will be described later, are applied from the microcomputer l2. .

When the horizontal preset signal generation circuit 24 detects the horizontal synchronization signal applied to the monitor 34, it provides the horizontal preset signal to the delay circuit 26. The delay circuit 26 outputs a preset signal for resetting the horizontal address counter 16 to an initial value. That is, in response to the completion of horizontal line scanning, a preset signal delayed by an integral number N times the readout clock of the shift register 32, which will be described later, is output based on a delay command signal from the microcomputer 12. In addition, regarding the integer N, in this example, N=
1 to 4, and any value among them is set by the microcomputer.

As a result, the horizontal address counter 16 outputs a horizontal address for each horizontal line with a further delay of N clocks from the initial value set by the initial value register 20.

In the vertical direction, when the vertical preset signal generation circuit 28 detects the vertical synchronization signal given to the monitor 34, that is, when the end of one frame is detected, a preset signal is generated to reset the initial value of the vertical address. given to vertical address counter I8. Note that the delay command signal of the microcomputer l2 supplied to the delay circuit 26 is also supplied to the other delay circuit 30. The delay circuit 30 outputs a load signal for loading the bit-parallel image data from the image memory 14 into the shift register 32 after being delayed by the same integer N times the shift clock. Then, the shift register 32 converts the image data loaded in bit parallel into bit serial image data in response to the shift clock.
Give to. In operation, when the display is not scrolled horizontally pixel by pixel on the monitor, that is, the CRT 34, the preset signal and load signal are not delayed as shown in FIG. Therefore, scrolling, for example, every four pixels can be performed as in the conventional case.

FIG. 3 is a timing diagram showing the relationship between a preset signal, a load signal, bit parallel data, and bit serial data with respect to a clock signal when horizontal scroll display is performed with a delay of initial value (in units of 4 pixels) + 1 pixel. Pixel (
In order to display scrolling in units of dots, the preset signal from the delay circuit 26 is delayed by one clock signal as shown by the broken line. Therefore, image memory l4
The address specification timing is also delayed by one clock signal compared to the case in Figure 2. And the same? Since the load signal outputted to the shift register 32 by the delay circuit 30 is also delayed by one clock signal, the load timing of the shift register 32 is also delayed by one clock signal compared to the case of FIG. Therefore, the data pits 1, 2, 3, and 4 of the image data output from the shift register 32 in FIG. 2 for each shift clock are delayed by one clock signal. In this way, CRT34
Image data delayed by one clock signal is given to , and horizontal scrolling display delayed by the initial value + 1 pixel is performed.

In the subsequent frame, the microcomputer l2 controls the delay circuits 26 and 30 to transmit the preset signal and the load signal by two clock signals. By sequentially delaying by 3 and 4 pixels, right scrolling is performed pixel by pixel. However, when N=4 is exceeded, the horizontal initial address is changed.

Also, when scrolling to the left, N=
4.3, 2.1 and so on.

The vertical scroll display is performed by shifting the vertical initial address by an appropriate number of horizontal lines, as in conventional scroll display devices.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of this invention. FIG. 2 is a timing diagram showing the relationship between each signal and data when performing normal (or scrolling every 4 pixels) display in the embodiment shown in FIG. FIG. 3 is a timing diagram showing the relationship between each signal and data when performing scroll display delayed by l pixels. In the figure, 12 is a microcomputer, l4 is an image memory, l6 is a horizontal address counter, 20 and 22
3 is an initial value register; 24 and 28 are horizontal and vertical recent signal generation circuits; 26 and 30 are delay circuits;
2 is a shift register, and 34 is a CRT. Figure 1

Claims (1)

[Scope of Claims] A still image scrolling display device comprising a shift register for loading bit-parallel image data read out from an image memory in accordance with a clock and converting it into bit-serial data, wherein a horizontal address of the image memory is provided. a horizontal address counter for specifying a horizontal address counter, an initial value register for setting an initial value in the horizontal address counter, and a presetting means for providing a preset signal delayed by an integral multiple of the clock to the horizontal counter for each horizontal line of the monitor. , and loading means for providing a load signal delayed by the same integral multiple of the clock to the shift register.