JPH0350848A - Hard macro cell - Google Patents

Abstract

PURPOSE:To effectively execute wiring and to sharply relax a restriction on a layout of a large-scale integrated circuit device by a method wherein a wiring region used for a wiring between other macro cells is formed inside a hard macro cell. CONSTITUTION:The following are laid out in advance on a semiconductor chip 1: a plurality of hard macro cells 2a, 2b to 2e; a hard macro cell 4 having a wiring region 3 used for wirings between other macro cells inside a cell. Parts between them are connected mutually by using wiring patterns 5 to constitute a large-scale integrated circuit device. The wiring patterns 5 which connect the hard macro cell 2a and the hard macro cells 2d, 2e mutually are interconnected and formed not only in a vacant region between the hard macro cells but also via the wiring region 3 on the hard macro cell 4. Thereby, a restriction on a layout can be relaxed sharply; a design itself of the wiring patterns can be made easy; a simulation of an overall circuit function can be executed simply and efficiently.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a hard macro cell suitable for being incorporated on a semiconductor chip to realize a large-scale integrated circuit device.

(Prior Art) In recent years, with advances in LSI microfabrication technology, the scale and performance of circuits that can be integrated on one semiconductor chip have improved dramatically. With the development of ASIC technology against this background, various custom LSIs have been manufactured based on user specifications.

One of the techniques for manufacturing such a custom LSI is a technique for realizing a large-scale integrated circuit device according to user specifications by combining macrocells that have been prepared in a library in advance. This technology embeds multiple macrocells on a semiconductor chip according to circuit specifications, interconnects these macrocells, simulates the overall circuit function, and develops a large-scale integrated circuit device according to user specifications. It is something.

However, the macrocells that are incorporated on such semiconductor chips and used to realize large-scale integrated circuit devices include compact hard macrocells whose mask pattern shape is fixed and whose performance is guaranteed; There is a soft macro cell that is highly flexible and can be used in various semiconductor processes. However, soft macro cells tend to have larger cell dimensions than hard macro cells, and have the problem that their performance varies depending on the implementation means (changes in wiring patterns, etc.). For this reason, when designing and developing large-scale integrated circuit devices, each time the wiring pattern between multiple soft macro cells is changed, the performance (characteristics)
There is a problem in that it is not possible to easily design and develop a large-scale integrated circuit device including simulation of the circuit function.

On the other hand, the implementation structure of the above-mentioned hard macrocell is defined in terms of hardware, so its performance (characteristics)
is known in advance, and even if the wiring pattern between hard macro cells is changed, its performance can be easily simulated. However, since the hardware implementation structure is fixed, there is a problem in that there is very little flexibility in changing the wiring pattern. Specifically, since the wiring area on the semiconductor chip is limited,
A large restriction is placed on the layout of the plurality of hard macrocells, and as a result, wiring between the plurality of hard macrocells may not be possible.

(Problems to be Solved by the Invention) Conventionally, when a large-scale integrated circuit device is realized by incorporating a plurality of hard macro cells on a semiconductor chip, the wiring area between the hard macro cells is severely limited. This placed great restrictions on the layout structure of a plurality of hard macro cells, and in some cases, it became impossible to wire between the hard macro cells.

The present invention has been developed with these circumstances in mind, and its purpose is to enable easy wiring between hard macro cells without being subject to major restrictions on the layout of a plurality of hard macro cells. An object of the present invention is to provide a hard macro cell suitable for designing and developing a large-scale integrated circuit device.

[Structure of the Invention (Means for Solving the Problem) The hard macrocell according to the present invention is characterized in that a wiring area for wiring between other macrocells is provided in advance inside the macrocell. It is something.

(Function) According to the present invention, a wiring area is provided inside the hard macrocell for wiring between the macrocells, so that a plurality of hard macrocells of this kind can be incorporated on a semiconductor chip. Even when realizing a large-scale macrocell, it is possible to effectively perform wiring between other macrocells by using the wiring area inside the cell.

In addition, since wiring between macrocells can be done relatively freely in this way, constraints on the layout of multiple hard macrocells on a semiconductor chip can be significantly relaxed, and large-scale integrated circuits Equipment design/
It becomes possible to carry out development easily and efficiently.

(Embodiment) Hereinafter, a Lehart macrocell according to an embodiment of the present invention will be described with reference to the drawings.

Figure 1 shows the design and design using the hard macrocell according to the example.
1 is a diagram showing an example of a layout configuration of a large-scale integrated circuit device to be developed; FIG. In FIG. 1, 1 is a semiconductor chip, and a plurality of hard macro cells 2 are provided on this semiconductor chip.
A, 2b, to 2e, and a hard macro cell 4 having a wiring region 3 inside the cell are laid out. And these macro cells 2a.

A large-scale integrated circuit device is realized by interconnecting the wiring patterns 2b, 2e, and 3 using the wiring pattern 5.

Therefore, each of the hard macro cells 2a, 2b, to 2e,
4 each has a predetermined circuit function, and is used by being incorporated on the semiconductor chip l according to the circuit specifications. The feature of this large-scale integrated circuit device is that a wiring area 3 is provided in advance in the cell F'1 portion of the hard macrocell 4, which is used for wiring between other macrocells. , node macrocells 2a, 2b, ~2e
A part of the wiring pattern 5 between them is formed through the wiring area 3.

Specifically, the wiring pattern 5 that interconnects the hard macrocell 2a and the hard macrocells 2d and 2e is formed not only in the free space between the hard macrocells but also through the wiring area 4 on the /'% -domain macrocell 3. The point is that it is.

Thus, according to the large-scale integrated circuit device designed and developed using the hard macro cell 4 having the wiring area 3 inside the cell, the cells on the hard macro cell 4 are only in the empty 6n area between the /%-domain macro cells. Internal wiring area 3
By effectively utilizing the
Since it becomes possible to arrange and form the wiring pattern 5 between 2e and 4, each node macrocell 2a, 2b, to 2e
, 4 can be significantly relaxed, and the wiring batten design itself can be easily performed.

Furthermore, if such a hard macro cell 4 having a wiring area 3 inside the cell is used, each hard macro cell 2a, 2b,
~2e, Since the performance (characteristics) of 4 is known in advance,
Since its overall performance can be easily determined, its overall circuit function can be easily and efficiently simulated. In other words, you can create a large-scale integrated circuit that meets desired circuit specifications by changing the layout of multiple hard macrocells and modifying/changing wiring patterns without having to recalculate the circuit performance each time, as is the case when using soft macrocells. It becomes possible to efficiently develop and design devices.

Note that the present invention is not limited to the embodiments described above. For example, the size, shape, and formation position of the wiring area provided inside the hard macrocell.

The number etc. may be determined according to the macro cell specifications. Furthermore, the means for forming the wiring region is not particularly limited, and may be such that the hard macrocell itself has a multilayered semiconductor structure and the wiring region is formed in the uppermost layer thereof. In short, the present invention can be implemented with various modifications without departing from the gist thereof.

[Effects of the Invention] As explained above, according to the present invention, a wiring area is provided inside a hard cell that is covered by wiring between other macro cells, so that it is possible to connect various hard macro cells whose performance is known. It becomes possible to easily develop and design a large-scale integrated circuit device with desired circuit specifications by using the above-mentioned method, setting the layout of these components relatively freely, and easily wiring between them. Moreover, it has great practical effects, such as being able to easily simulate its functions.

[Brief explanation of drawings]

FIG. 1 shows one embodiment of the present invention, a layerer h of a large-scale integrated circuit device realized using an advanced /X-domain macro cell.
It is a figure showing an example of RJ construction. 1... Semiconductor chip, 2a, 2b, ~2e.../X
- Domain macro cell, 3... Wiring area formed inside the hard cell, 4... Node macro cell having a wiring area inside the cell, 5... Wiring pattern.

Claims (1)

[Claims] In a hard macro cell that is incorporated on a semiconductor chip and used to realize a large-scale integrated circuit device, a wiring area is provided in advance inside the macro cell for wiring between other macro cells. A hard macro cell characterized by: