JPH03502874A - DC content control device for inverter - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] Invar's T Meno 1 straight beans 1 TECHNICAL FIELD The present invention relates to an inverter control device, and particularly to a DC control device at the output of an inverter. It is connected to a control device that controls the content or direct current content.

i1 Power inverters supply direct current to power one or more loads for long periods of time. Typically, such inverters have been used to convert power into alternating current power. The data generator generates a pulse width modulated waveform (PWM waveform) that contains a series of pulses and notches. Operated by the controller in pulse width modulated mode (PWM mode) to generate It contains a transistor-like switch that is The waveform is sent to the inverter output. The combined filter converts it into a sinusoidal output waveform. Such an inverter , a generator is driven by a variable speed prime mover to produce variable frequency alternating current power; The AC power is rectified, filtered, and input as DC power via a DC link. Variable speed, constant frequency (VSCF) power generation that is given to the converter Used as part of electrical equipment.

Ideally, the controller should be inverted so that no DC power is generated at the output. The data switch should be activated. However, the operating condition is that the DC content is to be generated at the output of the inverter. This DC content is controlled by the inverter. Undesirable consequences if the supplied load cannot tolerate DC content can lead to

U.S. Pat. No. 4,729,082 to 5ato teaches A control device for a power converter that converts between DC and DC power is disclosed. electric power In order to remove the DC component of the current on the AC side of the converter, the control device The converter is operated to generate a direct voltage that opposes the current component. DC voltage is, in one embodiment, a phase displacement that causes a DC component to be generated at the phase output. is generated by shifting half a cycle of the AC output waveform. However However, this patent specification does not explain how or by what means this can be achieved. There is no clear description of what will be done.

” Hadaku 11 According to the invention, a control device for an inverter can be installed in a simple and effective manner. Controls the DC content (DC content) in the converter output do.

In particular, control devices for inverters that generate AC output power are detecting means for detecting the magnitude of the direct current component in the direct current component; To reduce the magnitude of the flow component, the control waveform is controlled by the switch in the inverter. adjustment means for adjusting the time of the selected rising or falling edge; Contains.

In a preferred embodiment, the controller is configured to control the pulse width modulated (P) of the VSCF device. WM) specifically adapted for use with inverters. Preferably within positive direct current When a pulse is sensed, a pulse rises in at least a portion of the PWM control waveform. The rising edge is delayed. Conversely, negative DC content is detected at the inverter output. When the falling edge of at least a portion of the PWM control waveform is delayed be done.

The controller determines which pulse edges should be delayed and by how much. includes edge selection and edge delay circuits. PWMIII51 waveform is inverted delay the selected process by an amount that depends on the magnitude of the DC content at the output of the is applied to the edge delay circuit. Depending on the number of switch responses in the inverter Minimum pulse width or dead time requirement imposed uirements) beyond the point where they would be compromised or Cut/noge selection and one cut delay to avoid delaying the falling edge The circuit can be adapted.

The control device of the present invention includes an inverter that generates rail-to-rail output as well as a rail-to-rail output. It can be used with an inverter that produces a neutral point output.

The control device of the invention is simple in nature and controls the DC content at the inverter output. and thus the problems associated with it are avoided.

・・　　　　t　・ FIG. 1 is a block diagram showing a VSCF device incorporating the control device of the present invention: The second section includes a simplified illustration of the inverter shown in FIG. a combined schematic block diagram showing the device; FIG. 3 is a block diagram illustrating one of the control signal generators shown in block diagram form in FIG. diagram; Section 4 is a block representing one of the edge selection and edge delay circuits shown in FIG. Diagram; FIG. 5 is a schematic diagram showing the edge selection and edge delay circuit of FIG. 4; Each of FIGS. 6 to 8 shows the operation of the circuit shown in FIGS. 4 and 5. waveform diagram; It is.

−; Now referring to FIG. 1, a variable speed constant frequency (VSCF) device 10 is shown. ing. The VSCF device 10 is a variable speed, which may be, for example, a jet engine. 2 generators including a brushless synchronous generator 12 driven by a prime mover 14 The machine uses a polyphase variable frequency power converter that is converted into DC power by a rectifier 16 and a filter 18. Generates several AC outputs. The resulting DC power converts the DC power into an AC power with a constant frequency. is applied via a DC link 20 to an inverter 22 that converts the current into . This AC power is preferably filtered by an optional filter 24 and one or more given to the AC load above.

The inverter 22 includes switches Q1 to Q6 shown in FIG. The switch is controlled by the generator/converter control unit or G/CCU3O. It will be done.

The G/CCU also adjusts according to the parameters of the outgoing power generated at the point of regulation (FOR). Controls excitation of the brushless power generator 8112. This action of G/CCU makes the present invention Since it is not necessary for understanding, it will not be explained in further detail.

In particular, with reference to FIG. 2, switches Q1-Q6 of inverter 22 have associated Ryback diodes (flFback diodes) D1 to D6 and one They are connected in pairs in a conventional three-phase bridge configuration. The switch is base driven and and is controlled by base drive signals generated by separation circuits 32a-32c.

Each base drive and isolation circuit 32a, 32b or 32c is connected to a control signal generator 34. Control signals MA, MB or MC generated by a to 34 c, respectively. Receive each. Each of the control signal generators 34a-34c then generates a signal at the POR. response to a power parameter such as the at pressure.

The topology or topology of the inverter shown in FIG. ) so that the truth output is connected alternately to the top and bottom rails. Because many pairs of switches are connected alternately, it is called a rail-to-rail topology. Ru. This inverter has an additional switch connected between each phase output and the neutral voltage. Rail-to-neutral inverters (sometimes single-neutral clamped inverters) During the positive half-cycle of each phase output, the upper register may be replaced by Switches Q1, Q3, and Q5 alternate with corresponding neutral switches. and the remaining switch Q2 or Q4 or Q6 of the pair is kept off. . During the negative half cycle of each phase output, the top rail switch Q1 or Q3 or Q5 is kept off and switches Q2t, Q4 or Q6 are connected to the neutral Operated alternately with point switch. The phase output is thus Varies between the voltage on one of the rails and the neutral point voltage.

FIG. 3 shows each of the POR phase voltages showing the control signal generators 34a-34c in more detail. are applied to fourth-order or other low-pass filters 40a-40c, and each input Displays the magnitude and polarity of the DC content (DCco, ntent) in the inverter output phase. Generates a warning signal. The signal is processed by an analog-to-digital (A/D) converter. are processed and provided to adders 42a to 42c, and adders 42a to 42c Subtract the reference value REFI~REF3 from and calculate the magnitude of the DC content from the magnitude of zero. A deviation signal representing the deviation of the angle is generated. The deviation signal is sent to the gain and compensation unit 44a. ~44c, each of the gain and compensation units reduces the DC content to zero. 16-bit ADCO representing the necessary correction for inverter switching to Generates a digital word with ADC15. These digital correction words Or to the edge selection circuits 46a to 46c and edge delay circuits R48a to 48c. Given.

Edge delay circuits 48a-48c feed base drive and isolation circuits 32a-32c. generates a control signal that can be

Each edge delay circuit 48a-48c is retrieved from memory 50a-50c (r The pulse offset illumination (PWM) waveform is received. Each memory 50a ~50c are the specific PWM waveforms to be obtained from the memory, as well as the search The high and low order signals receiving the signals determine the phase and frequency selection of the PWM waveform. Contains address input. The low address input of memory 50a is connected to the clock signal. It receives the output of a counter 51 that accumulates pulses. Each of the memories 50a to 50c The high address outputs are used for command signals as well as sensing one or more of the inverters. output parameters. The pattern circuits 52a to 52c are provided with desired inputs. Selection of appropriate PWM waveform from memory 50a-50c to obtain inverter output state The details of the pattern selection circuits 52a to 52c that perform the Since this is not the case, I will not explain it in further detail.

Counter 51 is coupled to an adder 54.56, which in turn 50b and 50c. adder 54 and 56 receive reference signals representing displacements of 120° and 240°; Therefore, the outputs of memories 50b and 50c are their amounts from the output of memory 50a. is displaced. Again, a detailed understanding of phase change circuits is not necessary for understanding the present invention. Since there is no such thing, I will not explain it further here.

Typical pattern for selecting appropriate PWM waveform from memories 50a to 50C The selection circuit was developed in 1988 under the name "Low Distortion Control Device for rVSCF Devices". Reeker et al. U.S. patent application serial number 0 filed on December 16th No. 77285,423 (Sandstrand list number BO2939-^Tl-U SA) as disclosed and claimed. Accurate 120° displacement of memory output The circuit for maintaining the U.S. Patent Application System of Rozman et al. Real number 07/285,118 (Sandstrand list number BO300 3-^Tl-USA). Both of the above patents have been issued. The disclosure of the application is incorporated herein by reference.

As will be described in more detail hereinafter, the edge selection circuits 46a to 46b select the PWM waveform. Whether rising or falling edges should be delayed, and how The length of the extension determines whether a rough correction of the DC content should be performed. add In addition, the edge selection circuits 46a to 46c adjust the pulse width generated by the clock. which pulse edges should be further delayed by a time interval determined by Determine. Edge delay circuits 48a to 48c control the DC content at the inverter output. A delay effect is applied to reduce the impact.

Referring to FIG. 4, the edge selection circuit 46a and edge delay circuit 48a are blocked. is shown in the form of a block diagram.

The edge selection circuit 46a is configured to correct the DC content in the inverter phase output. , the gain and compensation unit 44 representing the required engineering delay. Receives 12 bits ADCO to ADCII in digital language. Bi Nodo ADCO~AD C3 is a fractional delay state machine (i fractional delay 5tate machine) 60, and the remaining bits ADC4 to ADCII is provided to counter/timer 62. Polarity of DC content at inverter output The 16th bit ADC15 representing MADCI obtained from the memory 50a The input control device along with the bit stream (or stream of bits) represented by 64. Bits ADC12-ADC14 are not used, but if desired For example, they are used together with bits ADCO to ADC11 as required for higher resolutions. Can be used to indicate required corrections.

The input controller 64 is also provided with a signal RPSEL, which is shown in FIG. is placed in the high state when the rail-to-rail converter topology shown is used. , also placed in the low state if a neutral-clamped inverter is used. Ru. The signal MAS generated by the three-phase half-cycle waveform generator 66 of FIG. It is also given to the input control device 64. The half cycle waveform MAS is the inverter output If force phase A is in the first or positive half cycle, it is in the high state and the inverter The phase A output of the controller is low when it is in the second or negative half cycle.

The three-phase half-cycle waveform generator 66 also includes phases B and MBS, denoted MBS and MC3. half-cycle waveforms with phase C are generated, and these waveforms are The waveform is the same as MAS except that it is displaced by 120° and 240°. be.

The input control device 64 generates two signals APCLK and APOL IDD, These signals are provided to a pulse delay/output controller 68. Control device 68 , the signal σT generated by the counter controller 70 and the counter output signal RC. Receive O. The controller 69 is then provided to the base drive and isolation circuit 32a. Generates control signal MA.

Counter controller 70 receives signal MARP generated by split delay state machine 60. D as well as a signal APCLK generated by input controller 64. Signal A PCLK is also provided to split delay state machine 60.

The signal processing and bits ADC4 to ADCII together make a rough correction. controlling the amount of delay of selected pulse edges of the PWM waveform to perform the PWM waveform; Signal MA EPD has a clock CLKI coupled to the clock input of counter/timer 62. Which pulse edge is further delayed by a time equal to the pulse width generated by Determine if it should be extended.

Referring to FIG. 5, the circuit shown in block diagram form in FIG. 4 is shown in greater detail. It is. The positioning of the circuit in Figure 5 is slightly different from Figure 4 for clarity. has been changed to. The circuit also shows one of the two states for ease of understanding. Hardware that generates digital signals in response to digital signals with possible waveform forms. It is shown as being implemented in hardware. Therefore, for example, the memories 50a~ The digital bit stream obtained from 50c is shown in waveform MA in FIGS. 6-8. It is represented by DCI. As noted above, however, the rotation in Figure 5 Some or all of the channels may be responsive to digital signals in the form of digital words. It can be implemented in software that generates digital signals.

Bit stream signal MADCI, rail-to-rail selection signal RR3EL, phase a polarity bit ADC15 indicating the polarity of the DC content correction for the inverter output of A; and the half cycle waveform MAS is an exclusive OR gate 102, an AND gate 10 4.106.108 and 110, or gate 112, and flip-flop 114 is provided to logic circuitry 100 including a The logic circuit 100 receives the signal AP OLI, and the signal APOLI is input to one input of exclusive-OR gate 116. given to power. A further input to exclusive-or gate 116 is A delayed version of signal MADCI (v version) M AD CI D is received. Exclusive OR gate is signal AP CLK, and the signal APCLK is connected to the counter controller 70 and the divided delay state. machine 60.

Division delay letter R8! Machine 60 receives bit A obtained from gain and compensation unit 44a. D free flop 122.124.126 and 128 from DCO to ADC3 includes a digital parallel adder 120 that adds the outputs of the . D Flip Flo The clock input which receives the signal APCLK and the addition output of adder 120 SUMI, SUM2, SUM3 and SUM4t - Contains additional inputs to receive. °ru The outputs of the D flip-flops are applied to adders A1-A4. parallel addition Calculator 120 includes a carry output terminal to which signal MAEPD is output. I'm reading. This signal is applied to D flip-flops 130 and 132 which are connected in series. Therefore, together with the output signals APCLKD and APCLKDD, the AND game 134, 136 and an OR gate 138. ora - Gate 138 receives a signal applied to the counter start input of timer/counter 62. Generates σ lower. The signal σ is also equal to ℃ at the output of the counter/timer 62. The AND gate 140 is also given to the JK flip - has an output connected to one input of flop 142; JK flip A further inverting input of flop 142 receives signal APCLKD.

The output of JK flip-flop 142 and D flip-flop 144 and The signal APOL IDD generated by 146 is connected to exclusive-OR gate 148 given to. The output of exclusive-OR gate 148 is D flip-flop 150. , and the D flip-flop 150 then outputs a control signal MA.

Except for D flip-flops 122 to 128 <JK and D flip-flops All are clocked by the clock CLKI, which operates at a frequency of approximately 9.8304 MHz. It should be noted that the clock may be clocked or synchronized.

The operation of the circuit shown in FIG. 5 will be explained with reference to the waveform diagrams in FIGS. 6 to 8. 6th The figure shows according to bits ADC4-ADCII from gain and compensation unit 44a. The scale or scale in Figure 6, which shows the approximate corrections to be made, is The pulse P1 of the signal MADCI obtained from 50a is approximately 25 microphones in the period It's like a second. Along with the tarokku CLKI frequency, The scale shows that the difference between the signals APCLK, APCLKD and APCLKDD is visible in the diagram. Something is going on that cannot be recognized, so only the signal APCLK is shown. Ru. Also, the state of the signal MARPD is determined by the control signal M in a manner that can be detected in FIG. This signal is not shown since it does not affect A.

At time t1, the rising edge of the pulse of bit stream signal MADCI is connected by D flip-flop 118 and AND gates 108 and 110. , and that there is a positive DC content at the phase A output of the inverter.

Combining such signals is accomplished by D flip-flops 118, 130 and 132. The signals APCLK-APCLKD and APCLKD after a short delay imposed by 6 Also, at time t1, which results in the occurrence of a pulse rising edge at D. , signal 71 rises high. This high signal opens counter/timer 62. CLKI, so that when a clock pulse is received from clock CLKI, At time t2, the value represented by ADC4 to ADC11 is decremented to zero. Once this value is decremented to zero, a narrow pulse will appear in the counter/timer. 62 output m, which is then generated by JK flip-flop 142. signal ADPT to switch to a high state. This then translates into the control signal Output MA is also output after a short delay imposed by D flip-flop 150. , causing it to switch to the high state.

At time t3, the signal MADCI obtained from memory 50a switches to a low state. Waru. This means that there is a bit of positive DC content at the inverter output. The signals APCLK, APCLKD and APCLKDD is imposed by flip-flops 118, 130 and 132. After a delay, the low state is returned to as well. Signal APCLKD is low , the output of AND gate 136 similarly switches to a low state, and the next At this point, the signal σT, and therefore the signals ADPT and MA, are also switched to a low state.

With the presence of positive DC content at the inverter output, the control device It can be seen that it narrows the .

This narrowing caused by the delay in the rising edge from time t1 to t2 is This brings about the rough corrections described in .

If there is a negative DC content at the inverter output and each in the signal MADCI Rising and falling pulse edges are input control at times t4 and t5 Assume that it is received by circuit 64. signal APCLK and therefore signal APCL KD and APCLKDD switch from high to low shortly after time t4. and returns to the high state shortly after time t5. The signal m is therefore substantially at time t5 The counter/timer 62 switches from a low state to a high state at The words represented by ADC4-ADC11 are caused to be decremented to zero. this Once the decrement is complete, a narrow pulse is generated at the output RCO at time t6, and then , causing signal ADPT to change to a high state. This means that the control signal MA is This has the effect of switching to the low state shortly after time t6.

The falling edge of each pulse in the MADCI signal is approximately above time from time t5. 6 and then increased positive to the inverter output to erase the negative DC content. It can be seen that the DC content of 6 Referring to FIG. 7, for the rail-to-rail topology shown in FIG. The representative signal MADCI received from memory 50a is a half-cycle reference signal, as well as the signal if a positive DC content is present at the inverter output MARPD. are shown along with the possible waveform states for. This shown in FDO~FD15 These conditions then determine which pulses in each cycle of the inverter phase output delayed by a time equal to the duration of the clock pulse generated by clock CLKI. determine what should be done. As seen in FIG. 7, except for waveform FDO, the signal MA Each of the possible waveform states for RPD corresponds to the rising edge of a pulse in the MADCI signal. A series of pulses with rising and falling edges coincident with rising edges have. If a negative DC content is present at the inverter output, the signal MA The rising and falling edges of EPD correspond to the pulses in the MADCI signal. As seen in the top waveform, which would coincide with the rising edge, the MAD The number of pulses in each full cycle of the CI signal is equal to 15, however, each MAEPD waveform states FDI to FD15 repeat on a time base of 16 pulses. Therefore, each MAEPD waveform state is different at different points in subsequent PWM cycles. For example, the FD1 waveform state for signal MARPD is MA, coincident with the rising edge of pulse P2 in the positive half cycle of the DCI signal. Pulse P2 includes a pulse with a rising edge at time t7 that corresponds to .

which happens to be the center pulse in the first positive half cycle of the MADCI waveform. , such is not required; the FD1 waveform state is not required in the MADCI signal. switches to low state at the next rising edge and remains low until time t8. , at time t8, the MAEPD signal switches high again. This standing The rising edge is the center pulse of the second positive half cycle of the MADCI signal. This coincides with the rising edge of the next pulse, pulse P3. Therefore, all time the selected pulse edge delayed by the clock pulse over the It can be seen that the pulses with are equally distributed throughout the cycle.

Although it cannot be seen in Figure 7 due to the scale of the waveform, the MA The rising and falling edges of the pulses in the EPD state waveform are actually M For the rising edge of the ADC1 signal pulse, the pulse from the clock CLKI It is displaced by the width. Furthermore, the positive DC content (DC content) state waveforms are present at the motor output and therefore require negative correction. Ru. If negative DC content is present at the inverter output, the MAEPD signal The rising and falling edges of the state waveform are clocked from clock CLKI. the width of the clock pulse from the falling edge of the pulse in the MADCI signal. Occurs at the time of displacement.

The high state part of the waveform nFD1 corresponds to a single pulse in a full cycle of the inverter output. It can be seen that the pulse coincides with the pulse starting at time t7, for example. Similarly, waveform state FD I to FDIO are 2 to 10 in the MADCI signal between time t7 and time t8. It is in a high state at the respective times coinciding with the pulse. However, the state waveform During these times, FD11 to FD15 are High for 10-14 pulses each.

FIG. 8 shows, as an example, the MAEPD signal when such a signal is in the FD8 state. The waveform of FIG. 8, which includes a series of waveform openings illustrating the effect, is obtained from memory 50a. Such that pulse P4 of the WM pulse pattern has a width of 0.9 microseconds. It is depicted on a scale or scale.

In the hourly graduation or scale of FIG. 8, D flip-flop 118. The delays imposed by 130 and 132 are caused by the delays imposed by signals MADC1, APCLK, A It is clear that PCLKD and APCLKDD can be identified. Also bit A The corrections represented by DC4 to ADCII are approximately equal to two clock pulses. A coarse correction delay n delay) is imposed on the leading edge of pulse P5 in the MA filtered waveform. It is assumed in the waveform of FIG. 8 that this is the case. Pulse P5 occurs During the time when the MAEPD signal is low, the counter/timer There is no additional delay other than the two clock pulse delays imposed by However, during the occurrence of pulse P6, signal MARPD goes high. be.

Therefore, the two clock pulse delays imposed by counter/timer 62 is increased by an additional clock pulse delay, which increases the width of pulse P6 to is further reduced by three clock pulses due to its leading edge delay. .

Pulses P7 and P8 represent the situation when negative DC content is present at the inverter output. , and thus the falling edge of the PWM waveform is delayed. Pulse P7 is 3 one tarok pulse than the pulse width of the corresponding pulse in the MADCI waveform. It is generated in a signal MA with a large pulse width. These three additional taros The tick pulse is a roughly two clock pulse imposed by counter/timer 62. lock pulse delay, as well as a single clock resulting from signal MAEPD going high. due to clock pulse delay. The next pulse P8 in the MA output signal is M Since the AEPD signal is low, only two clock pulses wider than the corresponding pulse in .

Edge selection and edge delay circuits 46a and 48 for the output of phase A of the inverter. Although only edge selection and edge delay circuit 46a, 46a has been described, other edge selection and edge delay circuits 46a, 4 It should be understood that 6b and 48a, 48b are the same and operate similarly. It is.

From the above, it can be seen that the DC content at the inverter output is reduced using the control of the present invention. It can be understood that it can be qualitatively removed.

The control device of Figure 4 exceeds the limit imposed by the number of inverter switching responses. to avoid the controller changing the pulses and notches in the PWM waveform. It should be noted that it can be modified in any simple way. Therefore, for example, Pal Avoid holes or notches that become too narrow which may lead to defective conditions. The control device can be changed as follows. Such modifications are readily apparent to those skilled in the art. It can be implemented by a meter.

Procedural amendment “voluntary” August 29, 1990

Claims (7)

[Claims] 1. Switch operated according to a waveform with rising and falling edges A control device for an inverter having: Detection means for detecting the magnitude of the DC component in the AC output power of the inverter and; a rise selected to reduce the magnitude of the DC component in response to said detection means; or adjusting means for adjusting the falling edge time; Control device for inverters with. 2. for detecting whether the DC component is positive or negative in polarity. further comprising means, wherein the adjusting means adjusts whether the DC component is positive in polarity or the selected rising or falling edge, depending on whether 2. A control device as claimed in claim 1, including means for delaying. 3. for detecting whether the DC component is positive or negative in polarity. further comprising means, said adjusting means being selected when the DC content is positive in polarity. selected if the DC content is negative in polarity. Claim 1 includes means for delaying the falling edge of the control device. 4. The adjustment means includes an edge selection circuit coupled to the detection means, and an edge selection circuit coupled to the detection means. an edge delay circuit coupled to the edge selection circuit; The circuit generates a selected rise by an amount determined depending on the magnitude of said DC content. 2. The control device according to claim 1, wherein the control device delays falling edges. 5. said detection means each representing an amount of time by which a selected edge is to be delayed; and means for generating a series of digital correction words, the edge selection circuit comprising: Contains a digital timer/counter that receives a series of correction words and a clock signal. , the timer/counter is configured to count each correction word according to its clock signal input. delay each selected edge by the amount of time needed to a program input coupled to a counter; a clock coupled to a clock input of a polarity detector that generates a digital signal indicating whether the A control device according to claim 4. 6. PWM waveform stored in memory and with rising and falling edges N-phase outputs each generated by a pair of switches operated alternately according to A control device for a pulse width modulated (PWM) inverter that generates: A connection to the phase output that generates a signal representing the magnitude and polarity of the DC component at the phase output. a control signal generator for each phase output including a low-pass filter to be combined; a PWM waveform coupled to a filter and to be delayed depending on the polarity of the DC component; an edge selection circuit for selecting an edge of; coupled to the memory, the low pass filter and the edge selection circuit; The magnitude of the DC component at the phase output to generate a control signal to control the an edge delay circuit that delays selected edges of said PWM waveform by an amount that depends on Road and; Control device with. 7. The edge delay circuit is a programmable counter that receives the waveform. the programmable filter including a program input coupled to the low pass filter; a counter, the controller further coupled to a clock input of the counter. and whether the DC component is positive or negative in polarity. a polarity detector for generating a digital signal applied to the counter, shown in FIG. A control device according to claim 6.