JPH0350230B2 - - Google Patents

Description

[Detailed description of the invention]

The present application relates to a timepiece equipped with a data processing mechanism that is easier to use in a photoelectric display type electronic timepiece. The recent development of electronic display elements has dramatically increased the amount of information displayed on watches.
It also contributed to improved reliability due to the solid construction of watches, and lower costs due to automatic production. In conventional watches, many aspects of the watch's specifications were stipulated by technical constraints, and the watches were grouped together in a fairly well-balanced form, but as mentioned above, we were given a greater degree of freedom. Currently, the design concept for watches has not yet been finalized, and designs are being carried out through trial and error, using traditional design concepts as clues. The present invention reanalyzes the characteristics required of a timepiece and constructs a timepiece that effectively utilizes the current large degree of freedom. The basic function of a clock is universal and uniform, and can be summed up in one word: ``maintaining and displaying the current time.'' In reality, there are a wide variety of demands for watches, and various watches are being manufactured to meet these demands. In addition to the basic functions of a watch, the things that are common to everyone are ease of use, legibility, reliability, environmental resistance, etc., and these additional characteristics that are common to the basic functions. A watch with this mark is made into a standard watch. Therefore, in this application, in a photoelectric display type electronic watch, the holding time system holds the time from 1:00 to 12:00 so that it does not reach 0:00, and the alarm time system stores the time from 0:00 to 12:00, including 0:00. A photoelectric display type electronic watch characterized in that the time is held and when the alarm time is "0 o'clock," the data is set to be empty and used as an alarm non-setting state, and a plurality of displays in the photoelectric display type electronic watch. It is equipped with a circuit that detects empty data in which the data is not set, and has a configuration that can sequentially switch and display the data on the same display body, and the empty data detection circuit is configured to detect empty data in which the data is not set. It is an object of the present invention to provide a timepiece that is easier to use by realizing a photoelectric display type electronic timepiece characterized by being configured to be able to detect and display sky data. FIG. 1A shows the block configuration of the timepiece system of the present invention. In FIG. 1A, numeral 100 is a standard component block of an optional watch that provides the basic functions of the watch and characteristics commonly required by the majority of people, and is called a standard part. Reference numeral 120 denotes an optional section that can be combined with the standard section to diversify the watch. The standard part alone has sufficient performance as a watch, and it differs from a normal watch by the potential for adding optional functions. FIG. 1B shows an example of the internal configuration of the standard section 100 in FIG. 1A, where 101 is a time reference signal source, which is composed of a crystal oscillation circuit, etc., and remains stable over time and environmental factors. generate a signal with a time interval of 102 is a mechanism for synthesizing timekeeping unit signals. Reference numeral 103 denotes a clock mechanism, which includes a counter whose initial value can be set, and a mechanism 10 for synthesizing a clock unit signal.
The time measurement unit signal output from step 2 is counted, and the counted value indicates the holding time. A display drive mechanism 104 includes a drive circuit suitable for the display element used. For example, a unidirectional current pulse is supplied to a light emitting diode, and an alternating current driving voltage is applied to a liquid crystal display element so that a long-term integrated charge average value converges to zero. 105 is a display element, for example a light emitting diode,
An electrostatic polarization display element or the like is used. 107 is an energy source, and a silver oxide battery or the like is used. 106
is a control mechanism that controls the time control mechanism of the timekeeping mechanism 103 to correct or set the time kept by the clock. The control mechanism 106 at least controls the timekeeping mechanism of the timekeeping mechanism 103, but may also control the timekeeping unit synthesis mechanism 102, the display drive mechanism 104, or further the time reference signal source 101, the display element 105, or the optional unit 120. In some cases. Time reference signal source 101 and timekeeping unit synthesis mechanism 102 and timekeeping mechanism 103
The rate of the clock can be adjusted by controlling the display drive mechanism 104 and the display element 105, and the display information can be switched and the display format can be specified. The option section 120 may have the same function as the control mechanism 106, or may store information input in advance and transmit the information to each section of the watch. It is also possible to collect information by itself, such as by detecting the ambient temperature and compensating for the temperature dependence of the timing unit signal. Alternatively, it may have a timekeeping function independent of the clock, such as a chronograph mechanism, and simply share only the display section. FIGS. 1A and 1B show examples of information flow paths, and apart from this there is also an energy flow, which is not shown. The number of options is also not limited to one. Figure 2 shows three C/Cs as a specific example of an optional clock system.
A schematic diagram of a timepiece constructed of MOSIC is shown, and FIGS. 3A, B, and C show functional block diagrams of each IC, and the system of the optional timepiece will be specifically explained below. In Figure 2, 201 is an IC version of the basic timekeeping system that has oscillation, frequency division, timekeeping, control, and additional functions.
is specified as 202 is a display driving IC, and by using separate ICs for the basic timekeeping system IC201 and the display driving IC202, the IC yield can be increased and various display elements can be replaced by replacing only the driving IC. There are other benefits. Reference numeral 203 is an example of an option IC, in which the multi-alarm mechanism and automatic speed adjustment functions are combined into one IC. Figure 3A shows the IC of the basic clock system in Figure 2.
FIG. 2 is a functional block diagram of an IC corresponding to 201 of FIG.
The functions of each block will be explained below, and its configuration and operation will be explained one by one. 301 is a crystal oscillation circuit. 302 is a frequency adjustment circuit, 303 is a timing signal generation circuit, 304 is a shift register, 305
is an addition circuit, 306 is a carry detection circuit, 307A
is an erase circuit, 307B is a data input circuit, 308
309 is an output data modulation circuit, 309 is a display modulation circuit,
310 is an alarm mechanism, 311 is a time setting circuit,
312 is composed of a circuit for flexibility. FIG. 3B shows the option IC20 according to the present invention.
FIG. 3 is a functional block diagram of No. 3. 320 is a timing regeneration circuit, 321 is a shift register for data storage, 322 is a data manual shift circuit, 323 is a data mark setting circuit, 324 is an additional shift register for data expansion, 325 is an input identification circuit, 326
is an automatic speed control circuit. Shift register 304 and adder circuit 3 in FIG. 3A
05, carry detection circuit 306, erase circuit 307A,
The data input circuit 307B constitutes a clock counting circuit, and when a clock unit signal is input from the outside, it performs counting and holds the time. The counting circuit using this shift register is based on the timing pulse 3 in Fig. 3A.
It works on 03. FIGS. 4A and 4B are timing pulse diagrams created here. 64 shift registers
It has a ring-connected configuration in which flip-flops are connected in a ring. Each flip-flop is numbered from 1 to 64, and the output of the specified flip-flop is assigned a number from 1 to 64.
It is assumed that Q _k (k=1, 2, . . . , 64), and the output of Q _k is transferred to Q _k-1 every time the φ ₂ signal rises. The output Q ₁ and the time measurement unit signal D ₁ T ₁ are added by an adder, and as a result of the addition, a sum signal S and a carry signal C are created, and the carry signal C is delayed by 1 bit and the D of the output Q ₁ Together with the timing output of ₁ T ₂ , this becomes the input signal to the adder mentioned above. The clock unit signal D ₁ T ₁ is added by an adder, but the carry signal C pulse does not overlap. At the timing of D ₂ T ₁ , the output Q ₁ indicates the counting content of the first digit (i.e., 1/16 seconds) of the 1/16 second digit (i.e., counting from 1/16 seconds to 15/16 seconds), but this D ₂ At the timing of T ₁ , the output Q ₆₁ , Q ₆₂ ,
Q ₆₃ and Q ₆₄ are each 1/256 second digit (i.e. 1/256 to 15/
256 seconds) 1st digit (1/256 seconds) 2nd digit (2/256 seconds)
It shows the contents of the third digit (4/256 seconds) and fourth digit (8/256 seconds). Timing 1 bit earlier than this
Looking at D ₁ T ₈ , the output Q ₆₂ Q ₆₃ Q ₆₄ Q ₁ is each 1/256
Shows the contents of the seconds digit 1/256 seconds 2/256 seconds 4/256 seconds 8/256 seconds. Therefore, when the time measurement unit signal D ₁ T ₁ of the output Q ₁ indicates the counting content of 1/256 seconds, the logical values of the outputs Q ₆₂ , Q ₆₃ , Q ₆₄ , and Q ₁ at the timing of D ₁ T ₈ are The set {Q ₆₂ , Q ₆₃ , Q ₆₄ , Q ₁ } is the value of the 1/256 second digit of the counter with the weight of {2 ⁰ , 2 ¹ , 2 ² , 2 ³ } and 2 ⁰ = 1/256 seconds. The detection circuit detects the state of the combination of {Q ₆₂ , Q ₆₃ Q ₆₄ Q ₁ } at the timing of DiT _{8 (} i=1 to 16) shown in FIG. ₁ as a clock signal and read out with _T2 , the time serial information of the digit Di of the output _Q1 is obtained from the data type flip-flop at the timing of Di+ ₁ , and lasts for the time of the pulse width of the digit Di+ ₁ . It turns out. digital
If Di is to be counted as an m-adic number, it is sufficient to detect a value greater than or equal to m and less than or equal to 15 using the digit Di, and then add 1 to the output Q ₁ using an adder at the timing of Di+ ₁ ·T ₁ . At the timing of Di+ ₁ , output Q ₆₁ is exactly output.
Output because it is the timing Di information of _Q1
Force Q ₆₁ to L for a period of Di+ ₁ . As a result, the signal at the timing Di of the output _Q1 (hereinafter referred to as Di data) is set to 0, and 1 is added to the data at Di+ ₁ to realize m evolution. Like the digits of the moon 1,
2, 3...9, 10, 11, 12, 1, and when counting from 1 to 12, detect 13 or more and 15 or less in hexadecimal, set the own digit to 0, and immediately add 1. In the case of month digits, carry is not carried out to the next digit.
Transmitted to the output terminal as annual output. Data D ₁ is in hexadecimal in units of 1/256 seconds, data D ₂ is 1/256 seconds in hexadecimal
Hexadecimal in units of 16 seconds, data D ₃ in decimal in units of 1 second,
Data D ₄ is in hexadecimal in units of 10 seconds, Data D ₅ is in decimal in units of 1 minute, Data D ₆ is in hexadecimal in units of 10 minutes, Data
D ₇ is in hexadecimal increments of 1 hour, and 0 o'clock is immediately converted to 1 o'clock. Data D ₈ is PM in binary using only D ₈ T ₁ for counting.
shows. Timings T ₂ , T ₄ , and T ₈ of data D ₈ are not used for counting. Data _D9 indicates the day of the week and is in octal notation, and 0 is immediately converted to 1. Data D ₁₀ is the day digit of the date, hour digit data D ₇ 12 o'clock → there is a carry to the PM digit every 1 hour, data D ₈ PM → AM
Every time (1 → 0), there is a carry to data D ₉ and data D ₁₀ . Data _D11 is the 10th digit of the date and is in ternary. Data D ₁₂ is the month digit in decimal. data
D The daily digit of ₁₀ detects 10 or more and sets the own digit to 0.
In addition to adding 1 to the next digit data D ₁₁ , if the 32nd day or more of a large month is detected, set the current digit and the next digit (10th) to 0.
Make it. Similarly, more than 31 days in the small month, 29 days in February in the common year
If more than one day is detected, or more than 30 days of February in a leap year, the current digit and the next digit (10th day) are set to 0, a carry signal is applied to the next next digit (month), and 1 is added to the 1st day digit. Add.
In this case, a gate circuit may be set at the output Q ₆₁ so that the first digit is set to 0 and the next digit is set to 3. Data D ₁₁ only needs to detect 4 or more and set its own digit to 0. The month carry output is connected to a counting circuit consisting of two flip-flops provided redundantly within the IC, and a gate circuit detects a leap year, which can be input to the leap year designation input. Data D ₁₃ to D ₁₆ indicate alarm times. Data _D13 is the 1 minute digit of the alarm time and is in decimal format. Data _D14 is the 10 minute digit of the alarm time in hexadecimal format.
Data D ₁₅ is the hour digit of the alarm time, which is in hexadecimal format, and 0 o'clock also exists. Since 0:00 is a time that does not exist in the holding time, it can be used as an alarm non-setting state. Because of this configuration, the alarm time of 0 o'clock when the watch is powered on does not represent any actual data, so there is no need to worry about the alarm going off even if the user holds it until the desired time is set. will disappear. This can be used as a more convenient configuration as the amount of data such as multi-alarms increases. Data D ₁₆ represents the PM of the alarm time at the timing of D ₁₆ T ₁ , and a carry signal is added every time data D ₁₅ changes from 12 to 0. Data D ₁₆ timing
In D ₁₆ T ₈ , the alarm is set to H for a permanent alarm setting and L for a temporary alarm setting. data
The timings D _{16 T 2} and D ₁₆ T ₄ of D 16 are set by the logic gate of the output part of Q ₆₁ so that they are always low, but they are set by the external signal by the data input gate set after the gate circuit. It is now possible to set it to H. The fact that the timing D ₁₆ T ₄ of the data D ₁₆ is H prevents detection of coincidence between the alarm time and the holding time. This function can be used to trigger conditional alarms, such as alarms that specify the day of the week or month and day. Data D ₁₆ timing
In the D ₁₆ T ₂ , display specification information for changing the display screen from hour and minute display to month and day display is defined, and by specifying this with an external signal, information stored in the alarm information storage register can be read from the outside. It can be shown as a month and day display. Alarm time information data using external data input terminal
D ₁₄ , which transfers D ₁₃ D ₁₄ D ₁₅ D ₁₆ to the input signal of Q ₆₀ ;
When signals 3, 2, 12 and D ₁ T ₂ are input from the outside at timings D ₁₅ , D ₁₆ , and D ₁ , December 23rd is displayed in an alarm time display state.
In the explanation of the present invention, the reason why the hour and minute display of the holding time is expressed separately from the hour and minute display of the alarm time will be explained.
PM display, colon:, second digit display, second scale display, and hour/minute data are used to display the hours and minutes specific to the time being held.In the alarm time display, the second digit is erased and the appearance of the display surface is changed. This is because in the day of the week display, the colon and AM/PM are deleted and the date mark and day of the week character symbol are displayed, so that the type of displayed data can be clearly seen at a glance. Table 1 shows the count values of each digital data in the circuit system of the present invention. There is not just one way to select the numbers for the day and hour digits, but for the day, 0 to
It may also be 6 in hexadecimal. In the circuit of the present invention, seconds are displayed on the display surface.

[Table] shares part of the day of the week segment with the table, and changes the display pattern, so instead of using 10-second digits as 0-5, day of the day is expressed as 1-7. FIG. 5 shows the circuit of the present invention, the shift register 304, adder circuit 305, carry detection circuit 306, and erase circuit 30 in FIG. 3A.
7A shows the actual carry portion consisting of the data input circuit 307B. 804 is a 60-bit shift register, 805 is an adder, and S=α・+・
The relationship is βC=α・β, and the 2 of α and β
When adding base values, the sum signal is S and the carry signal is C.
It's getting old. Here, α and β are inputs to the adder 805. The output of carry signal C is delayed by 1 bit in the shift register and becomes carry signal 811, which is ORed.
One count is added via gate 809 at the timing of the upper digit. As long as the carry signal 811 and another addition signal X do not overlap, the OR gate 809 also performs the addition function. Since there is no overlap, there is no need to consider carry in OR gate 809. 60-bit shift register 804 and adder followed by shift registers 824, 823, 8
22,821 are the clock signals φ _{1 and} φ 1 of FIG.
Shifted by φ ₂ . The shift reads the output _Q1 of the previous stage as data Di _{+ 1} at the timing of the clock signal _φ1 , and outputs it to the next stage as the output Qi+ ₁ at the timing of the clock _signal φ2. 2, 3...63). Figure 5 shows the digital pulse.
D ₁₅ is the alarm digit, and “13”, “15” and “14”, “15” are D ₁₅・{Q ₆₅・Q ₆₄・(Q ₆₃ + ₆₃ )・
Q ₆₂ +Q ₆₅・Q ₆₄・Q ₆₃・(Q ₆₂ + ₆₂ )}=1 is detected as being true, and this is read into the data type flip-flop as data input at the timing of T ₈ φ ₁ . , T ₁ φ ₂ timing.
In FIG. 5, this flip-flop for T ₈ φ ₁ reading and T ₁ φ ₂ reading is abbreviated as 812.
The above alarm time digit signal is detected at the timing D ₁₅ T ₈ φ ₁ , read out as W ₁ and added to Y at the timing coinciding with the digital pulse D ₁₆ .
Similarly, the daily digit of digital pulse D ₁₀ is set to “0”.
"day" is detected and a timing signal for digital pulse _D11 is created.For the month, day, day of the month, and hour, the own digit after the digit must be set to "1", so these digits are combined (D ₇ +D ₉ +D ₁₂ +“0 day”・D ₁₁ )
A signal that detects data “0” and “13 or more” at the timing of and sets the upper digit and the own digit to “1”
W ₂ is created. The signal W ₂ is added to the erase signal Y as an addition signal T ₁ W ₂ with X and W ₂ intact to set the upper digit and the own digit to "0", and then the timing of T ₁ is applied to set it to "1". is added to the setting signal z. Digital pulse D ₉ is 8 of “1 to 7”
Since it is a hexadecimal, the function of detecting "13 or more" has no meaning. W ₃ sets the current digit to “0” and the carry to the next digit (later digit in time and becomes the upper digit) to “1”.
It is a collection of groups that perform only
Day digit (D ₁₁ ), 10 seconds, 10 minutes in hexadecimal, alarm 10 minute digit (D ₄ , D ₆ , D ₁₄ ), 1 second, 1 minute, 1 day in decimal,
Alarm 1 minute digits (D ₃ , D ₅ , D ₁₀ , D ₁₃ ), binary
It is detected that each of the PM digits (D ₈ ) is greater than or equal to the number that should be carried out, and is set as W ₃ . W ₃ is added to X as T ₁ W ₃ and also added to Y as W ₃ . The transition point from 11 o'clock to 12 o'clock in the hour digits of the hour and alarm is detected and set as W ₄ , and the PM and alarm PM digits are changed (D ₁₅ , D ₇ ). This may be done by detecting 11 o'clock and storing it in a latch, and using a logic circuit to differentiate the latch output when it is no longer 11 o'clock, thereby creating a signal synchronized with the fall of the latch output. For the date digits, use a latch to memorize the major month, February, 30th, and 20th, and at the timing of the 1st digit (D ₁₀ ), enter {(32nd or more of the major month) + ( 31 days or more of a small month) + (30 days or more of February) + (change from February 28 of a normal year)}, set the day digit to the 1st, and add the digit to the month digit. Let's do it. FIG. 6 shows an example of the circuit configuration of a clock system according to the present invention, which is a mechanism involved in setting time information. S _H , S _M , S _K , and S _D are input terminals for specifying data to be set. They are connected to the output terminals of flip-flops that are constantly reset by a narrow reset pulse, and have low input impedance.
The logic level is "L". S _H specifies the decimal or hexadecimal digit, S _M specifies the sexagesimal digit or 28, 29, 30, 31 decimal digit, and S _K specifies the second, minute, hour, PM of the retention time KT.
It is generally correct to assume that S _D specifies the day, month, and day of the day in the date digits. S _UO and S _UT are unlock switch input terminals that make it possible to set the clock time. The reason why the input terminal circuit for setting the logic level is not connected to the input terminal of the SUT is for convenience when the SUT is connected and used as, for example, SK. S _U1 and S _U2 are data input terminals for creating setting data. The clock system of the present invention differentiates the input signals of S _U1 and S _U2 by a logic circuit and calculates SU ₁ ↑, S _U2
↑ has been created so that the data can be set at any speed of the operator's choice. Of course, it is also possible to connect S _U1 and S _U2 to another signal source to fast-forward at a fixed frequency. S ₁ and S ₂ in FIG. 6 are differential signals of S _U1 and S _U2 , respectively, whose rising edge is synchronized with the rising edge of the digital pulse D ₁ and whose width is equal to the repetition period of the digital pulse D ₁ . Next, the selection of setting digits will be explained. The "minute" digit of the held time is corrected by the signal S ₁ in _{the H} , S _M , S _K , _D , and UL states. The selected state of the setting digit is delayed by 1 bit in the data type flip-flop 812a, the timing is specified to set "1" in the gate 901, the selected state is added in the OR gate, and the output of the OR gate 903 is is added to the adder. Since the input pulses of the OR gate 903 all have different phases and do not overlap, signal addition can be performed by a simple OR gate without carry. The data type flip-flop 812a has a synchronizing function for reliable operation since the change in logic level of the switch input for setting digit selection is independent of the clock system. It also has a noise removal effect. Similarly, the “hour” and “PM” of the retention time are
SH・_M・S _K・_D・UL, “day” in the date is _H・
S _M・S _K・S _D・UL, “month” of the date is S _H・_M・
S _K・S _D・UL, “minute” of alarm time is _H・
S _M・_K・_D・UL, alarm time “hour” and “PM” are set when SU ₂ is changed from “L” to “H” while S _H・_M・_K・_D・UL is “H”. 1 in the given digit
will be added. Gate 902 is a gate that prohibits carry. In normal operation, the above-mentioned carry detection mechanism generates a carry signal for the next high-order digit at a predetermined value for each digit, and an adder adds the data to the high-order digit. When correcting or resetting the holding time, it is more convenient to prohibit carrying. For example, if there is a carryover to the hour digits when the minute digits are corrected, it will disappear unless the hour digits are reset. From the correction digit selection gate to the digit prohibition gate 9
02 is directly connected without going through a data type flip-flop, because malfunctions can be ignored based on probability. In selecting the set digit, the digital signal is selected at an earlier timing by one digit delay in the data type flip-flop 812a. “Daily” for setting the day of the week for the date and distinguishing between (temporary alarm) and (daily alarm) alarms
The designated marks are _H , _M , S _K , S _D , respectively.
At UL=1, _H・_M・_K・_D・UL=1
Set by “L” → “H” of S _U1 . Similarly, the second returns to zero in two modes _{: H} , _M , _K , S _D ,
“L” of SU ₂ in UL and _H・_M・S _K・_D
→This is done by changing “H”. FIG. 7 shows an example of the circuit configuration of the alarm mechanism. When the data type flip-flops constituting the shift register ring are numbered as described above,
The 60th data input is written as DATA60. Similarly, the data input of the 28th flip-flop (which is equal to the output of the 29th flip-flop) of the shift register ring is designated as DATA28.
An exclusive OR gate 1004 detects a mismatch in the logical values of DATA60 and DATA28, and a comparison is made between the holding time tkT and the alarm time tAT. Since the DATA60 signal is delayed by one digit compared to the DATA64 signal, for example, DATA60 seen at the timing of digital pulse _D2 is 1/2
56 seconds digit, 1/1 at digital pulse D ₃ timing
Shows the 6 second digit. Similarly, at each timing of D ₆ , D ₇ , D ₈ , and D ₉ , DATA60 is 10 minutes of the retention time.
Shows minutes, hours, PM symbol, while data 28
Since DATA 60 is delayed by 32 bits or 8 digits, DATA 28 each indicates the minute, ten minutes, hour, PM, and other symbols of the alarm time. To detect time coincidence, the set priority flip-flop 1003 is set at the timing D ₅ T _{8 φ1} , and the flip-flop 10 is activated by the mismatch output of the exclusive OR circuit 1004 for mismatch detection.
Reset 03. If tKT=tAT, D ₆ ~
D ₉ timing period flip-flop 100
3 remains set. To be exact, D ₉ T ₂ φ ₁
Hold time tKT and alarm time until the timing of
Compare with tAT. 10 at the timing of D ₉ T ₄ φ ₁ in the data type flip-flop 1005
The content of the output of the flip-flop 05 is read, and from the comparison of the holding time tKT by the gate 1004 and the alarm time tAT, the output of the flip-flop 1 is read.
Since there is a delay until reading 005, as a result, DATA60 and DATA28 are D ₆ T ₁ φ ₁ to D ₉ T ₂ φ ₁
will be compared until then. The timing value of DATA60 signal D ₉ T ₂ φ ₁ is always “L”,
The timing value of D ₉ T ₂ φ ₁ of the DATA28 signal is also always “L”, but when the contents of the shift register are forcibly set from the outside through the DIN terminal, the D ₉ T ₂ φ ₁ timing value is set to “L”. Can be set to the relationship ≠DATA28. Alarm coincidence is indicated by the output logic value of the flip-flop 1005 being "H", which means that the output logic value of the flip-flop 1005 is "H" continuously for only one minute, since this is a comparison in units of minutes, i.e., tKT=tAT.
In others, it is "L". flipflop 1005
The flip-flop 1006 is triggered by the rise of the output from "L" to "H". The output of the flip-flop commands the sound output of the alarm, and in the configuration of the present invention, the duty is 25% at 2048 Hz and 1 Hz.
It is double modulated with the signal. If this double modulation output is further modulated at several Hz and turned into a sound, it can be made to sound like the chirping of a cricket, resulting in an alarm signal that is less irritating and attracts attention. When flip-flop 1006 rises, flip-flop 1007 is triggered. The output F of flip-flop 1007 commands the flashing of the watch display. Flip-flops 1006 and 1007 are both preferentially reset by the clock data inputs S ₁ , S ₂ and the STOP input. This allows the watch user to communicate an alarm confirmation to the watch, to which the watch responds by canceling the alarm. Even if no confirmation operation is performed on the alarm, the alarm signal output will automatically stop after one minute. This prevents battery consumption and
It is also necessary to avoid causing noise to others. Even in this case, flushing continues without stopping.
It will stop only after confirmation. Flip-flop 1006 receives a signal from gate 1008 one minute after the alarm match, and is forcibly reset. The output of flip-flop 1005 is read in with a delay in data type flip-flop 1009.
Gate 1010 connects flip-flops 1005 and 1
From the output of 009, a coincidence signal of tKT=tAT (1
Detecting the fall of the width (width). DATA28 is
In the case of a daily alarm, the setting is detected at a timing of D ₉ T ₈ φ ₁ , and an erasure prohibition signal having a width of D ₁₀ →D ₈ is created. The erase signal ERASE is set to ERASE= from the alarm match signal ALDET of the flip-flop 1006, the logic NOT output _QER of the erase inhibit signal, the modified unlock signal UL, the digital timing signal, and tATO indicating alarm time 0.
(D ₁₄ +D ₁₅ +D ₁₆ +D ₁ T ₈ )...(tATO+Q _ER・
ALDET). From the above explanation, generation of a time reference signal, generation of a timing signal, and
The configuration of the counter, the configuration of the operation input terminal, the configuration of the alarm mechanism, and the basic operation of the whole were shown. In the timepiece system of the present invention, the display surface of the timepiece is switched to three states, that is, displaying the holding time, displaying the alarm time, and displaying the date, and the display is driven based on the idea that the expression of the display surface is changed to facilitate identification. The decoder of the circuit is made to distinguish between multiple states, and the display can be inverted, erased, or transformed by modulating the display data with the main circuit. Furthermore, when a correction digit is selected, the digit is displayed by flashing. Regarding the modulation of these displays,
This will be explained with reference to FIG. The portion depicted in matrix representation 1101 in FIG. 8 mainly modulates display data. The meaning of the matrix is that the combinations of the signals written on the bottom of the vertical column and the signals written on the right side of the horizontal row are indicated by intersection points, and the intersections surrounded by circles are the selected combinations. As shown in the upper part of the matrix, the sum of the logical products corresponding to each intersection point is created, and the waveform is shaped and delayed by 1 digit or 4 bits using a data type flip-flop array. The signal is then intermittent by the intermittent gate 1103 and sent out 16 times per second with a time width of 4 msec.
Intermittent signals are marked with a △. The system of this watch is shown in a matrix representation in Figure 8 not only for the sake of ease of viewing, but also because the configuration itself is realized using, for example, a matrix-like read-only memory (ROM), allowing for a variety of watch specifications. It also represents the ease of standardization and specification changes. This is an appropriate construction method considering the current situation in which a dynamic ROM that cleverly utilizes clock signals can be constructed in a small occupied area in a C/MOS IC. Matrix 1101
On the right side of the line is written the reason or purpose for selecting the intersection above that line. The output of the shift register ring DATA60 shown in FIG. 7 is delayed by one digit from the output of the shift register ring _Q1 , which is the reference of this system. are other parts of the system such as
Q ₁ It is 1 larger than the subscript of the digital signal used for signal processing. The output of the gate 1107 and the output of the matrix 1101 are added together to modulate the display signal, but the gate 1107 forcibly sets specific data of a specific digit to "L". Matrix 110
Modulation is performed by setting specified data to "H" in a predetermined mode using 1. φ ₁ Hz is created by latch 1108 in FIG.
9 and 1110, the signals φ ₁ F and φ ₁ G having different phases for modulation are obtained. F is a flashing signal of the alarm coincidence output, and G is a flashing prohibition signal shown at the lower left of FIG. Terminal 1111 is a continuous terminal, and a reset flip-flop 1114 is continuously reset with a narrow 1 Hz signal of BD ₃ T ₈ .
It is always set to "L" by the Q output of . The CONTA output at the bottom right of Figure 5 has a shift register of 1/16.
This signal is obtained by detecting the moment when the second digit becomes "0". Using this signal, the latch 1112 in the intermittent circuit 308 in FIG. By creating a signal with a width of one memory cycle of approximately 4 msec synchronized with _φ1 , which is delayed by 7 and a half bits from the moment when the signal becomes φ1, and by making an AND of this signal and _φ2, a clock that does not generate noise components during intermittent operation can be created. It is used to obtain signals. The sum signal of the output of latch 1112 and the serialization setting terminal 1111 is further reread by latch 1113 which uses _φ2 as a clock signal, and the 1/16 second digit becomes "0" in synchronization with _φ2 , resulting in an accurate 8-bit delay. A signal with a width of one memory cycle is created, and the DATA signal of the shift register output of T ₈ , φ ₁ and 1102 is sent to the intermittent gate 1105,
1106 and 1103 provide intermittent output of 16 times per second. Figure 9A shows details of the option circuit example in Figure 3B.
9 to 9F. FIG. 9A shows an example of the configuration of a multi-alarm option circuit. The shift register in the center of the circuit diagram is 1
It consists of 64 data type flip-flops numbered 11-448. in the middle
The ring is cut off at the two terminals Axo and Ax ₁ , but this is so that a shift register can be added separately.
Connect Ax ₁ directly. The DouT output is connected to the DATA-IN of the main system as explained above,
D _GL output is connected to DATA CL of the main system. (See Figure 3A). DATA OUT of the main system is connected to D _IN . φ ^* ₂ and Contφ are preliminary signals in case another optional system is used. 9th
Since D _IN , φ ₁ , and φ ₂ in Figure A are intermittent signals, care must be taken to distinguish them when considering them together with the main signal. The optional system is configured to operate normally regardless of whether it is intermittent or continuous. Gate 1401 modulates the alarm time portion of the data sent to the clock system of the present invention. FIG. 9B shows a circuit diagram for generating the timing signals S _B and S _A. Gate group 1402 creates timing S _B for forcibly writing option data into alarm data of the clock system of the present invention. The gate group 1403 determines the timing at which the data of the clock system according to the present invention is passed to the shift register of the optional circuit shown in FIGS. 9A to 9G.
This is to create the S _A signal. Basically, the timing signals S _A and S _B are also used in the alarm data section 4 of this device.
Regarding the digital timing, the main unit's DATA
OUT and DATA IN of this device are DATA OUT.
is delayed by 4 bits, so S _A and
There is a timing difference with S _B. The clock pulses sent from this device are 16 times per second, 64
However, in order to sequentially send the option alarm data to the alarm data section of this device and have this device detect the time, the relative phase relationship between the option and the shift register of this device is 4 bits each time. Must be shifted digit by digit. Therefore, clock control gate 1410 removes 16 bits of the 64 bits of the clock pulse. The cancellation signal is CONTφ, which is created in FIG. 9C. gate 1404
is a gate that receives a date matching signal in the month/day alarm and erases date-designated alarm data. Gates 1405 and 1406 are gates for writing data into the symbol part of alarm data, and designate a normal alarm, daily alarm, and date conditional alarm. Gate 1407 switches between reading new data from the main body into the option shift register or causing the option shift register to operate closedly as a ring memory. A gate 1408 detects when the alarm data is "0" (empty data), and a gate 1411 detects when the erase state is "15". In FIG. 9C, manual shift circuit 1420
This function is related to data shifting in order to check and correct the display data that has already been set in the multi-alarm display state, and to check the contents of other already set data. Connect the MS _IN terminal to S _UT and data will be sent one by one each time it goes from “L” to “H”, so you can check multi-alarm data while manually sending it, and you can also view even more data at a glance. If it remains “H” for more than 2 seconds, the data will be automatically fast-forwarded at 1Hz, and the “H”
→When the gate 1422 is returned to “L”, automatic shifting of data stops immediately.The manual feed signal is “L”→
Circuit for creating pulses synchronized with “H”, 142
1 is a timer circuit for automatic feeding. 1421,
The two types of shift signals in 1422 are hereinafter referred to as 1423.
The timing is set by the gate of , and becomes the signal CONTφ that controls the clock pulse of the shift register. Multi-alarm allows you to set multiple alarm times. In this embodiment, the shift register for additional functions is 64 bits, and one set of data is 4 digits.
Since the digit is 4 bits, 64/(4×4) = 4 sets of alarms can be set. However, in order to set an alarm specifying month and day, the month and day are stored as one set of data, so only two sets of alarms can be set by specifying month and day. The number of alarm sets can be increased by adding a register between the Axo and Ax ₁ terminals on the left side of Figure 9A. In reality, the time is not necessarily set in all of the plurality of alarm registers, and in that case, 0 is written in unset registers as described above. The clock data is in 12-hour format and there is no 0:00 mark, so an alarm set at 0:00 will never match the clock data. Therefore, it is suitable as an unspecified processing method. In particular, the following points are intended by the present invention as a response of the watch when the user switches the watch to alarm mode. In other words, if there is an alarm register that has not been set, alarm settings can be added, and the user's main concern is whether or not alarm settings can be added, so when switching to alarm mode, , if there is a free space in the register, first display this (display only one "0") to attract the user's attention. Therefore, when the user puts the watch into alarm mode, the watch first searches for empty data in the additional alarm register for about 0.5 seconds. In other words, during this time, there is no signal from the manual shift circuit in Figure C of Figure 9.
The CONTφ signal opens the gate of the clock control circuit shown in FIG. 9A, and a shift pulse is transmitted to shift the data in the additional register. 9th
The gate 1409 on the right side of Figure C is opened and closed by a signal, and this signal is
STOP” circuit. As shown in the figure, this circuit is a flip-flop (FF) using a NOR gate, but the _Q9 /60S input to the lower left terminal
↑ Output because it is set every 60 seconds by the signal
QSTP is L, which is transmitted to the circuit shown in FIG. 9C to open gate 1409, allowing the CONTφ signal to pass through. When the additional register is shifting, gate 1408 in the upper right corner of FIG. 9A examines whether the data is zero. The time of 0.5 seconds is D
Qφ _3AT entering the circuit is created at the interval between the rising edges of the Qφ _3AT signal. It takes 0.5 seconds to find empty data among several data.
Although it appears to be an unexpectedly long time, it is possible to improve the exchange of data between the main body register and the display section and additional registers in order to reduce power consumption, as proposed in Japanese Patent Application No. 49-125801 related to this application. This is because the embodiment of the present application also happens to use a configuration in which the processing is performed "intermittently" rather than continuously. During this 0.5 seconds,
Even if several pieces of setting data appear alternately on the display screen, to the user's eyes, it appears only as the display unit blinking, and this period is not for the user to read the display. If you adopt a configuration that does not use "intermittentization",
Searching for data is instant. If no empty data is detected, that is, when all alarm registers are set to the time, if 0.5 seconds elapse, the circuit shown in Figure 9D is activated.
The Qφ _3AT signal is added, but since this is a set signal, the state of the FF does not change, and the CONTφ signal generated by the circuit in FIG. 9C continues to be transmitted to the clock control circuit in FIG. 9A, but at this stage. In this case, CONTφ is a continuous H level, and the gate is opened to allow the shift signals of φ ₁ and φ ₂ to pass through. The main body register and the additional register continue to shift in parallel, and one of the alarm time setting values selected at that timing is read into the main body register and sent to the display section for display. The same time will continue to be displayed until the user presses a button to advance the display, but this is because the main register and additional register shift in parallel, which fixes the phase of both, and the same data is repeatedly transferred from the additional register to the main register. This is because it is sent to When the button is pressed, as mentioned earlier, in order to change the phase between the main register and the additional register, the supply of shift pulses to the additional register is stopped for 4 digits, causing a phase shift of 1 data, and the next Data is displayed. The φ ₁ and φ ₂ inputs at the bottom left of FIG. 9A become shift pulses φ ₁ and φ ₂ ,
If the two gates (unsigned) under the "clock control" 1410 in the same figure are open, φ ₁ and φ ₂ pass through and the shift continues; if they are closed, the shift pulse is not transmitted and the additional register 321 is The shift is temporarily stopped and the phase with the main body register is adjusted. Clock control 1 opens and closes the gate.
It is controlled by the CONTφ signal input to 410. However, if there is a register for which the alarm time has not been set, the alarm time is set to "0" during the above 0.5 seconds.
The setting or "empty" is detected by the "0" detection gate 1408 in the upper right corner of FIG. 9A, producing a 0HAT signal;
This is transmitted to the terminal with the same name on the left side of D in Figure 9, and FF
is reset and the output becomes H, which is transmitted to the C circuit, gate 1409 is closed, and the CONTφ output becomes L. The CONTφ signal is transmitted to the clock control circuit of A to close the gates of shift signals φ ₁ and φ ₂ , and the shifting of the additional register is temporarily stopped. However, 0.5 seconds after the mode switching, the FF of circuit D is set by the Qφ _3AT signal as described above, and the signal becomes L, so the CONTφ signal is output again from circuit C and the clock control circuit of circuit A is output. The gate opens, the shift signal is transmitted, and the main register and additional register continue shifting in parallel. The shift of the additional register is stopped from the time "0" is detected within 0.5 seconds until the end of the 0.5 second period, but due to this stop, the phase of the additional register is changed to 0 repeatedly by the main register. The phase is adjusted to read the data, and thereafter the phases of both registers are fixed and the display continues to display "0", indicating that there is an empty register. Thereafter, each time the button is pressed, the phase of the register is shifted, and other set values are sequentially displayed. When the user switches to the alarm mode in this way, priority is given to displaying empty data first. The circuit 1430 in FIG. 9E regenerates digital pulses D 1 to D ₁₆ from the reference digital pulse D ₁₁ and boosting signals φ _UC1 and φ _UC2 using ₁₆ latch circuits. Since the rise and fall of φ _UC1 are synchronized with T ₁ , φ _UC1 and φ _UC2 and φ ₂ and φ ₁ to 1431
The circuit can reproduce the timing signals _T1 to _T8 . The circuit 1424 in FIG. 9F compares the month/day signal of the main body data, the month/day signal of the optional month/date alarm data, and the month/day of the optional month/date alarm data, and if they match, an alarm is activated. Month/day data and alarm symbol data that means the combination of month/day data and time alarm data.
Erase the timing part of T ₂ , that is, the connection mark. The circuit 1425 in FIG. 9G is an optional alarm data erasing circuit, which erases alarm data that matches the time held in the main body. This is because the alarm data of the option is forced to be input into the alarm data section of the main unit under normal operating conditions, so even if a matching alarm is deleted on the main unit, the corresponding alarm data of the option will not be deleted. is necessary. Figure 9D
The gate circuit of the 1426 SRG-STOP keeps the relative relationship between the shift register between the main unit and the alarm unchanged and switches the main unit when detecting the alarm time correction/setting state and the match between the alarm time and the hold time. This shift stop command circuit is necessary so that the alarm time data created by the operation is correctly transferred to the corresponding data of the option, or that the deletion of the alarm data of the option and the main body match. It is possible to construct the IC at a lower cost by minimizing the number of terminals on the watch's IC, and the fewer the number of interconnections between the ICs, the more advantageous it is for watch assembly. It is necessary to know from the state of modulation. A 1 Hz signal is detected from the DIN data input signal, and a 2 Hz φ ₃ signal and its delayed signal φ ₄ and φ 1 and φ ₂ signals that are different by a half period of ₁ Hz are created from the rising and falling edges of the signal. Since this signal φ ₃ does not overlap with the 1 Hz signal of display flashing, the information taken out from the main system DATA output in synchronization with φ ₃ is correct information that is not affected by flashing. If it is not detected in synchronization with _φ3 , erroneous information will be read due to the influence of the entire flashing modulation of the main system output data for the flashing of correction digits and the flashing of alarm coincidence. Depending on the display status of the main system, the display digit D _D is the date in _D11 and the retention time in _D5 .
At tKT, D ₁₃ , the alarm time tAT is displayed. FIG. 10 is a diagram showing the operation of this clock system, and when both S _K and S _D are 0, the alarm is set and displayed. As described above, according to the present invention, by keeping the alarm time at 0 o'clock and making it empty data,
It is extremely convenient for initializing the clock and for retrieving multiple pieces of data.

[Brief explanation of drawings]

FIG. 1A is a block diagram showing the connection between the main body system and the optional system of the watch. Figure 1B is a functional block diagram of the main body system of the watch. Figure 2 is a diagram of the configuration of an optional watch with three IC configurations: option, timekeeping, and display drive. FIG. 3A is a functional block diagram of the timekeeping IC of the watch body. FIG. 3B is a functional block diagram showing the contents of the option IC. FIG. 4A is a diagram showing the relationship between the waveforms of a clock pulse, and FIG. 4B is a diagram showing the relationship between the waveforms of a timing pulse and a digital pulse. Figure 5 is a timekeeping circuit diagram. FIG. 6 is a time setting circuit configuration diagram. FIG. 7 is a configuration diagram of the alarm mechanism. FIG. 8 is a configuration diagram of an output data modulation circuit. FIG. 9A is a circuit diagram showing an option shift register storage section. Figure 9B is a circuit diagram for producing timing signals of S _A and S _B , Figure 9C is a circuit diagram for producing a CONTφ signal, Figure 9D is a shift stop command circuit diagram, and Figure 9E is
9 is a timing signal reproducing circuit diagram, FIG. 9F is a connected mark erasing circuit, and FIG. 9 G is an alarm data erasing circuit diagram, all of which constitute an alarm option mechanism. FIG. 10 is a diagram showing the operation of the present timepiece system. 1420...Manual shift circuit, 1410...
...Empty data detection circuit.

Claims (1)

[Claims] 1. In a photoelectric display type electronic watch, a memory circuit that holds a plurality of alarm time data, a display drive circuit that receives the alarm time data read from the memory circuit and creates a display drive signal, and a display drive circuit that generates the display drive signal. a display element that receives an input signal and displays an alarm time; a manual shift circuit that receives an input signal from a switch operation by a user and controls readout of alarm time data so as to sequentially display the plurality of alarm times for confirmation; a detection circuit for detecting "empty" data included in the alarm time data; and a circuit for controlling the manual shift circuit so as to display the "empty" data with priority in response to a detection signal from the detection circuit. A photoelectric display type electronic clock characterized by: