JPH03500344A - Electronic assembly with self-test circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] Electronic assembly with self-test circuit The invention relates to an electronic assembly according to the features of the preamble of claim 1 of the claims. It is something.

In order to ensure and evaluate its correct functioning, electronic assemblies must be The test will be repeated during the test. For this purpose, the assembly is processed using inspection data (output data) By comparing the appropriate tests, it can be confirmed whether the circuit being tested is normal or not. recognized. For example, an inspection pattern can be transferred from an automatic inspection device through the input bin of the inspected object. and supply it to the inspected object, and the inspection data is sent to the automatic inspection equipment via the output bin. It is possible to inspect. In this case, the occurrence of the inspection pattern is also an evaluation of the inspection data. This is also done outside the inspected object. circuit parts that are not directly accessible from the outside. The possibility of inspecting even can be obtained.

Already from German Patent No. 2902375, for stepwise operation consists of a series of flip-flop circuits arranged one after the other in a self-testing circuit. Its use as a check circuit is well known. This circuit contains the current output state of the circuit. and a direct input terminal is present as related to the previous input signal. circuit The output terminal is connected to the data input terminal of the digital logic module to be tested. and the output end of the digital logic module is connected to the input end of the second circuit. There is. The output signal of the first circuit is thus supplied to the logic module and Each output signal of Joule is applied to one input of the first circuit, and its state is determined by the first circuit. The logic module responds to each input signal from the circuit. In other words, the inspection method At the end, the output of the second circuit receives the last input signal of the second circuit and all the preceding ones. There are states related to all input signals.

Thus a unique output characteristic for the logic circuit's successive answers to every test sequence. A signature is generated. This output signature is then output at the end of the test train. Predetermined test signatures to confirm the normality of digital logic circuits compared to The match between the output signature and the predetermined test signature. or the difference confirms whether the circuit operates correctly.

Known test circuits are integrated into the same microprocessor or other component. located on the circuit module. However, the control signal for generating the test signal The code must be supplied externally to the module and must be supplied externally to the module and The second circuit output must be read and also processed external to the module. .

Additionally, known self-test circuits provide address or control information to the circuit to be tested. For testing the functionality of the entire microprocessor system, the not present. Testing the functionality of the entire microprocessor system by checking instructions, addresses and It requires the generation of test data and the verification of signals occurring throughout the system.

In another known device (European Patent Application No. 0135009), the main A microprocessor having a microprocessor and associated main memory. A control microprocessor with memory is installed for testing the processor system. main microprocessor, main memory and inspection equipment through the instruction unit errors and their types, as well as control microprograms. The processor processes the inspection column and other parts of the inspection equipment, the main microprocessor and the main memory. The control microprocessor and testing equipment are An interface circuit is provided for forming a connection with the input circuit. child The disadvantages of the known device are the necessary external wiring and the microprocessor to be tested. A complex control program that executes a complex inspection program contained in the main program of A microprocessor is required.

Furthermore, with complex microprocessor systems, reliable testing can be time consuming and costly. In particular, there are a large number of functions (instructions, operands) to be tested. Exists.

The object of the present invention is to Electronic assemblies with self-testing circuits that can quickly and reliably test even electronic assemblies. It is to provide.

To solve this problem, electronic assemblies of the type mentioned at the outset are claimed in the patent claims. The invention has the features set out in the characterizing part of claim 1 below. According to the invention in an advantageous manner According to the device, it is possible to use a pseudo-random digital signal as a test pattern. This allows for a more reliable inspection of the modules of the assembly. microprocessor By giving unique test patterns to each bus in the system separately, Optimal adaptation to the functions to be investigated is guaranteed. to generate a test pattern , an inherent test that works parts of the main program within the microprocessor in assembly. A self-testing microprocessor is not required, so that the self-testing circuitry It has great independence from Joule. For example, the test procedure described here is Simply for easy installation of the current supply during other test stages (aging, heating test) It can be executed more easily. For example, a test pattern generator as a shift register circuit. The realization of circuit technology itself is described in the literature “Semiconductor circuit technology” written by Tietze and Schienck. Known from Jutsu no, 5th edition, Springer Publishing, 1980, pp. 509-512. be.

Advantageous embodiments of the device according to the invention are listed in claim 2 of the patent claims. Ru.

According to claim 3, the inspection procedure proceeds in four steps that are processed one after another. Electronic assemblies with self-test circuits operate particularly advantageously if carried out. child In this case, the important buses for the module to be tested at each test stage are system test pattern. In this case, is there a simple way to control it? 'E function also control bus The memory in the memory module (ROM, RAM) can be inspected through A meaningful examination of a location can also be performed taking into account its immediate range.

The present invention will be explained with reference to the drawings. Figure 1 is an explanatory diagram of the inspection progress, Figure 2 is what should be inspected. Block circuit diagram of self-test circuit with module, Figure 3 shows test pattern generation The device itself is a diagram showing a known embodiment, and FIG. 4 shows an example of test data evaluation. This is a review to show.

In the explanatory diagram of FIG. 1, the order of test steps 1...4 is the same as the self-test circuit STS. The interaction between the module μP, ROM, and RAM to be tested in the electronic assembly of It is shown by the action. The first test stage involves a self-test after the electronic assembly is turned on. A self-test of the self-test circuit STS is performed, and in this self-test, the most Correct output of critical system functions, such as test patterns, is verified.

In the second testing stage, the processor module μP performs a pseudo-random instruction sequence, a pseudo-random Provides corresponding test patterns consisting of random operands and pseudo-random control signals. be provided. In the third test stage, the read module ROM is in a pseudo-random state in the embodiment. A signature chair is formed from its contents. Third inspection stage In the write/continue module RAM is a pseudo-instruction module that addresses memory ranges. Random addresses, pseudorandom data and pseudorandom data written within memory ranges. A test pattern consisting of random write/read cycles is used.

In Figure 2, the necessary elements of the self-test circuit STS are shown in the module μPSRO to be tested. M, is shown in conjunction with RAM. The $1 test pattern generator TMGI is a digital It is connected to the processor module μP via the data bus DB. in the same way The second test pattern generator TMG2 connects to the processor module via the control bus SB. It is connected to the μP. Data bus DB, address bus A, B and control bus The processor module μP is connected to the test data evaluation circuit TDA via the SB. ing. Here, in its simplest embodiment, it is a digital counting module. Another test pattern generator TMG3, which may be a The read module ROM is connected to the module ROM, and the read module ROM stores the data to be read. is similarly applied to the test data evaluation circuit TDA via the data bus DB. moreover, In the simplest case, a digital counter or a linear negative feedback shift register A fourth test pattern generator TMG4, which may be present, writes data via the address bus AB. It is connected to the write/read modules RA and M, and the write/read modules The read data is also sent to the RAM via the data bus DB (inspection data). It is given to the evaluation circuit TDA. The test pattern supply is thus carried out as shown in the diagram. In the example, the data bus DB, address bus AB and control bus SB are respectively multiple test pattern generators, possibly supplied with different test patterns This is done using A very wide range of test patterns can be applied to the processor module μP. required for. Therefore, a unique test pattern generator T for the data bus A separate test pattern generator TMG2 for MG1 and control bus is required. Ru. In this case, the test pattern for the data bus is the write/continue module R. It can also be used for data to be written to AM. For address bus AB According to the illustrated embodiment, the test pattern generated by the test pattern generator TM As shown by the dashed connection line between G2 and test pattern generator TMG4. It can also be used for addressing the write/output module RAM. It is generated by the test pattern generator TMG3.

FIG. 3 shows an embodiment of the test pattern generator which is known per se (for example from the literature). “Semiconductor Circuit Technology” by Tse/Schenck, 5th edition, Springer Publishing, x9so edition , pp. 509-512). Here, clock T is clocked Four flip-flops-modules F1...-F4 fed to input @C are connected in phase. connected back and forth. Flip-flops - outputs of modules Fl...-F4 State quantities X, . . . χ4 are generated at each end Q. The quantities x3 and χ1 are exclusive via the circuit EXO to the data input of the first flip-flop module F1. He was recently returned to Japan. The output terminal Q of the flip-flop circuit is connected to each subsequent flip-flop circuit. It is led to the input ends of the flop modules F2, F3, F4. Status g @ X.

...X4 and the flip-flop - state of the quantity y fed back to the module F1 The table will look like this: Here, the first state quantity is X, = 1, and the other state quantities are Xz + It is started from the fact that X3 + Xa - 0.

Thus, on each test pulse the information is shifted one position to the right. figure In the example shown, here the initial state is formed again after each 15 test pulses. It is recognized that the

To obtain a larger period, a correspondingly longer shift register must be used. Must be.

In Figure 4, on the right hand side, individual signatures are shown for each linear negative feedback shift register. LPSR and its output is routed through multiplexer MIJχ to another linear is fed to the negative feedback shift register LFSR, which in turn feeds the system An embodiment of the test data evaluation circuit TDA forming the signature is shown in detail. There is. Test results can thus be indicated in the form of this system signature.

international search report m--1^--Shuuichi' Per/DE 8B1005772 International Search Report DE 8800577

Claims (3)

[Claims] 1. Each test pattern is used as an inspection pattern for each module of the assembly to be inspected. Self-test circuit that generates internal test signals on the fly and also performs internal evaluation of result signals in which the self-test circuit uses a linear negative feedback to generate the result signature. Contains test data evaluation circuitry, including return shift registers, and electronic assembly. an electronic assembly including at least one microprocessor; There, The test signal is a pseudo-random digital signal, and The test pattern generator (TMG1...) that generates a unique test pattern performs self-testing. address bus (AB) and data bus (DB). and one test pattern generator for the control bus (SB). An electronic assembly characterized by: 2. One result signal for each module to be tested (uP, ROM, RAM) to a multiplexer (MUX) through a linear negative feedback shift register (LFSR). A multiplexer (M A claim characterized in that a system signature is formed on a terminal in (UX) The electronic assembly according to item 1. 3. In the first test stage, the self-test circuit performs a self-test after the assembly is turned on. In the test step 1, the processor (uP) performs a pseudo-random test on the data bus (DB). A test pattern sequence consisting of a program instruction sequence and a pseudo-random operand is supplied. A pseudo-random control signal is supplied to the control bus (SB), and the first test stage The read module (ROM) performs a pseudo-random address via the address bus (AB). The dress is supplied, a signature is formed from its contents, and a first inspection stage is carried out. The write/read module (RAM) uses an address to address a memory range. via the pseudo-random address for the response bus (AB) and the data bus (DB). Pseudo-random data is written to a memory range by by a sequence of test patterns consisting of pseudo-random read/write cycles achieved. 3. Electronic assembly according to claim 1 or 2, characterized in that it is inspected.