JPH0348979A - Parallel image processor - Google Patents

Abstract

PURPOSE:To minimize the deterioration of the execution processing speed of a parallel image processor by performing the local processes in parallel with each other and making a single image process module collect and distribute the data on other picture process modules for execution of a global process. CONSTITUTION:It is suppose that a partial image is already inputted to an input memory 6, and the statistic data on the image density of an arithmetic part 7 are outputted to an output memory 8 in parallel with each other. The statistic data are sent to a memory 6 of a master module 3 from the memory 8 based on the data collection state. The part 7 of the module 3 applies an arithmetic operation to the statistic data of the memory 6 and outputs a binary level to the memory 8. Then the binary level is transfered to the memories 6 of all modules 3, 4 and 5 from the memory 8 of the module 3 based on the data distribution state. Then the parts 7 of all modules 3 - 5 binarize the images of the memories 6 based on the binary level and output the binary images to the memories 8 in parallel with each other. Thus the execution processing speed is not substantially deteriorated.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a parallel image processing device, and particularly to a parallel image processing device that executes processing (for example, adaptive binarization processing) that includes an algorithm that cannot be processed in parallel as part of the processing. It relates to a processing device.

[Conventional technology]

Adaptation of objects 2 with a parallel image processing device that divides one screen image into equal partial screens and processes each image processing module (hereinafter simply referred to as a module) in parallel.
When attempting to perform value conversion, etc., it is necessary to refer to the processing results of each partial screen once during the process.

Conventionally, with this type of technology, when each module is finished to the point where it can process independently, for example, the 80286 CPU
There is a method in which an external host CPU, such as the It had been taken.

[Problem to be solved by the invention]

The above-mentioned conventional technology has the disadvantage that the processing speed of the entire apparatus is reduced because a host CPU, which is several times to several tens of times slower than the image processing module, is responsible for part of the processing.

[Means to solve the problem]

The parallel image processing device of the present invention includes an input bus that supplies input data, an input data memory that stores data obtained from the input bus, and an arithmetic unit that reads and writes data in the input data memory and performs arithmetic processing. In a conventional parallel image processing device configured by parallelizing a plurality of image processing modules each including an output data memory that stores calculation results obtained from the calculation section and an output bus from which the output data memory outputs data. , a data collection section that transfers data stored in the output sections of all modules to the input data memory of any one module; and a data distribution unit that performs memory transfer to the input data memory.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention, which is an image processing system in which a plurality of image processing modules are arranged in parallel.

In FIG. 1, the system consists of an input data bus 1, an output data bus 2, and a plurality of image processing modules 3.4.5, each image processing module having an input memory 6,
It consists of an arithmetic unit 7 that performs image processing and an output memory 8, and one of all the modules further has a data collection and distribution unit 9 that performs memory transfer, and this image processing module 3 is called a parent module.

FIG. 2 is a flowchart showing the principle of the present invention, which will be explained by taking adaptive binarization processing as an example of image processing.

Generally, an automatic threshold value determination method such as adaptive binarization processing includes a step S of performing various statistical processing on an image, a step S1 of determining a threshold value from the processing results, and a step of performing binarization using the threshold value. It can be decomposed into S.

Steps S, , S, can be performed in parallel by dividing the image, but step S2 requires reference to the processing results of each divided image, and is a process that cannot be performed in parallel. The effectiveness of the present invention for image processing involving such algorithms is that step S1, which can be processed independently by each image processing module (hereinafter simply referred to as a module) in charge of a partial screen, is processed in parallel. Then, by collecting the result data in one module, processing step S2 in one module, distributing the result to all modules, and processing step S3 in parallel, an external general-purpose C
There is no need to intervene in the PU and image processing, making it more efficient in terms of speed.

To explain this principle in more detail, see Section 3.4.5.
FIG. 6.7 shows a state fiber diagram when the parallel image processing device according to the present invention performs adaptive binarization processing.

FIG. 3 shows step SI, where it is assumed that a partial image has already been input to the input memory 6, and the calculation section 7 outputs statistical data of the density of the image to the output memory 8 in parallel.

FIG. 4 shows how data is collected, and the statistical data on all output memories 8 is transferred to the input memory 6 of the parent module 3.

FIG. 5 shows step S1, in which the calculation unit 7 of the parent module 3 performs calculations on the statistical data on the input memory 6, and outputs the resulting binary level to the output memory 8.

Figure 6 shows how data is distributed from the output memory 8 of the parent module 3 to the input memory 6 of all modules 3, 4.5.
Transfer value levels to memory.

FIG. 7 shows step S, all modules 3.4.
The arithmetic unit 7 of 5 binarizes the image on the same manual memory 6 according to the binary level on the input memory 6 and outputs the binary image to the output memory 8 in parallel.

A series of these processes is performed by the built-in programs of modules 3, 4, and 5, and although there is a small time lag due to memory transfer, etc., the effective processing speed hardly deteriorates compared to normal fully parallel processing.

〔Effect of the invention〕

As explained above, in image processing such as adaptive binarization performed by a parallel image processing device, local processing is performed in parallel, and global processing is performed in which one image processing module processes data from other image processing modules. Collection and distribution has the effect of minimizing the reduction in execution processing speed of a parallel image processing device compared to a method in which a normal CPU intervenes in image processing.

This is a transfer.

1...Input data bus, 2...Output data path, 3-5...Image processing module, 6
...Input memory, 7...Calculation section,
...output memory.

Claims (1)

[Claims] an input bus that supplies input data; an input data memory that stores input data obtained from the input bus; an arithmetic unit that reads and writes data in the input data memory to perform arithmetic processing; and an arithmetic processing result obtained from the arithmetic unit. In a conventional parallel image processing device configured by parallelizing a plurality of image processing modules each including an output data memory for storing data and an output bus for outputting data from the output data memory, the output data memory of all modules Data that transfers the above calculation result data to the input/output memory in the input of one module, or conversely, transfers the data from the output memory of one module to the input memory of all modules. A parallel image processing device characterized in that one module among all modules has a collection and delivery section.