JPH0348699B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frequency synthesizer, and more particularly, to a frequency synthesizer that uses a phase lock loop to accurately match the phase of an oscillator output signal to the phase of a reference signal.

2. Description of the Related Art Frequency synthesizers that synthesize output waves of a desired frequency from a specific frequency source through processes such as frequency division, frequency doubling, and mixing are widely used, for example, in communication systems. Conventionally, this frequency synthesizer utilizes a phase lock loop (PLL), which is a type of feedback control circuit. Next, a conventional example of such a frequency synthesizer will be described.

FIG. 1 is a block diagram showing a schematic configuration of a frequency synthesizer, which includes a phase comparator 2, a low-pass filter 4, a voltage controlled oscillator (VCO) 6, and a variable frequency divider 8. .

The phase comparator 2 is a device that detects the phase difference between two input signals, and its output side is connected to the input side of the low-pass filter 4. The low-pass filter 4 freely passes signals with frequencies lower than the cutoff frequency without attenuation, and provides large attenuation to signals with frequencies higher than the cutoff frequency. The output side of this low-pass filter 4 is connected to the input side of a voltage controlled oscillator 6. The voltage controlled oscillator 6 is an oscillator whose oscillation frequency is changed by a control voltage, and one signal line branched from the output side of the voltage controlled oscillator 6 is connected to the input side of the variable frequency divider 8. The variable frequency divider 8 achieves the function of dividing the signal frequency by an integer, and its output side is connected to one input side of the phase comparator 2.

That is, the frequency synthesizer shown in FIG. 1 consists of a phase lock loop in which a phase comparator 2, a low-pass filter 4, a voltage controlled oscillator 6, and a variable frequency divider 8 are connected to form a closed loop.

In such a frequency synthesizer, a reference signal having a reference frequency f _R and an output signal from a variable frequency divider 8 are input to the phase comparator 2 . A signal corresponding to the phase difference between these two signals is output from the phase comparator 2 and input to the low-pass filter 4. This low-pass filter 4 removes unnecessary frequency components, and the output frequency f ₀ of the voltage-controlled oscillator 6 is determined based on the output signal of the low-pass filter 4 . Further, the output signal from the voltage controlled oscillator 6 is input to the variable frequency divider 8, and the output signal whose frequency has changed according to the division ratio of the variable frequency divider 8 is supplied to the phase comparator 2, and the output signal whose frequency is is compared with the reference frequency f _R , and eventually a phase lock is performed to match the phases of the reference frequency f _R and the output frequency f ₀ .

Here, when the frequency division ratio in the variable frequency divider 8 is set to N, the output frequency f ₀ is f ₀ =N×f _R (1). Therefore, by changing N, any output frequency can be obtained with the frequency increment being _fR .

However, in such a phase lock loop configuration, even if a predetermined lock state is controlled, there is a slight phase fluctuation in the output signal of the voltage controlled oscillator 6, so that the reference frequency f _R and the variable frequency divider 8 A phase difference occurs between the output frequency and the output frequency, and a ripple voltage having a component of the reference frequency f _R appears in the output signal of the phase comparator 2. Therefore, unless the ripple voltage is suppressed by making the cutoff frequency of the low-pass filter 4 sufficiently smaller than the reference frequency f _R , unnecessary spurious will occur in the output signal of the voltage controlled oscillator 6. That is, in order to prevent spurious emissions that adversely affect communication, etc., it is necessary to lower the cutoff frequency. However, if the cutoff frequency is lowered, the delay time of the low-pass filter 4 becomes longer and the pull-in time becomes longer. As a result, there is a possibility that it may become impossible to realize the desired phase lock loop. In fact, it is known that the phase lock loop shown in FIG. 1 cannot simultaneously achieve the highly accurate frequency increment and relatively short pull-in time required of high frequency wireless communication devices.

Therefore, in order to realize small frequency increments and short pull-in times, a frequency synthesizer using a mixed number frequency division method has been devised, and the schematic configuration of this frequency synthesizer is shown in FIG. This frequency synthesizer includes a phase comparator 10, a summing point 12, a low-pass filter 14, a voltage controlled oscillator 16, and a variable frequency divider 1.
8, an accumulative adder 20 and a D/A converter 22.

In this case, the signal line through which the reference signal of the reference frequency f _R is transmitted branches into two, one of which is connected to the input side of the phase comparator 10, and the other is connected to the cumulative adder 20.
connected to the input side of the A summing point 12 is provided on the output side of the phase comparator 10 , and the output side of this summing point 12 is connected to the input side of a low-pass filter 14 .
The output side of the low-pass filter 14 is a voltage controlled oscillator 16.
One of two signal lines branched from the output side of the voltage controlled oscillator 16 is connected to the input side of the variable frequency divider 18. The frequency division ratio of the variable frequency divider 18 is N or N-1, and switching thereof is performed by a carry signal to be described later. The output side of the variable frequency divider 18 is the phase comparator 1.
Connected to 0.

On the other hand, the cumulative adder 20 sequentially adds the decimal values supplied every count cycle with a period T = 1/f _R (2) based on the reference signal, and the cumulative value is 1. If the value is exceeded, that is, if a carry occurs, the accumulated value is set to 0 and a carry signal is output. The output side of the cumulative adder 20 where a carry signal is generated is connected to the variable frequency divider 18, and the output side where a signal corresponding to the cumulative value is generated is connected to a D/A converter 22. Furthermore, the output side of the D/A converter 22 is connected to the summing point 12.

Here, the desired output frequency of the frequency synthesizer is f ₀ , and this output frequency f ₀ is the reference frequency
Let K be the quotient divided by f _R. That is, f ₀ /f _R = K …(3) Furthermore, the integer obtained by rounding up the decimal point of the quotient K is N
and N-K=F...(4).

Next, the operation of the frequency synthesizer configured as described above will be explained. Therefore, in order to explain using specific numerical values, f ₀ =9.9MHz (5) and f _R =1.0MHz (6) are set in advance. As a result, from equation (3), K=f ₀ /f _R =9.9/1.0=9.9...(7), and by rounding up the decimal part of K, N=10...(8). Furthermore, from equation (4), F=N-K=10-9.9=0.1...(9).

First, in the initial state, the cumulative value of the cumulative adder 20 is set to 0, and the frequency division ratio of the variable frequency divider 18 is set to 10. Then, the reference signal of the reference frequency f _R is input to the phase comparator 10 and the cumulative adder 20 . In the cumulative adder 20, F, ie, 0.1, is added in the first count cycle, resulting in a cumulative value of 0.1. Following this, 0.1 is added one after another in each new count cycle, and in the 10th count cycle, the cumulative value becomes 1.0 and a carry occurs. As a result, the carry signal input from the cumulative adder 20 to the variable frequency divider 18 causes the frequency division ratio of the variable frequency divider 18 to be N-1=9 (10). Then, in the 11th counting cycle, the cumulative value becomes 0.1 again. That is, among the 10 count cycles, the frequency division ratio in consecutive 9 count cycles is 10, and in the 10th count cycle following these 9 count cycles, the frequency division ratio is 9. Therefore, the average frequency division ratio is =10×9+9×1/10=9.9=K (11).

Generally, a carry occurs by adding F only once during the period T shown in equation (2) and performing this addition (1/F) times. That is, the number of count cycles within the time indicated by T×1/F=1/f _R ×F (12) is 1/F. Among these (1/F) count cycles, the frequency division ratio becomes N in [(1/F)-1] count cycles, and the frequency division ratio becomes N-1 in the last one count cycle. Therefore, the average frequency division ratio is =N[(1/F)-1]+(N-1)×1/1/F =N(1-F)+(N-1) =N-F...( 13) From equations (13) and (4), we get =N-F=K...(14). That is, if the system is in a phase-locked state, the output frequency f ₀ will be f ₀ =(N-F)×f _R (15). In this case, in [(1/F)-1] count cycles, the output frequency of the variable frequency divider 18 is (N-F)×f R /N, and (N-F)× _{f R /} N-f Since _R =f _R ×−F/N (16), the frequency is lower than the reference frequency f _R by f _R ×F/N. Therefore, the phase of the output signal of the variable frequency divider 18 is delayed little by little compared to the phase of _fR . The phase delay of this output signal accumulates one after another,
Since the frequency division ratio becomes N-1 every time shown in equation (12), it returns to the initial value. Here, the relationship of the phase difference between the output signal of the variable frequency divider 18 and the reference signal of the reference frequency f _R with respect to time is shown in FIG. That is, since such a periodically varying phase difference is generated, a stepped ripple voltage corresponding to the phase difference is generated in the output of the phase comparator 10. When this ripple voltage is transmitted to the voltage controlled oscillator 16, the voltage controlled oscillator 1
The output of 6 has a frequency f _R centered around the output frequency f ₀ .
A spurious signal that fluctuates at ×F intervals will be generated. Since this spurious has a harmful effect on communication systems and the like, it is necessary to prevent its occurrence.

Therefore, in this frequency synthesizer, a D/A converter 22 (see FIG. 2) is used to prevent the generation of spurious signals. That is, a signal corresponding to the cumulative value of the cumulative adder 20 is sent to the D/A converter 22.
3 to generate a signal corresponding to the waveform shown in FIG. 3, and this signal is inverted at addition point 12 and combined with the output signal of phase comparator 10, thereby suppressing the generation of the ripple voltage. ing.
However, as shown in FIG. 4, in reality, the characteristics of the output frequency with respect to the control voltage as an input signal to the voltage controlled oscillator 16 are non-linear, so it is inconvenient that the generation of spurious cannot be sufficiently prevented. There is.

The present invention has been made to overcome the above-mentioned disadvantages, and provides a frequency synthesizer that prevents the generation of harmful spurious signals and enables accurate phase locking by combining at least two phase lock loops. The purpose is to

To achieve the above object, the present invention provides a first phase comparator, a first low-pass filter, a first voltage controlled oscillator, and a frequency division ratio (integer) that can be controlled externally, and that the frequency division ratio a first phase lock loop including a first variable frequency divider with terminals that can increase or decrease by 1, a second phase comparator, a second low pass filter, a second voltage controlled oscillator and a frequency division ratio ( integer)
a second phase lock loop including a second variable frequency divider that can be externally controlled and has terminals that can increase or decrease its frequency division ratio by 1, and each of the first and second variable frequency dividers; Accumulating means for generating a signal for increasing or decreasing the frequency division ratio by 1, and accumulating data setting for setting accumulating data to be supplied to the accumulating means based on a reference frequency and a target output frequency. and means for connecting the output side of the second variable frequency divider to the first and second phase comparators, inputting the reference signal of the reference frequency to the second phase comparator, and The ripple of the first phase comparator is reduced by comparing the phases of the output signal of the first variable frequency divider and the output signal of the second variable frequency divider in the phase comparator, and The present invention is characterized in that it is configured to derive an output signal having the target output frequency from the voltage controlled oscillator.

Next, preferred embodiments of the frequency synthesizer according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 5 shows the basic configuration of a frequency synthesizer according to the present invention, and this frequency synthesizer includes an accumulation data setting means 30, an accumulation adder 31 as an accumulation means, and a first phase lock loop. 32a and second phase lock loop 32b
including. In this case, the first phase lock loop 32a
consists of a phase comparator 34a, a low-pass filter 36a, a voltage controlled oscillator 38a and a variable frequency divider 40a. On the other hand, the second phase lock loop 32b includes a phase comparator 34b, a low pass filter 36b, a voltage controlled oscillator 38b and a variable frequency divider 40b. Note that the cumulative adder 31 and the phase comparators 34a and 34
b, low-pass filters 36a, 36b, voltage-controlled oscillators 38a, 38b, and variable frequency dividers 40a, 40
The functions of each of b are basically the same as those used in the prior art.

In the first phase lock loop 32a, the output side of the phase comparator 34a is connected to the input side of a low pass filter 36a, and the output side of the low pass filter 36a is connected to the input side of a voltage controlled oscillator 38a. The signal line connected to the output side of the voltage controlled oscillator 38a branches into two, one of which is connected to one input side of the variable frequency divider 40a, and the output side of the variable frequency divider 40a is connected to the phase comparator 34a. connected to one input side of the

Moreover, in the second phase lock loop 32b,
A low-pass filter 36 is provided on the output side of the phase comparator 34b.
b, voltage controlled oscillator 38b and variable frequency divider 40
b are connected sequentially. And variable frequency divider 40b
The signal line connected to the output side is branched into two and connected to the input sides of phase comparators 34a and 34b.

Further, the accumulation data setting means 30 is connected to an accumulation adder 31, and the signal line connected to the output side of the accumulation adder 31 is branched into two, and a variable frequency divider 40 is connected to the accumulation data setting means 30.
a, 40b.

The frequency synthesizer according to the present invention is basically constructed as described above, and its operation and effects will be explained next.

Here, as in the case of the prior art, the desired output frequency of the output signal to be obtained by the frequency synthesizer is f ₀ , and this output frequency f ₀
Let K be the quotient obtained by dividing by the reference frequency f _R (see equation (3)). Furthermore, let N be an integer obtained by rounding up the decimal point of the quotient K, and let NK be F (see equation (4)). Note that F in this case is set by the accumulation data setting means 30, and a signal corresponding to F as the accumulation data is input to the accumulation adder 31.

Further, the variable frequency dividers 40a, 4 in the initial state
Let N be the frequency division ratio of each of 0b. That is, similar to the explanation of the prior art, if f ₀ = 9.9 MHz f _R = 1.0 MHz, then K = 9.9 N = 10 F = 0.1 ((5), (6), (7), (8 ) and equation (9)). Therefore, various waveforms and numerical values corresponding to such numerical values are shown in FIG. In this case, A is the reference frequency
A reference signal of f _R is shown, and B shows an output signal of the variable frequency divider 40b. Further, C indicates the phase difference between the signals A and B, D indicates the cumulative value of the cumulative adder 31, E indicates the frequency division ratio of the variable frequency dividers 40a and 40b, and G indicates the output signal of the variable frequency divider 40a. .

First, a reference signal A with a highly stable reference frequency f _R is sent to the phase comparator 3 using a high-stability crystal oscillator or the like.
4b and the cumulative adder 31. As a result, if the cumulative value is 0 in the initial state, F=0.1 is added to the cumulative adder 31 in one count cycle as shown by equation (2). Even in the second counting cycle following this
0.1 is added, making the cumulative value 0.2. Similarly, 0.1 is added for each count cycle,
A carry occurs during the 10th count cycle, and the cumulative value becomes 0. By inputting the carry signal at this time to the variable frequency dividers 40a, 40b, the frequency division ratio of each of these variable frequency dividers 40a, 40b is switched to N-1=9. In other words, from the 1st to the 9th count cycle, the frequency is divided by 10,
In the 10th count cycle, the frequency is divided by nine. Therefore, the average frequency division ratio is 9.9 as in equation (11). As a result, the output from the voltage controlled oscillator 38b of the second phase lock loop 32b passes through the variable frequency divider 40b, so that its average output frequency becomes ×f _R =9.9×f _R (17) . Further, in the output of the voltage controlled oscillator 38b, as in the case of the prior art described above, spurious waves are generated due to step-like ripples caused by the phase difference shown by C in FIG.

On the other hand, the operation of the first phase lock loop 32a is basically the same as that of the second phase lock loop 32b, but the output of the variable frequency divider 40b is supplied as a reference input to the phase comparator 34a. Therefore, if each of the first phase lock loop 32a and the second phase lock loop 32b is in a locked state, the phase of the output signal G of the variable frequency divider 40a is synchronized with the phase of the output signal B of the variable frequency divider 40b. Because there are
No step-like ripple occurs in the output of the phase comparator 34a. Therefore, since the low-pass filter 36a of the first phase lock loop 32a only needs to sufficiently suppress the component of the reference frequency _fR , its cutoff frequency can be set relatively high, and as a result, the desired short pull-in time can be obtained. is possible.

Moreover, in the second phase lock loop 32b,
The spurious component of the voltage controlled oscillator 38b is compressed to approximately 1/N by frequency division by the variable frequency divider 40b. Further, since phase fluctuations having relatively high frequency components mixed into the first phase lock loop 32a from the variable frequency divider 40b are sufficiently suppressed by the low-pass filter 36a, an output signal having a desired output frequency f ₀ is obtained. can be suitably generated.

In this embodiment, the accumulative adder 31 is employed as the accumulating means, and the variable frequency dividers 40a, 40
Although the frequency division ratio of b is configured to be changed, it is also possible to use an accumulative subtracter in place of the accumulative adder 31. That is, let N be the integer part of the quotient K obtained by dividing the desired output frequency f ₀ by the reference frequency f _R , let F be the decimal part, introduce this F into the cumulative subtracter, and subtract it for each counting cycle. Similar effects can be obtained by configuring the frequency division ratio of the variable frequency dividers 40a and 40b to be switched to N+1 when a downshift occurs.

According to the present invention, as described above, by combining two phase lock loops, it is possible to obtain a frequency synthesizer that suppresses the generation of harmful spurious signals and can perform phase lock with short pull-in time. The present invention has the advantage that it can be used in wireless communication systems that require accurate frequency resolution and frequency hopping at the same time.

Although the present invention has been described above with reference to preferred embodiments, the present invention is not limited to these embodiments, and various improvements and design changes can be made without departing from the gist of the present invention. Of course.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a frequency synthesizer using a phase lock loop according to the prior art, FIG. 2 is a block diagram showing the configuration of another frequency synthesizer according to the prior art, and FIG. An explanatory diagram showing the phase difference over time between the reference signal introduced into the phase comparator and the output signal from the variable frequency divider. Figure 4 shows the control characteristics showing the relationship between the control voltage and output frequency in the voltage controlled oscillator. An explanatory diagram of
FIG. 5 is a block diagram showing the configuration of a frequency synthesizer according to the present invention, and FIG. 6 shows signal waveforms, phase differences, cumulative values, and the like in the frequency synthesizer of FIG.
FIG. 3 is an explanatory diagram showing the relationship between frequency division ratios. 30... Accumulation data setting means, 31... Accumulation adder, 32a, 32b... Phase lock loop, 34
a, 34b... Phase comparator, 36a, 36b... Low pass filter, 38a, 38b... Voltage controlled oscillator, 4
0a, 40b...variable frequency divider.

Claims (1)

[Claims] 1. The first phase comparator, first low-pass filter, first voltage-controlled oscillator, and frequency division ratio (integer) can be controlled externally, and the frequency division ratio can be increased or decreased by 1. a first phase lock loop including a first variable frequency divider with terminals, a second phase comparator, a second low pass filter, a second voltage controlled oscillator and a frequency division ratio (an integer) externally connected to the phase lock loop; a second phase lock loop including a second variable frequency divider with terminals that can be controlled and whose frequency division ratio can be increased or decreased by 1; and a frequency division ratio of each of the first and second variable frequency dividers; an accumulating means for generating a signal for increasing or decreasing by 1, and an accumulating data setting means for setting accumulating data to be supplied to the accumulating means based on a reference frequency and a target output frequency. and connecting the output side of the second variable frequency divider to the first and second phase comparators, inputting the reference signal of the reference frequency to the second phase comparator, and performing the first phase comparison. Said first
The ripple of the first phase comparator is reduced by comparing the phases of the output signal of the variable frequency divider and the output signal of the second variable frequency divider, and the ripple of the first phase comparator is reduced. 1. A frequency synthesizer configured to derive an output signal having an output frequency. 2. In the synthesizer according to claim 1, the accumulation means includes an accumulation adder, and the accumulation data setting means divides the target output frequency by the reference frequency and rounds up the decimal part. A value obtained by subtracting the quotient from an integer is used as accumulation data, a frequency division ratio in the initial state of the first and second variable frequency dividers is used as the integer, and the accumulation data is used by the accumulative adder as the reference. A frequency synthesizer configured to switch the division ratios of the first and second variable frequency dividers to the integer minus 1 when a carry occurs during addition at every count cycle based on the frequency. 3. In the synthesizer according to claim 1, the accumulation means includes an accumulation subtracter, and the accumulation data setting means uses the decimal part of the quotient obtained by dividing the target output frequency by the reference frequency for accumulation. data, the division ratio in the initial state of the first and second variable frequency dividers is the integer part of the quotient, and the accumulation subtractor subtracts the accumulation data for each count cycle based on the reference frequency. A frequency synthesizer configured to switch the frequency division ratios of the first and second variable frequency dividers to the integer part +1 when a downgrade occurs.