JPH0348695B2 - - Google Patents

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to improvements in logic circuits using Schottky junction gate field effect transistors also constructed using GaAs.

[Background of the invention]

In addition to the conventional emitter-coupled logic circuit using bipolar transistors, a logic circuit using Schottky junction gate field effect transistors, which will be described below with reference to FIG. 1, can be considered. That is, two shotgun junction gate type field effect transistors (hereinafter simply referred to as transistors for simplicity) Q1 are constructed using GaAs.
and Q2. The drains D of these transistors Q1 and Q2 are connected to a power supply line L1 through loads M1 and M2, which are made up of, for example, resistors R1 and R2, respectively. Also, the sources S of transistors Q1 and Q2
are connected to each other and have a constant current source A common to them.
It is connected to the power line L2, which is a pair with the power line L1, through the power line L1. Further, a reference voltage source ER is connected between the gate G of the transistor Q2 and the power supply line L1. Further, a logic signal input line H is led out from the gate G of the transistor Q1. Furthermore, logic signal output lines T1 and T2 are led out from the drains D of the transistors Q1 and Q2, respectively. The above is the configuration of a logic circuit using a Schottky junction gate type field effect transistor, which can be considered from an emitter-coupled logic circuit using a conventional bipolar transistor. According to the logic circuit having such a configuration, the following effects can be obtained. That is, a power supply EM with a polarity such that the power supply line L1 side is positive is connected between the power supply lines L1 and L2, and a reference voltage source ER is connected to the gate G of the transistor Q2.
Negative reference voltage based on power line L1
In the state where V _rf is applied, a binary voltage V _iL of negative polarity, which is larger in absolute value than the value of the reference voltage V _rf , is applied to the input line H, with the power line L1 as a reference. A negative polarity voltage V _iH that takes "0" on the display and is smaller in absolute value than the value of the reference voltage V _rf
When a logical input signal V _io that takes "1" in a binary representation with meaning is given, when the logical input signal V _io is "0" in a binary representation (when the voltage V _iL ), Transistor Q2 remains conductive and transistor Q
1 remains non-conductive. Therefore, a zero voltage V _01H is obtained on the output line T1 with reference to the power supply line L1, and the output line T2
, a negative polarity voltage V _02L is applied with reference to the power supply line L1.
is obtained. In addition, the power supply EM is connected between the power supply lines L1 and L2 in the same manner as described above, and the reference voltage V _rf is connected to the gate G of the transistor Q2 in the same manner as described above.
is applied, and the logic input signal is applied to the input line H in the same way as described above.
When V _io is given, the logical input signal V _io is "1" in binary display.
(voltage V _iH ), transistor Q2 remains non-conductive, and transistor Q1 maintains conductive state. Therefore, a negative polarity voltage V _01L is obtained on the output line T1 with the power line L1 as a reference, and a zero voltage V _02H is obtained on the output line T2 with the power line L1 as a reference.
is obtained. From the above, the logic circuit shown in Fig. 1 is based on the logic input signal V _io , and when the logic input signal V _io is "0" in binary display, the output line T1 is given a meaning by the voltage V _01H . ``1'' is selected on the binary display, and the logical input signal V _io
When is "1" in the binary display, the logic output signal V ₀₁ is outputted as "0" in the binary display, which is given meaning by the voltage V _01L , and the logic input signal V _io is connected to the output line T2. When it is "0" in the binary display, it is "0" in the binary display with meaning given by the voltage V _02L , and the logic input signal V _io
It exhibits a logical function of outputting a logic output signal V ₀₂ that takes "1" in a binary representation, which is given meaning by the voltage V _02H , when it is "1" in a binary representation. By the way, in the case of the logic circuit shown in FIG. 1, the threshold voltages of transistors Q1 and Q2 are now V _th1 and V _th2 , respectively, and the sources S obtained between the gates G and sources S of transistors Q1 and Q2, respectively, are as follows. Let the gate-source voltages with reference to V _gs1 and V _gs2 be respectively V gs1 and V gs2, and further, the gate-drain voltages with drain D as a reference obtained between the gate G and drain D of transistors Q1 and Q2, respectively.
V _gd1 and V _gd2 , and the drain-source voltages obtained between the drains D and sources S of transistors Q1 and Q2, with the source S as a reference, are respectively
V _ds1 and V _ds2 , and the gate-drain junction capacitances between the gates G and drains D of transistors Q1 and Q2, respectively, are C _gd1 and C _gd2 , and the GaAs constituting transistors Q1 and Q2, respectively, are Let the dielectric constants of the semiconductor layers be ε ₁ and ε ₂ , respectively, furthermore, let the widths of the shottock junction gates of transistors Q1 and Q2 be respectively W ₁ and W ₂ , and let the electron charge be q, and furthermore, let transistor Q1 be The carrier densities in the active regions between the source and drain of the GaAs semiconductor layers constituting transistors Q1 and Q2 are respectively _Nd1 and _Nd2 , and the built-in voltage at the Schottky junction of transistors Q1 and Q2 is _Vbi1 , respectively. as well as
V _bi2 , and the lengths of the shotgun junction gates of transistors Q1 and Q2 are l _g1 and l _g2 , respectively. In such a case, (a) When the gate-drain voltages V _gd1 and V _gd2 are between the threshold voltages V _th1 and V _th2 , respectively, V _gd1 > V _th1 ...(1) V _gd2 > V _th2 ...( 1) If the relationship is as follows, (b) Gate-drain junction capacitance C _gd1 and C _gd2
are approximated, C _gd1 = (π/2)ε ₁・W ₁ + {1/(2・2 ^1/2 )} {(q・N _d1・ε ₁ ) / (V _bi1 −V _gd1 )} ^1/2・W ₁・l _g1 ...(2) C _gd2 = (π/2)ε ₂・W ₂ +{1/(2・2 ^1/2 )}{(q・N _d2・ε ₂ )/(V _bi2 −V _gd2 )} ^1/2・W ₂・l _g2 ……(2)′. (c) Gate-drain voltages V _gd1 and V _gd2 are between threshold voltages V _th1 and V _th2 , respectively, V _gd1 ≦V _th1 ...(3) V _gd2 ≦V _th2 ...(3) ′, (d) Gate-drain junction capacitances C _gd1 and C _gd2
However, by approximation, C _gd1 = ε ₁・W ₁・tan ^-1 {(V _bi1 −V _th1 )/(V _th1 −V _gd1 )} ^1/2 ……(4) C _gd2 = ε ₂・W ₂・tan ^-1 {(V _bi2 −V _th2 )/(V _th2 −V _gd2 )} ^1/2 ……(4)′. Note that the gate-source junction capacitances C _gd1 and C _gd2 shown in equations (2) and (2)′ and equations (4) and (4)′ above are derived as follows. There is. In other words, when looking at the model of transistors Q1 and Q2, the GaAs layer 1 that constitutes them is
As shown in FIGS. 3A and 3B, a gate electrode 3 is formed on an insulating substrate 2, and a gate electrode 3 is attached on the GaAs layer 1 so as to form a shot junction therebetween. , has a structure in which a source electrode 5 and a drain electrode 6 are respectively attached at both positions with the gate electrode 3 sandwiched therebetween, and GaAs
Let us consider the gate-drain junction capacitance C _gd1 of the transistor Q1 in the case where the layer 1 has a sufficiently high carrier density (N _d1 and N _d2 ) and the relationship expressed by the above-mentioned equation (1) is satisfied. In this case, the shot junction 4 below the gate electrode 3
Therefore, the depletion layer 7 that spreads between the gate electrode 3 and the source electrode 5 according to the voltage and spreads toward the insulating substrate 2 side does not reach the insulating substrate 2, as shown in FIG. 3A. Therefore, transistor Q1 is not in a pinch-off state. Therefore, the gate-drain junction capacitance C _gd1 in this case is the area A under the gate electrode 3 of the depletion layer 7.
Gate-drain capacitance C _gd1a with dielectric layer
, the gate-drain capacitance C _gd1b with the region B on the drain electrode side of the depletion layer 7 other than under the gate electrode 3 as a dielectric layer, and the gate electrode 3 of the depletion layer 7
It is given by the sum of the gate-drain capacitance C _gd1c with the region C on the source electrode side of the region other than the lower region as a dielectric layer, that is, C _gd1 =C _gd1a +C _gd1b +C _gd1c (C-1). Here, gate-drain junction capacitance C _gd1a ,
C _gd1b and C _gd1c are the above-mentioned region A of the depletion layer 7,
Let the charge amounts at B and C be H _a , H _b and
If H _c , then C _gd1a = (δH _a / δV _ds1 ) _Vgs1 = constant ... (D-a) C _gd1b = (δH _b / δV _ds1 ) _Vgs1 = constant ... (D-b) C _gd1c = ( δH _c /δV _ds1 ) _Vgs1 = constant ... (D-c). Therefore, by approximating and solving equation (D-a) assuming that the tip surface of the depletion layer 7 is flat in region A, as shown in FIG. 3A, we get C _gd1a = {1/( 2・2 ^1/2 )} [{q・N _d1・ε ₁ /(V
_bi −V _gd1 )} ^1/2 ]・W ₁・l _g1 ...(E-a). Furthermore, if we approximate and solve equation (D-b) assuming that the tip surface of the depletion layer 7 is an arcuate surface in region B, we get C _gd1b = (π/2)・ε ₁・W ₁ ……(E -b) becomes. Furthermore, the tip surface of the depletion layer 7 is
Assuming that region C is an arcuate surface, if we approximate and solve, we get C _gd1c =0...(E-c). Therefore, formula (C-1), (E-a), (E-b)
and (E-c), the above-mentioned equation (2) can be obtained. Furthermore, when considering the gate-drain junction capacitance C _{gd2 of transistor Q2 in the case where the relationship expressed by equation (1)' is described above, the gate-drain junction capacitance C gd2} of transistor Q2 is Since the above-mentioned equation (2)' is obtained according to the case described above regarding the total capacity C _gd1 , further detailed explanation will be omitted. Furthermore, let us consider the gate-drain junction capacitance C _gd1 of the transistor Q1 in the case where the relationship expressed by the above-mentioned equation (3) is satisfied. In this case, the depletion layer 7 has reached the insulating substrate 2, as shown in FIG. 3B, and the transistor Q1 is therefore in a pinch-off state. Therefore, the gate-drain junction capacitance C _gd1 in this case is the depletion layer 7 in the region on the drain electrode 6 side of the region other than under the gate electrode 3.
gate electrode 3 from the region where it reaches the insulating substrate 2
Gate-drain junction capacitance C _gd1d with region D looking at the source electrode 6 side end as a dielectric layer, and the region other than region D in the region of the depletion layer 7 on the drain electrode 6 side other than under the gate electrode 3 Gate-drain junction capacitance C _gd1e with region E as dielectric layer
, that is, C _gd1 = C _gd1d + C _gd1e ... (C-2). Here, the gate-drain junction capacitances C _gd1d and C _gd1e are: C _gd1d = (δH _d / δV _ds1 ) _Vgs1 = constant, assuming that the amount of charge in regions D and E is H _d and _He , respectively. F-d) C _gd1e = (δH _e /δV _ds1 ) _Vgs1 = constant ... (F-e) Given. For this reason, now let the thickness of GaAs layer 1 be a ₁ ,
Also, the length of the depletion layer 7 in contact with the insulating substrate 2 is
Assuming L ₁ , solve the equation (F-d): C _gd1d = (ε ₁・W ₁・a ₁ )/(2・L ₁ )
...(G-d). Also, by solving equation (F-e), we get C _gd1e = ε ₁・W ₁ tan ^-1 {(V _bi −V _th1 )/(V _th1 −V _gd1
)} ^1/2 + (ε ₁・W ₁・a ₁ )/(2・L ₁ )……(G-e)
becomes. Therefore, formula (C-2), (G-d) and (G-
By using the equation e), the above-mentioned equation (4) can be obtained. In addition, considering the gate-drain junction capacitance C gd2 of the transistor Q2 in the case where the relationship expressed by the above-mentioned equation (3)' is satisfied, the gate-drain junction capacitance C _gd2 of the transistor Q1 in the case where the above-mentioned equation (3) is obtained. According to the case described above for C _gd1 , the above-mentioned formula (4)' can be obtained, so further detailed explanation will be omitted. Above, equations (2) and (2)′, and (4) and
Gate-source junction capacitance shown in equation (4)′
It has become clear how C _gd1 and C _gd2 are derived. Here, the gate-drain junction capacitance C _gd1 has the values expressed by equations (2) and (2)′ above, respectively.
and C _gd2 , and the gate-drain junction capacitance having the values expressed by equations (4) and (4)′ above, respectively.
C _gd1 and C _gd2 are the gate-drain voltages V _gd1 and V _gd2 and the drain-source voltages V _ds1 and V _ds2
and the gate-source voltages V _gs1 and V _gs2 have the following relationship: V _gd1 = V _gs1 − V _ds1 ……(5) V _gd2 = V _gs2 − V _ds2 ……(5)′ Therefore, the gate-source voltage
The values of V _gs1 and V _gs2 both depend on the drain-source voltages V _ds1 and V _ds2 , respectively. However, the values of gate-drain junction capacitance C _gd1 and C _gd2 expressed by equations (2) and (2)′ are (4) and (4)′
This is larger than the gate-drain junction capacitances C _gd1 and C _gd2 expressed by the equations. This means that (a) the threshold voltage on the right side of equations (4) and (4)'
V _th1 and V _th2 , gate-drain voltage V _gd1
and V _gd2 have the relationship V _th1 =V _gd1 =0 ...(6) V _th2 =V _gd2 =0 ...(6)', then (6) and
V _th1 − ( _Vgs1 − V _ds1 )=0 (7) V _th2 − obtained by substituting the right sides of equations (5) and (5)′ into V gd1 and V _gd2 of equation (6)′, respectively. (V _gs2 −V _ds2 )=0 …(7)′, that is, V _ds1 =V _gs1 −V _th1 …(8) V _ds2 =V _gs2 −V _th2 …(8)′ When the relationship is
The values of the drain-to-drain junction capacitances C _gd1 and C _gd2 are: C _gd1 = (π/2)ε ₁・W ₁ ……(9) C _gd2 = (π/2)ε ₂・W ₂ ……(9)′ On the other hand, in equations (2) and (2)', the first term on the right side is
It is the same as the right-hand side of equations (9) and (9)′, and (2)
and (V _bi1 −
V _gd1 ) and (V _bi2 - V _gd2 ) are the gate-drain voltages V _gd1 and V _gd2 , respectively, which are built-in voltages due to the operation of transistors Q1 and Q2.
Since it does not take a value larger than V _bi1 and V _bi2 , it does not take a negative value, and therefore, the second term on the right side of equations (2) and (2)' takes a positive value. (b) Based on the actual situation, V _bi1 = V _bi2 = 0.8 (V) ... (10a) l _g1 = l _g2 = 1μm ... (10b) W ₁ = W ₂ = 10μm ... (10c) N _d1 = N _d2 = 1 × 10 ¹⁷ cm ^-3 ... (10d) V _th1 = V _th2 = 0.12 (V) ... (10e) V _bi1 = V _bi2 = 0.7V ... (10f) q = 1.602 × 10 ^-19 ( Clone) ... (10g) ε ₁ = ε ₂ = 12.6×8.84×10 ¹⁴ (F/cm)
...(10h) and the gate-drain junction capacitance C _gd1 and
C _gd2 , drain-source voltage V _ds1 and gate-source voltage V _ds2 , and V _gs1 and V _gs2
In general, C _gd , V _ds , and V _gs
When we calculated the relationship between the value of C _gd (fF) and the value of V _ds (V) using the value of V _gs (V) as a parameter, we obtained the results shown in Figure 2. It is clear from this point. In addition, Figure 2 shows the gate-source junction capacitance.
It also shows the relationship between the value of C _gs (fF) and the value of V _gs (V) with the value of V _gs (V) as a parameter when C _gs1 and C _gs2 are generally C _gs ,
The relationship between I _ds (mA) and the value of V _gs (V) is also shown, where I _ds is generally the current flowing through the drain D and source S of transistors Q1 and Q2. From the above, the gate-drain junction capacitance
C _gd1 and C _gd2 are obtained using equations (1) and (1)′ and equations (5) and (5)′ described above, V _ds1 <V _gs1 −V _th1 ...(11) V _ds2 When <V _gs2 −V _th2 ...(11)′, V _ds1 ≧V _gs1 − can be obtained using equations (3) and (3)′ and (5) and (5)′ described above. V _th1 ...(12) It has a larger value than the case where V _ds2 ≧V _gs2 −V _th2 ...(12)′. Note that when the gate-source junction capacitances between the gates G and sources S of transistors Q1 and Q2 are respectively C _gs1 and C _gs2 , (a) the gate-source voltages V _gs1 and V _gs2 are respectively When the threshold voltages V _th1 and V _th2 have the following relationship: V _gs1 > V _th1 ... (13) V _gs2 > V _th2 ... (13)', (b) Gate-source junction The capacitances C _gs1 and C _gs2 are
Approximately, C _gs1 = (π/2)ε ₁・W ₁ +{1/(2・2 ^1/2 )}{(
q・N _d1・ε ₁ )/(V _bi1 −V _gs1 )} ^1/2・W ₁・l _g1 …(14)
C _gs2 = (π/2)・ε2・W2+{1/(2・2 ^1/2 )}{
(q・N _d2・ε ₂ )/(V _bi2 −V _gs2 )} ^1/2・W ₂・l _g2 …(1
4)′, and (g) the gate-source voltages V _gs1 and V _gs2 are between the threshold voltages V _th1 and V _th2 , respectively, V _gs1 ≦V _th1 ……(15 ) V _gs2 ≦V _th2 ……(15)′ If (h) the gate-source junction capacitances C _gs1 and C _gs2 are
Approximately, C _gs1 = ε ₁・W ₁・tan ^-1 {(V _bi1 −V _th1 )/(V _th1
−V _gs1 )} ^1/2 ...(16) C _gs2 =ε ₂・W ₂・tan ^-1 {(V _bi2 −V _th2 )/(V _th2
−V _gs2 )} ^1/2 ……(16)′. However, the gate-source junction capacitances C _gs1 and C _gs2 having the values expressed by equations (14) and (14)′ and equations (16) and (16)′, respectively, are (11) and
The gate on the right side of equation (11)′ and equations (12) and (12)′
The respective values of source-to-source V _gs1 and V _gs2 do not have values that depend on drain-source voltages V _ds1 and V _ds2 , respectively. Note that the gate-source junction capacitances C _gs1 and C _gs2 shown in equations (14) and (14)′ and equations (16) and (16)′ above are based on the equations (2) and
Since the expressions (2)' and (4) and (4)' are derived in the same manner as when they are derived, further detailed explanation will be omitted. From the above, in the case of the logic circuit _shown in _FIG . (b) The gate-drain junction capacitances C _gd1 and C _gd2 between the gate G and the drain D do not depend on the drain-source voltages V _ds1 and V _ds2 between the gates S and the drain-source voltages V _ds1 and V ds2. _ds2 is gate G and source S
When looking at the gate-source voltages V _gs1 and V _gs2 and the threshold voltages V _th1 and V _th2 between the (12)', the drain-source voltage is larger in the former case than in the latter case.
Depends on V _ds1 and V _ds2 . By the way, in the case of the logic circuit shown in Fig. 1, the gains of transistors Q1 and Q2 are respectively
When G _a1 and G _a2 , the gate G and source S of transistors Q1 and Q2 are
Between, gate-drain junction capacitance C _gd1 and C _gd2
Large values of the mirror capacitances (1-G _a1 )C _gd1 and (1-G _a2 )C _gd2 are generated, which are (1-G _a1 ) and (1-G _a2 ) times larger, respectively. Therefore, the input capacitance seen from the gate G and power supply line L1 of transistors _Q1 and _Q2 is the parallel capacitance {C _{gs1 +} (1-G _a1 )
C _gd1 } and the parallel capacitance between gate-source capacitance C _gs2 and Miller capacitance (1-G _a2 ) C _gd2 {C _gs2 + (1-
G _a2 ) C _gd2 }. Therefore, in the case of the logic circuit shown in Fig. 1, the gate-drain junction capacitance C _gd1 is expressed as (11) and
When it has a large value, which occurs when the relationship of formula (11)' is satisfied, there is an extremely large input capacitance between the gates G of transistors Q1 and Q2 and the power supply line L1. Therefore, in the case of the logic circuit shown in Fig. 1, the gate-drain junction capacitance C _gd1 is expressed as (11) and
When the equation (11) has a large value as shown in equation (11), the above-mentioned logical function cannot be obtained at high speed.

[Object of the present invention]

Based on the above, the present invention seeks to propose a logic circuit using a novel Schottky junction gate type field effect transistor, which is free from the above-mentioned drawbacks.

[Means to solve the problem]

The logic circuit using the Schottky junction gate field effect transistor according to the present invention has an apparent first
Similar to the logic circuit shown in the figure, it has first and second Schottky junction gate field effect transistors constructed using GaAs, and the first and second Schottky junction gate field effect transistors are constructed using GaAs. Drains are connected to a first power supply line through first and second loads, respectively, and sources of the first and second Schottky junction gate type field effect transistors are connected to each other, It is connected to a second power supply line paired with the first power supply line through a constant current source common to them, and further connected to the gate of the second Schottky junction gate field effect transistor and the first power supply line. A reference voltage source is connected between the first and second Schottky junction gate field effect transistors, and a logic signal input line is led out from the gate of the first Schottky junction gate field effect transistor; A logic signal output line is led out from the drain of one or both of the field effect transistors. However, in the logic circuit using the Schottky junction gate type field effect transistor according to the present invention, in the logic circuit using the Schottky junction gate field effect transistor having such a configuration, the first and second Schottky junction gate type The threshold voltage of the field effect transistor is
V _th1 and V _th2 , and the gate voltage with respect to the source obtained between the gate and source of the first and second shotgun junction gate field effect transistors, respectively.
Let the source voltage be V _gs1 and V _gs2 , respectively,
Further, when the drain-source voltages obtained between the drains and sources of the first and second shotgun junction gate transistors with respect to the sources are V _ds1 and V _ds2 , respectively, the logic signal input line Regardless of whether the logic input signal supplied to the terminal takes either "1" or "0" in binary representation, the relationship of V _ds1 ≧V _gs1 −V _th1 V _ds2 ≧V _gs2 −V _th2 is satisfied. The values of the first and second loads, the value of the current flowing through the constant current source, and the value of the reference voltage obtained from the reference voltage source are selected.

【Example】

Next, an embodiment of a logic circuit using a shotgun junction gate field effect transistor according to the present invention will be described. The embodiment of the logic circuit using the Schottky junction gate field effect transistor according to the present _invention is apparently the logic circuit shown in FIG. Regardless of whether it is displayed as “1” or “0”, the above-mentioned relationship V _ds1 ≧V _gs1 −V _th1 ……(12) V _ds2 ≧V _gs2 −V _th2 ……(12)′ is satisfied. So, the resistance R1 as a load
and the values of R2 r ₁ and r ₂ , the current flowing through constant current source A
The value of I _s and the reference voltage obtained from the reference voltage source ER
Let the value of V _rf be V _th1 = V _th2 = V _th , and r ₁ = r ₂
= r, it has a value that satisfies the relationship: V _rf ≧1.5·r·I _s −V _th (20). Here, the value r of resistors R1 and R2, constant current source A
When the value of the current I _s flowing through the reference voltage source ER and the value of the reference voltage V _rf from the reference voltage source ER satisfy the relationship of equation (20), the logic input signal V _io is displayed as "1" and "0", the above-mentioned (12) and
The reason why the relationship in equation (12)' is satisfied is as follows. (b) When the logic input signal V _io takes "1" in binary display: Now, if the voltage of the logic input signal V _io in this case is the voltage V _ioH , then the voltage V _ioH is V ioH in operation. It is desirable to have a value expressed as _ioH =−V _rf +0.5·r·I _s (a). On the other hand, at this time, the source voltage of transistor Q1 is V _S1H , the drain voltage is V _d1H , and the gate voltage is V S1H .
If the source voltage is V _gs1H and the drain-source voltage is V _ds1H , then the source voltage at this time is
V _s1H has a value expressed as V _s1H =V _ioH −V _gs1H (b). Therefore, the source voltage V _s1H expressed by equation (b)
Using equation (a), when the values r ₁ and r ₂ of resistors R1 and R2 are r, V _s1H = −V _rf +0.5・r・I _s −V _gs1H ……(c) It has a value expressed as . Further, the drain-source voltage V _ds1H of the transistor Q1 has a value expressed as V _ds1H = V _d1H - V _s1H (d). On the other hand, the drain voltage of transistor Q1 V _d1H
has a value of V _d1H =−r·I _s (e). Therefore, the drain-source voltage V _ds1H expressed by equation (d) is calculated using equations (c) and (e): V _ds1H = −r・I _s −(−V _rf +0.5・r・I _s −V _gs1H ) =V _gs1H −1.5・r・I _s +V _rf ……(f) It has a value expressed as follows. Therefore, from equation (f), the following relationship is obtained: V _rf = V _ds1H −V _gs1H +1.5·r·I _s (g). Therefore, the threshold voltage of transistor Q1 is V _th1
Then, from the relationship V _rf ≧1.5・r・I _s −V _th1 ……(h), which corresponds to the above-mentioned formula (20), using formula (g), V _ds1H −V _gs1H +1 .5・r・I _s ≧1.5・r・I _s −V _th1 ……(i) relationship is obtained. Therefore, from equation (i), V The relationship _ds1H ≧V _gs1H −V _th1 ...(j) is obtained. Also, in this case, transistor Q2 is turned off, and transistors Q1 and Q2 are connected to each other, so the drain-source voltage of transistor Q2 is V _ds2H , the gate-source voltage is V _gs2H , and the threshold voltage is When V _th2 ,
The drain-source voltage V _ds2 is larger than the drain-source voltage V _ds1H described above. Therefore, the relationship V _ds2H ≧V _gs2H −V _th2 ……(k), which corresponds to the above-mentioned equation (12)′, is obtained. (b) When the logic input signal V _io takes "0" in binary display: In this case, if the gate-source voltage and drain-source voltage of transistor Q2 are V _gs2L and V _ds2L , respectively, then this Although the detailed explanation is omitted, the drain-source voltage V _ds2L when the logic input signal V _io is "1" in binary display
According _to the above-mentioned equation ( _{f )} when _taking Accordingly, the following relationship is obtained: V _ds2L −V _gs2L +r・I _s ≧1.5・r・I _s −V _th2 (m). Therefore, from equation (m), the relationship V _ds2L ≧V _gs2L −V _{th2 .} . . (m'), which corresponds to equation (12)' described above, can be obtained. Further, in this case, the transistor Q1 is turned off, and the transistors Q1 and Q2 are connected to each other, so the drain-source voltage of the transistor Q1 in this case is V _ds1L , the gate-source voltage is V _gs1L , When the threshold voltage is V _th1 , its drain-source voltage V _ds1L
is larger than the drain-source voltage V _ds2L described above. Therefore, the relationship V _ds1L ≧V _gs1L −V _th1 (n), which corresponds to the above-mentioned equation (12), is obtained. As described above, an embodiment of a logic circuit using a shotgun junction gate type field effect transistor according to the present invention has been clarified. According to the embodiment of the logic circuit using the shot junction gate field effect transistor according to the present invention, the values of the resistors R1 and R2, the constant current source A
When the value of the current I _s flowing through the reference voltage source ER and the value of the reference voltage V _rf from the reference voltage source ER satisfy the relationship of equation (20) described above, the logic input signal V _io is “1” in binary display. ” and “0”, the above-mentioned relationships (12) and (12)′ are satisfied, so
From the above, it can be seen that the gate-drain junction _capacitance C _gd1 and C _gd2 are
is shown in equations (9) and (9)′ mentioned above.
2) Exhibits small values of ε ₁ · W ₁ and (π/2) · ε ₂ · W ₂ or less. Therefore, the gates C of transistors Q1 and Q2
The input capacitance between the power supply line L1 and the power supply line L1 is sufficiently small. Therefore, according to the logic circuit using the shotgun junction gate type field effect transistor according to the present invention, even when the logic input signal V _io takes either "0" or "1" in binary display, the transistor The input capacitance seen between the gates G of Q1 and Q2 and the power supply line L1 is small, and therefore, the above-mentioned logic function can be obtained at high speed, which is a great feature. Incidentally, in the logic circuit shown in FIG. 1, based on the present invention, transistors Q1 and Q2 having the parameters shown in equations (10a) to (10h) mentioned above are used, and the power supply EM is set to 3.5V.
When the logic input signal V _io takes "1" in binary display, -
When the value is 1.02V and it takes "0" in the binary display, the resistor R1 is
and R2 have a value of r ₁ = r ₂ = 1.4KΩ, furthermore, as constant current source A, a current I _s flowing through it is 0.6 mA, and as reference voltage source ER, A reference voltage V _rf of 1.4V was used. In this case, the gate-drain junction capacitances C _gd1 and C _gd2 of transistors Q1 and Q2 are as follows: When the logic input signal V _io takes "1" in binary display, C _gd1 = 1.07 (fF) C _gd2 = 0.64 (fF), and the logic input signal
Even when V _io takes "0" in binary display, it is obtained with small values of C _gd1 = 0.59 (fF) and C _gd2 = 0.83 (fF), and the logical function is
In terms of response rise speed of the drain voltage seen through transistors Q1 and Q2, a high speed of 34 psec was obtained. On the other hand, in the apparently same logic circuit shown in FIG.
As, a reference voltage V _rf of 1.0V is used,
Therefore, in the same case as described above, except that the relationship of equation (20) described above is not satisfied, the gates of transistors Q1 and Q2
The basis of the present invention is that the drain-to-drain junction capacitances C _gd1 and C _gd2 are C _gd1 = 12.10 (fF) and C _gd2 = 0.75 (fF) when the logic input signal V _io takes "1" in binary representation. In addition, even when the logical input signal V _io takes "0" in binary representation, C _gd1 = 0.66 (fF) C _gd2 = 1.08 (fF), which is also true for the present invention. Similarly, the response rise speed of the drain voltage across transistors Q1 and Q2 is 56 ps compared to the case based on the present invention. , the speed was 1.65 times lower. Note that the above description merely shows one embodiment of the present invention, and various modifications and changes may be made without departing from the spirit of the present invention.

[Brief explanation of drawings]

FIG. 1 is a connection diagram showing an example of the configuration of a logic circuit using a shotgun junction gate type field effect transistor for explaining the background of the present invention and explaining the present invention. To help explain this, Figure 2 shows the gate-drain junction capacitance C _gs (fF), gate-source junction capacitance C _gs (fF), and drain-source voltage V _ds (V) of the transistor. - It is a characteristic curve diagram showing the relationship between the current I _ds (mA) flowing between the sources. FIG. 3 is a schematic diagram showing a model of a transistor for explaining the gate-drain junction capacitance of the transistor. Q1, Q2...transistor, L1, L2...
Power line, M1, M2...load, A...constant current source,
EA...Reference voltage source, H...Input line, T1, T2
...Output line.

Claims (1)

[Scope of Claims] 1. First and second Schottky junction gate field effect transistors are constructed using GaAs, and the drains of the first and second Schottky junction gate field effect transistors are connected to the first Schottky junction gate field effect transistor. 1st and 2nd
are connected to the first power supply line through respective loads, and the sources of the first and second shotgun junction gate type field effect transistors are connected to each other, and the sources of the first and second shotgun junction gate type field effect transistors are connected to each other through a constant current source common to them. 1st
a reference voltage source is connected between the gate of the second shotgun junction gate field effect transistor and the first power supply line; A logic signal input line is led out from the gate of the first Schottky junction gate field effect transistor, and a logic signal output line is led out from the drain of one or both of the first and second Schottky junction gate field effect transistors. In the derived logic circuit using the Schottky junction gate field effect transistor, the threshold voltages of the first and second Schottky junction gate field effect transistors are respectively
V _th1 and V _th2 , and the gate voltage with respect to the source obtained between the gate and source of the first and second shot-type junction gate field effect transistors, respectively.
Let the source-to-source voltages be V _gs1 and V _gs2 , respectively, and the drain-source voltages obtained between the drains and sources of the first and second shot-type junction gate field effect transistors with respect to the sources as a reference, respectively, are V gs1 and V gs2, respectively. _ds1 and V _ds2 , the gate-drain junction capacitances of the first and second shottock junction gate field effect transistors are C _gd1 and C _gd2 , respectively, and the first and second shottock junction gate field effect transistors are When the dielectric constants of the constituent GaAs are ε ₁ and ε ₂ , respectively, and the widths of the Schottky junction gates of the first and second Schottky junction gate field effect transistors are W ₁ and W ₂ , respectively, the logic signal input Regardless of whether the logic input signal supplied to the line is "1" or "0" in binary display, it satisfies the relationship: V _ds1 ≧V _gs1 −V _th1 V _ds2 ≧V _gs2 −V _th2 , and C The values of the first and second loads and the current flowing through the constant current source are adjusted to satisfy _gd1 < (π/2) ε ₁・W ₁ C _gd2 < (π/2) ε ₂・W ₂ . A logic circuit using a Schottky junction gate type field effect transistor, characterized in that a value and a value of a reference voltage obtained from the reference voltage source are selected.