JPH0347003B2 - - Google Patents
Info
- Publication number
- JPH0347003B2 JPH0347003B2 JP59203700A JP20370084A JPH0347003B2 JP H0347003 B2 JPH0347003 B2 JP H0347003B2 JP 59203700 A JP59203700 A JP 59203700A JP 20370084 A JP20370084 A JP 20370084A JP H0347003 B2 JPH0347003 B2 JP H0347003B2
- Authority
- JP
- Japan
- Prior art keywords
- amplifier
- input
- oscillation circuit
- terminal
- terminals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000010355 oscillation Effects 0.000 claims description 39
- 239000013078 crystal Substances 0.000 claims description 20
- 239000004065 semiconductor Substances 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 4
- 239000003990 capacitor Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Oscillators With Electromechanical Resonators (AREA)
- Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体集積回路特にマイクロコンピ
ユータの発振回路に関し、端子ピン数を可及的に
減少させようとするものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, particularly an oscillation circuit for a microcomputer, and is directed to reducing the number of terminal pins as much as possible.
１チツプマイクロコンピユータではクロツク発
振器は増幅器をチツプ（半導体基板）内に構成
し、水晶振動子又はCR素子は外付けする構成を
とつている。第２図ａは水晶発振回路の場合、同
図ｂはCR発振回路の場合で、１０，１２は増幅
器（奇数段からなり入、出力間では、インバー
タ）、１８，２０は端子ピンであり、これらは図
示のように接続される。CR発振回路の場合増幅
器１２はヒステリシスを持ち、水晶発振回路の場
合増幅器１０はヒステリシスを持たず代つて
1MΩ程度の抵抗１６で弱い負帰還がかかつてい
る。ｃ，ｄは所要部品を外付けした状態を示し、
ｃは水晶発振回路で２２はその水晶振動子、２
４，２６はコンデンサである。ｄはCR発振回路
で２８はその抵抗、３０はコンデンサである。
In a one-chip microcomputer, the clock oscillator has an amplifier built into the chip (semiconductor substrate), and the crystal resonator or CR element is attached externally. Figure 2a shows the case of a crystal oscillation circuit, and Figure 2b shows the case of a CR oscillation circuit, where 10 and 12 are amplifiers (consisting of an odd number of stages and are inverters between input and output), 18 and 20 are terminal pins, These are connected as shown. In the case of a CR oscillation circuit, the amplifier 12 has hysteresis, and in the case of a crystal oscillation circuit, the amplifier 10 does not have hysteresis.
A weak negative feedback is applied by the resistor 16 of about 1MΩ. c and d show the state in which the necessary parts are attached externally,
c is a crystal oscillation circuit, 22 is its crystal oscillator, 2
4 and 26 are capacitors. d is a CR oscillation circuit, 28 is its resistance, and 30 is a capacitor.
このように従来方式ではクロツク発振回路は端
子ピン２個を使用しており、既知のように集積回
路装置では端子ピンは１個でも少ないのが望まれ
るので、問題である。
As described above, in the conventional system, the clock oscillation circuit uses two terminal pins, which is a problem because, as is known, in integrated circuit devices, it is desirable to have as few as one terminal pin.
水晶発振回路では、水晶振動子は増幅器１０の
入、出力端間に接続されるので端子ピン２個使用
は避けられない。これに対しCR発振回路では増
幅器１２の入、出力端間に接続されるのは抵抗
で、コンデンサは入力端とグランド間に接続され
る。抵抗なら内蔵可能である。 In the crystal oscillation circuit, since the crystal resonator is connected between the input and output terminals of the amplifier 10, the use of two terminal pins is unavoidable. On the other hand, in the CR oscillation circuit, a resistor is connected between the input and output terminals of the amplifier 12, and a capacitor is connected between the input terminal and ground. A resistor can be built-in.
本発明はかゝる点に着目するものであつて、端
子ピンが１個で済む発振回路を提供しようとする
ものである。また水晶発振回路、CR発振回路な
どに必要に応じて切換可能にすることを他の目的
とする。 The present invention focuses on this point and aims to provide an oscillation circuit that requires only one terminal pin. Another purpose is to enable switching between crystal oscillation circuits, CR oscillation circuits, etc. as required.
本発明の半導体集積回路は、第１、第２の端子
と、水晶発振用増幅器及び該増幅器の入、出力端
子間に接続される帰還抵抗素子と、CR発振用増
幅器及び該増幅器の入、出力端子間に接続される
帰還抵抗素子と、入力又は出力データ用の増幅器
とが同一半導体基板に形成され、前記第１、第２
の端子と前記各増幅器間の配線パターンの選択的
変更により、水晶発振回路及びCR発振回路の一
方が構成され、水晶発振回路を形成するための配
線パターンは、前記第１、第２の端子間に前記水
晶発振用の増幅器及び帰還抵抗素子とを接続する
パターンであり、CR発振回路を形成するための
配線パターンは、前記第１の端子に前記CR発振
用の増幅器の入力を接続し、第２の端子に前記入
力又は出力用データ増幅器の入力端又は出力端を
接続するパターンであることを特徴とするもので
ある。
The semiconductor integrated circuit of the present invention includes a feedback resistance element connected between first and second terminals, a crystal oscillation amplifier, the input and output terminals of the amplifier, and a CR oscillation amplifier and the input and output terminals of the amplifier. A feedback resistance element connected between the terminals and an amplifier for input or output data are formed on the same semiconductor substrate, and the first and second
By selectively changing the wiring pattern between the terminal and each of the amplifiers, one of the crystal oscillation circuit and the CR oscillation circuit is configured, and the wiring pattern for forming the crystal oscillation circuit is between the first and second terminals. The wiring pattern for forming the CR oscillation circuit connects the input of the CR oscillation amplifier to the first terminal, and connects the input of the CR oscillation amplifier to the first terminal. This pattern is characterized in that the input terminal or output terminal of the input or output data amplifier is connected to the second terminal.
第１図で説明すると、本発明では図示のように
増幅器１０，１２，１４、抵抗１６，２８、端子
ピン１８，２０をチツプ即ち半導体基板に構成し
ておき、CR発振回路の場合はａの如くまた水晶
発振回路の場合はｂの如く結線する。即ちａの場
合は抵抗２８を増幅器１２の入、出力端間に接続
し、該増幅器の入力端は端子ピンに接続し、また
増幅器１４の入力端を端子ピン２０に接続する。
またｂの場合は抵抗１６を増幅器１０の入、出力
端間に接続し、該増幅器の入力端は端子ピン１８
に、出力端は端子ピン２０に接続し、その他は未
結線とする。ａ，ｂの切換えは配線用マスクパタ
ーンを変えることにより容易に実現できる。増幅
器１０，１２は前述のように入、出力端間で見れ
ばインバータとなつているものであり、そして増
幅器１２はヒステリシス特性を持つ。増幅器１４
はインバータである必要はなく通常の増幅器又は
バツフアでよい。増幅器１０の帰還抵抗１６は
1MΩ程度の高抵抗、増幅器１２の帰還抵抗即ち
CR素子の該Ｒは２〜5KΩの低抵抗である。 To explain with reference to FIG. 1, in the present invention, amplifiers 10, 12, 14, resistors 16, 28, and terminal pins 18, 20 are configured on a chip, that is, a semiconductor substrate, as shown in the figure. In the case of a crystal oscillation circuit, connect as shown in b. That is, in case a, the resistor 28 is connected between the input and output terminals of the amplifier 12, the input terminal of the amplifier is connected to the terminal pin, and the input terminal of the amplifier 14 is connected to the terminal pin 20.
In case b, the resistor 16 is connected between the input and output terminals of the amplifier 10, and the input terminal of the amplifier is connected to the terminal pin 18.
The output end is connected to the terminal pin 20, and the others are left unconnected. Switching between a and b can be easily achieved by changing the wiring mask pattern. As described above, the amplifiers 10 and 12 are inverters when viewed between the input and output terminals, and the amplifier 12 has hysteresis characteristics. Amplifier 14
does not need to be an inverter, but may be an ordinary amplifier or buffer. The feedback resistor 16 of the amplifier 10 is
High resistance of about 1MΩ, feedback resistance of amplifier 12, i.e.
The R of the CR element is a low resistance of 2 to 5KΩ.
第１図ａで端子ピン１８にコンデンサ３０即ち
CR素子のＣを接続すると第２図ｄと同じ回路構
成となり、CR発振回路が得られる。この場合外
付けするのはコンデンサ３０のみであるから、
こゝではＣ発振回路と呼ぶ。端子ピン２０はＣ発
振回路の場合は遊びになるので、これをマイクロ
コンピユータの他の端子例えばデータ端子とする
ことができる。入力データ用なら増幅器１４は図
示極性でよく、出力データ用なら逆極性にする。
つまり増幅器１４はレシーバ／トランスミツタの
機能を有する。 In FIG. 1a, a capacitor 30 or
When C of the CR element is connected, the circuit configuration becomes the same as that shown in FIG. 2d, and a CR oscillation circuit is obtained. In this case, only the capacitor 30 is externally connected, so
Here, it is called a C oscillation circuit. Since the terminal pin 20 is idle in the case of a C oscillation circuit, it can be used as another terminal of the microcomputer, such as a data terminal. If it is for input data, the amplifier 14 may have the polarity shown, and if it is for output data, it should have the opposite polarity.
That is, the amplifier 14 has a receiver/transmitter function.
第１図ｂで水晶振動子２２の両端を端子ピン１
８と２０に接続し、これらの端子ピンとグランド
との間にコンデンサ２４，２６を接続すると、第
２図ｃと同じになり、水晶発振回路が得られる。
この場合は端子ピンに余りは発生せず、データ入
出力などに利用はできない。 In Figure 1b, connect both ends of the crystal resonator 22 to terminal pin 1.
8 and 20, and connect capacitors 24 and 26 between these terminal pins and ground, the result is the same as that shown in FIG. 2c, and a crystal oscillation circuit is obtained.
In this case, no surplus is generated at the terminal pin, and it cannot be used for data input/output.
第１図に示すように増幅器１０，１２，２４、
及び抵抗１６，２８を予めチツプに形成しておけ
ば、第１図ａのＣ発振回路、第１図ｂの水晶発振
回路、それに図示しないが第１図ａで抵抗２８は
外付けする（２８は１２から切離し、別に抵抗を
１８，２０間に接続し、端子２０と１４との接続
は断ち、端子２０と１２の出力端を接続する）よ
うにしてCR発振回路を構成でき、融通性のある
回路構成とすることができる。勿論Ｃ発振回路と
する場合は第１図ａで増幅器１０及び抵抗１６を
除いて、増幅器１２，１４（場合により１４は省
略）、抵抗２８のみとしてよい。 As shown in FIG. 1, amplifiers 10, 12, 24,
If the resistors 16 and 28 are formed on the chip in advance, the C oscillation circuit shown in FIG. 1a, the crystal oscillation circuit shown in FIG. 1b, and the resistor 28 in FIG. is disconnected from 12, a separate resistor is connected between 18 and 20, the connection between terminals 20 and 14 is cut off, and the output ends of terminals 20 and 12 are connected. A certain circuit configuration can be used. Of course, in the case of using a C oscillation circuit, the amplifier 10 and resistor 16 may be removed in FIG.
以上詳細に説明したように本発明ではＣ発振回
路構成として端子ピンを１個節約することがで
き、実用上有効である。
As described above in detail, the present invention can save one terminal pin in the C oscillation circuit configuration, and is practically effective.
第１図は本発明を説明する回路図、第２図は従
来例を示す回路図である。
図面で１２はヒステリシスを持つ増幅器、２８
は抵抗、１８は端子ピン、３０はコンデンサ、１
０は水晶発振回路用の増幅器、１６はその抵抗で
ある。
FIG. 1 is a circuit diagram explaining the present invention, and FIG. 2 is a circuit diagram showing a conventional example. In the drawing, 12 is an amplifier with hysteresis, 28
is a resistor, 18 is a terminal pin, 30 is a capacitor, 1
0 is an amplifier for the crystal oscillation circuit, and 16 is its resistance.
Claims (1)
間に接続される帰還抵抗素子と、 CR発振用増幅器及び該増幅器の入、出力端子
間に接続される帰還抵抗素子と、 入力又は出力データ用の増幅器とが同一半導体
基板に形成され、前記第１、第２の端子と前記各
増幅器間の配線パターンの選択的変更により、水
晶発振回路及びCR発振回路の一方が構成され、 水晶発振回路を形成するための配線パターン
は、前記第１、第２の端子間に前記水晶発振用の
増幅器及び帰還抵抗素子とを接続するパターンで
あり、 CR発振回路を形成するための配線パターンは、
前記第１の端子に前記CR発振用の増幅器の入力
を接続し、第２の端子に前記入力又は出力用デー
タ増幅器の入力端又は出力端を接続するパターン
であることを特徴とする半導体集積回路。[Claims] 1. A feedback resistance element connected between the first and second terminals, a crystal oscillation amplifier and the input and output terminals of the amplifier, and a CR oscillation amplifier and the input and output terminals of the amplifier. A feedback resistor connected between the feedback resistor element and an amplifier for input or output data are formed on the same semiconductor substrate, and crystal oscillation is achieved by selectively changing the wiring pattern between the first and second terminals and each of the amplifiers. One of the circuit and the CR oscillation circuit is configured, and the wiring pattern for forming the crystal oscillation circuit is a pattern that connects the amplifier for crystal oscillation and the feedback resistance element between the first and second terminals. , The wiring pattern for forming the CR oscillation circuit is
A semiconductor integrated circuit characterized in that the pattern is such that the input of the CR oscillation amplifier is connected to the first terminal, and the input end or output end of the input or output data amplifier is connected to the second terminal. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20370084A JPS6181004A (en) | 1984-09-28 | 1984-09-28 | Oscillating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20370084A JPS6181004A (en) | 1984-09-28 | 1984-09-28 | Oscillating circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6181004A JPS6181004A (en) | 1986-04-24 |
| JPH0347003B2 true JPH0347003B2 (en) | 1991-07-18 |
Family
ID=16478398
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20370084A Granted JPS6181004A (en) | 1984-09-28 | 1984-09-28 | Oscillating circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6181004A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58219803A (en) * | 1982-06-14 | 1983-12-21 | Mitsubishi Electric Corp | Oscillating circuit |
-
1984
- 1984-09-28 JP JP20370084A patent/JPS6181004A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58219803A (en) * | 1982-06-14 | 1983-12-21 | Mitsubishi Electric Corp | Oscillating circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6181004A (en) | 1986-04-24 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |