JPH0346850A - Cell exchange device - Google Patents

Abstract

PURPOSE:To perform switching without an influence upon cells to the other output ports by receiving cells distributed by destinations to multiplex them again with each destination as the unit by an output stage cell exchange switch module and distributing them to respective output ports thereafter. CONSTITUTION:Respective cells of input signals (a) to (d) are subjected to time division by a cell multiplexing circuit 7 and cells to be directed to prescribed output ports are selected and outputted. These signals (f) to (i) are supplied to storage circuits 10a to 10d provided for individual input ports in an output stage cell exchange switch module 70 and are temporarily buffered, and outputs are multiplexed by an output stage cell multiplexing circuit 12. Output stage cell selecting circuits 13a to 13d allow only cells, which are assigned to outgoing lines (k) connected to them, to pass through address filters, and they are converted from the speed of time-division multiplexed cells to the speed of output ports by corresponding speed converting circuits 14a to 14d and are outputted from pertinent output ports 5.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a common division type cell switching device that divides various information such as voice, data, and images into blocks called cells and exchanges them at high speed.

[Conventional technology]

Figure 5 shows, for example, the IEEE Journal on Selected Areas of Communication.
FIG. 2 is a block diagram illustrating a conventional cell switching device as shown in pages 1373 to 380 of Vol. 5AC-4, No. 8 (published November 1986) of "Areasin Communications". In the figure, Ia and Ib are cells consisting of a header part and a data part, and 2 is this cell 1 (
3 is a cell switching device that switches the cell 1 input to input boat 2, and 4 is a 2×2 space switch that constitutes this cell switching device 3. The unit switch 5 is an output port of the cell switching device 3. Note that the above-mentioned document describes a Banyan network that performs high-speed switching by directly referring to the header information of cell 1 in hardware, and in that paper, the name "packet" is used instead of the name "cell." Both cells and packets represent the same thing in that they block media information and add a header containing destination information. However, the difference is that, in general, the length of one block of a packet is treated as variable, but in a cell, it is treated as a fixed length according to international standards. In asynchronous transfer mode (ATM) communication, which transmits and exchanges at high speed,
Since the term "cell" is used, the term "cell" will be used instead of "packet" in the following explanation of the conventional example. Next, the operation will be explained. In Figure 5, a plurality of 2
The cell switching device 3 consisting of the ×2 unit switch 4 is configured to select the corresponding output port 5 according to the bit arrangement of the header portion of each cell 1. For example, the unit switches 4 arranged in the first row on the left in the figure connect the input port of the unit switch 4 to the upper output port if the first bit of the header section of cell 1 is 0''', and ”, it is connected to the lower output port. Similarly, the unit switches 4 arranged in the second column on the left select the output port according to the second bit of the header section of cell 1. By lining up the switches 4 and interconnecting them as shown in Figure 5, you can express the number of the output port 5 at the final stage in binary and add it to the header of the cell 10, and from which input port 2 the input can be sent. Even if cell 1 is the desired output port 5
reach.

[Problem to be solved by the invention]

Since the conventional cell switching device is configured as described above, there is a problem that blocking (collision) will occur if cells 1a and 1b aiming at the same output port 5 are input to the input port 2 at the same time. In order to solve this problem, a method has been proposed in which a buffer memory is provided in the input section or inside the unit switch 4, but when cells to a certain output port 5 are concentrated, the buffer memory becomes full. , there was a problem that the cell l to other output ports 5 was also blocked. This invention was made to solve the above problems, and allows switching without causing blocking, and even if cells are concentrated on one output port, it does not affect cells going to other output ports. The purpose is to obtain a cell switching device.

[Means to solve the problem]

The cell switching device according to the present invention includes an input stage cell multiplexing means for time-division multiplexing each human-powered cell, and a cell destined for a predetermined output port gel loop from the output signal of the input stage cell multiplexing means. an input-stage cell exchange switch module having input-stage cell selection means; a space switch for spatially switching cells output from the previous-stage cell selection means; a storage means for writing cells output from the space switch; A storage control means for managing and storing addresses of cells stored in a storage means for each destination, monitoring their remaining storage capacity, and preferentially reading out cells of destinations having a large remaining storage capacity, and reading from the storage means. one or more stages comprising an output stage cell multiplexing means for multiplexing the output stage cells; and an output stage cell selection means for selecting and passing cells destined for a predetermined destination from the output signal of the output stage cell multiplexing means. This device includes an output stage cell exchange switch module and a cell output stage module having speed converting means for converting the speed of time-division multiplexed cells to the speed of an output port.

[Effect]

The cell switching device in this invention once multiplexes the cells that have arrived at the input boat by the input stage cell multiplexing means in the input stage cell exchange switch module, and then
The output stage cell exchange switch module which receives this output after sorting by address filter by the input stage cell selection means preferentially writes the cells into the storage means with a small amount of reserved cells under the control of the storage control means. , cells read from each storage means are multiplexed again in units of destinations by the cell multiplexing means, and then distributed toward each output port by an address filter by the output stage cell selection means, To realize a cell switching device which reduces the probability of cells being discarded and can perform switching without affecting cells to other output ports even if cells are concentrated in one output port.

【Example】

An embodiment according to the present invention will be described below with reference to the drawings. In FIG. 1, 3 is a cell switching device, 2 is an output port of this cell switching device 3, and 5 is an output port of this cell switching device. Reference numerals 60 to 63 designate input stage cell exchange switch modules which are arranged for each of the input boats 2 divided into a plurality of groups and exchange each input cell. Reference numerals 70 to 73 designate output stage cell exchange switch modules that exchange cells sent out from the input stage cell exchange switch modules 60 to 63 and destined for a specific output port gel loop. 80-83 are cell output stage modules connected to the output stage cell exchange switch modules 70-73. The cell exchange device 3 includes input stage cell exchange switch modules 60-63, output stage cell exchange switch modules 70-73, and cell output stage modules 80-83. Further, 7 is an input stage cell multiplexing means (input stage cell multiplexing circuit) for time-division multiplexing cells, and 8a to 8d (8e to
8h) is an input stage cell selection means (input stage cell selection circuit) which selects and distributes cells destined for a plurality of groups through a plurality of output ports from the output signal of the input stage cell multiplexing circuit 7 through an address filter. be. The input stage cell exchange switch modules 60 to 63 include the input stage cell multiplexing circuit 7 and input stage cell selection circuits 8a to 8d. Here, FIG. 2 shows the output stage cell exchange switch module 7.
0 to 73, for example, a block diagram showing the configuration of a cell exchange switch module 70. In FIGS. 1 and 2, 4 indicates input stage cell exchange switch modules 60 to 63.
In order to equalize the amount of cells reserved between storage means (memory circuits) 10a to 10d (10e to IOh), which will be described later, for cells outputted from the input stage cell selection circuit and destined for a specific output port gel loop, This is a space switch that connects storage circuits 1°a to 10d (10e to 10h) with a small amount of storage. 9a to 9d (9e to 9h) are header processing means (header processing circuits) that read, analyze and output the cell destination, and 108 to 1od (1oe to 10h) are output from the header processing circuits 9a to 9d (9e to 9h). In the above-mentioned memory circuit, when a write address is specified, a cell to be stored can be stored at that address, and when a read address is specified, the stored cell can be read out regardless of the order in which it was written. 11 indicates this memory circuit 10a to 10d (], Oe to
10h) is a storage control means (storage control circuit) that controls reading and writing. In this storage control circuit 11, 16 is a storage circuit 10.
An address exchange unit (address exchange circuit) that distributes the address of the cell written by a to 10d to each output port gel loop (hereinafter referred to as an outgoing line) while referring to the header processing circuits 9a to 9d; A first-in, first-out (FIFO) format address storage unit for outgoing lines (outgoing line corresponding address FIFO) that allows writing to be performed on a first-come, first-served basis for each outgoing line; a read right granting unit (read right granting circuit) for permitting reading; 15 is each memory circuit 10a;
This is a counter for each storage circuit that manages the cell reservation amount of ~10d. 19a to 19d (19e to 19h) are memory circuits 1
When a cell is read from 0a to 10d, the read address is managed and held as a free address, and the memory circuit 10
This is free address management means (free address management circuit) that provides a write address when a new cell arrives at a to 10d. 12 is a memory circuit 10a to 10d (10e to 10h)
13a to 13d are output stage cell multiplexing means (output stage cell multiplexing circuit) for multiplexing the cells read out from each other;
(13e to 13h) are output stage cell selections in which out of the output signals of the output stage cell multiplexing circuit 12, cells destined for a particular group in a particular output port group are selected by an address filter, distributed and passed through. means (output stage cell selection circuit). The output stage cell exchange switch modules 70 to 73 include the space switch 4, header processing circuits 9a to 9d (9e to 9h), storage circuits 10a to 10d (10e to 10h), storage control circuit 11, and free address management. Circuits 19a to 19d (19
e to 19h), output stage cell multiplexing circuit 12, and output stage cell selection circuit 13a to 13b (13e to 13h)
Equipped with. Further, 14a to 14d (14e to 14h) are connected to the output stage cell selection circuits 13a to 13d (13e to 13h) of the output stage cell exchange modules 70 to 73,
It is a speed conversion means (speed conversion circuit) that converts the speed of a time-division multiplexed cell to the speed of an output boat, and the cell output stage modules 80 to 83 are connected to the speed conversion circuits 14a to 14a.
14d (14e to 14h). Next, the operation will be explained. Here, the cells have a fixed length, and the arrival of input cells is random. It is assumed that the cell input phase is adjusted before being input to the input boat 2 of ~It5, and the cell power from all input boats 2 is supplied with the same cell phase. First, the operation of the input stage cell exchange switch modules 60 to 63 will be explained based on FIG. 3 using the input stage cell exchange switch module 60 as an example. Input signal a shown in FIG.
-d are time-divided by a cell multiplexing circuit 7 and multiplexed into a multiplexed signal e shown in FIG. This multiplexed signal e is sent to the cell header by the input stage cell selection circuits 8a to 8d (8e to 8h) corresponding to the output ports of the input stage cell exchange switch modules 60 to 63. 1 address is detected, and a cell destined for a predetermined output port is selected and output, as shown by signals f and p in FIG. 3, for example. In FIG. 3, the cell whose first address is "1" is sent as a signal f by the input stage cell selection circuit 8a, and the cell whose first address is "2°" is sent as a signal p by the input stage cell selection circuit 8b. Here, multiplexing is performed at a speed that is the number of ports times the link speed of input port 2, and for example, multiplexing is performed in synchronized time slots in cell units as shown in Figure 3. A time slot without an input cell is assigned as an empty slot so that the first address in the header does not correspond to any output port.As described above, the first input stage cell exchange switch module 60 ~63, the cells input at the link speed are switched according to the first address in the header section, and are sent out in bursts to the first stage output port at the multiplexed speed.Next, , output stage cell exchange switch modules 70 to 73
The operation will be explained by taking the output stage cell exchange switch module 70 as an example. Here, among the outputs of the input stage cell exchange switch modules 60 to 63, four signals inputted to the output stage cell exchange switch module 70 are respectively referred to as f, g, h, and i. In the signal f-f, cells are sent out in bursts on the signal line at a multiplexed speed, and the number of cells on the four signals varies. Therefore, these signals f-i are stored in the memory circuit 1 provided for each input store in the output stage cell exchange switch module 70.
After being supplied to 0a to 10d and buffered by − degrees, the output is multiplexed in the output stage cell multiplexing circuit 12. Here, if the arrival of input cells is uniform both in time and space, the speed of the output signal j of the output stage cell multiplexing circuit 12 is equal to the number of ports of the input link speed of the output stage cell exchange switch module 70. It is considered that the cells input to the output stage cell exchange switch module 70 can be multiplexed without being discarded, provided that the number is at least twice as large. However, since the actual arrival of cells varies both temporally and spatially, it is necessary to buffer cells once in the memory circuits 10a to 10d to absorb cell overflow. At this time, the space switch 4 refers to the amount of reserved cells in each of the memory circuits 10a to 10d, and connects cells preferentially to the memory circuit with a smaller amount of reserved cells, so that the amount of reserved cells among the memory circuits 10a to 10d is as uniform as possible. I will make it happen. That is, the space switch 4 is connected to the storage circuit side counter 15 in the storage control circuit 11.
, if m cells arrive at the same time, m memory circuits 10a to 10 with the least amount of reserved cells are
Select and connect d, and write the arrived cell to it. At that time, the cells output from the space switch 4 are sent to a predetermined storage circuit 10 via the corresponding header processing circuits 9a to 9d.
a-10d, the header processing circuits 9a to 9d analyze the destination of the cell and send the corresponding one out of 1 and n to the address exchange circuit 16 of the storage control circuit 11. Furthermore, when the cell is stored in the memory circuits 10a-10d,
From the corresponding free address management circuits 19a to 19d, the address storing the cell is determined by the address exchange circuit 16.
sent to. The address exchange circuit 16 converts this address into
The outgoing line kz determined by the header processing circuits 9a to 9d
Outgoing line corresponding address FIFOI7a associated with n
~17d. The storage control circuit 11 has a function of not only reading cells addressed to the same output line when reading cells, but also preventing the order of cells from being reversed. Specifically, when the read right granting circuit 18 stores a cell in the memory circuits 10a to 10d, its address is output 1. 'fi k-n Address FIFO 17a ~
17d, a read address is given to the memory circuits 10a to 10d within a range where the subsequent output stage cell multiplexing circuit 12 can multiplex the outputs from all the memory circuits 10a to 10d, and the cells are sent out. At this time, the memory circuit side counter 1
5 counts and manages the amount of reserved cells for each of the memory circuits 10a to 10d. Various methods can be considered for controlling reading of the memory circuits 10a to 10d. In the case where output stage cell exchange switch modules are connected in multiple stages, for example, in the output stage cell exchange switch module arranged in the intermediate stage, if the remaining storage capacity of the outgoing line corresponding address FIFO 17a-17d is above a certain value. For the outgoing line, N cells (N is an integer of 2 or more) are read out continuously, and for other outgoing lines, n cells (n is 1 or 0) are read out and multiplexed. Compare the methods or the amount of cells addressed to each other's outgoing lines,
Possible methods include reading out N cells in succession for the outgoing line with the most remaining capacity, and reading out and multiplexing n cells for the other outgoing lines. Even so, for an outgoing line with many cells, more cells will be read out than for an outgoing line with fewer cells. At this time, it is necessary to avoid a method in which reading is stopped for outgoing lines with fewer cells as destinations and the delay time increases beyond a certain value. In addition, when the output stage cell exchange switch modules 70 to 73 shown in FIG. will be held. Therefore, such an output stage cell exchange switch module 70~
In 73, in order to prevent overflow, it is necessary to uniformly read out each memory circuit 10a to lOd. Therefore, the output stage cell exchange switch module 70
The readout turret providing circuit 18 73 performs control to read cells addressed to each outgoing line in the order of outgoing lines. The following description will be made assuming an intermediate stage output stage cell exchange switch module in which there is also an output stage cell exchange switch module downstream of the output stage cell exchange switch module 70 shown in FIG. In addition, as a method, if the remaining capacity on the destination outgoing line side of the cell exceeds 4 (equivalent to the number of input boats), 2
A method of reading out four or fewer cells in succession, and reading out one or zero cells for multiplexing when there are four or less cells will be considered and explained with reference to the timing diagram of FIG. Assume that the cell string shown in FIG. 4 is input as the signal f-i. Signal g shows a case in which nine consecutive cells from the input stage cell exchange switch module 61 arrive at the outgoing line in a concentrated manner toward E, m, and n. To the outgoing line,
Outgoing line corresponding address FIFO for each of l, m, and n
corresponds to 17a, 17b, 17c, and 17d. On the 1st day of the read right granting circuit, each outgoing line corresponding address F
The number of accumulated cell addresses in IF017a to 17d is monitored, and first, the number of cell addresses stored in IF017a to 17d is monitored.
When the first cell address is stored in 17d,
The readout gate of the outgoing line corresponding address FlFO17a addressed to the outgoing line is opened and the address is stored in the corresponding memory circuits 10a to 1.
0d, and one cell read from the address is supplied to the output stage cell multiplexing circuit 12 to start multiplexing. Multiplexing is performed using the outgoing line corresponding address FIFOs 17a and 17.
b, 17c, and 17d in the order of cell units, and if there is no stored cell address, the next outgoing line corresponding address is immediately read out from the FIFO and multiplexing is started. The first cell is the cell addressed to the outgoing line, and is the first cell for signal f (hereinafter, the first cell for signal r is called the Fl cell. The same applies to other cells). First, an address is taken out from the outgoing line corresponding address PIFO 17a, and using this address, the memory circuit 10
Cells are read from a and sent to the output stage cell multiplexing circuit 12 where they are multiplexed. When the multiplexing of this cell is completed, the next line is out! The address is extracted from the destination outgoing line corresponding address PIFO 17b, and the G2 cell is multiplexed. Next, it is the turn of the outgoing line corresponding address FlFO17c for the outgoing line m, but since it is empty, it immediately becomes the turn for the outgoing line n, the address is taken out from the outgoing line corresponding address PIFO17d, and the G
3 cells are multiplexed. Next, it's the turn to address the outgoing line, so G
One cell is multiplexed, and then 11 cells are multiplexed on the outgoing line l, 66 cells are multiplexed on the outgoing line m, and 07 cells are multiplexed on the outgoing line n. Next, it is the outgoing line's turn, but since the number of accumulated cell addresses in the outgoing line corresponding address FIF○17a is 5, two addresses are read out consecutively.
Cells H1 and G4 are multiplexed in succession. Below, H2,
H3, G5, 09F3. H5, F2. H4, +2. G8
．． F4. G10 is multiplexed in the order of output stage cell selection circuits 13a to 13 as the multiplexed signal j shown in FIG.
sent to d. The output stage cell selection circuits 13a to 13d select the output stage cell selection circuit 13a among the cells received by the signal j.
Only cells addressed to outgoing line k connected to ~13d are passed through the address filter. The cells distributed to each output line k-n in this manner are shown as signals k-n in FIG. This signal k-n is sent to the cell output stage module 80, and the corresponding speed conversion circuit 14a-
14d, the speed of the time-division multiplexed cell is converted to the speed of the output port, and the speed is output from the corresponding output port 5. As described above, the output stage cell exchange switch module 70
Now, the output line corresponding address FIFO of the storage control circuit 11
I7a-17d enables address management of the memory circuits 10a-10d and allows cells to be temporarily stored. Generally, the total number of cells supplied by the signal lines input to the output stage cell exchange switch modules 70 to 71 is, on average, equal to the input link speed times the number of input ports, provided there is no temporal or spatial bias. Therefore, it is considered that the total number of cells that can be multiplexed on the multiplexed signal j of the output stage cell exchange switch modules 70 to 73 is about the same or smaller than the total number of cells. Memory circuits 10a-10d (10e-1
The increase/decrease in the remaining cell storage capacity of 0h) depends on the number of arriving cells over time.
Since the memory circuits 10a to 10d (1
0e to 10h) to absorb temporal fluctuations and reduce cell discard. In addition, the memory circuits 10a to 10d (10e to 10h) of the output stage cell exchange switch modules 70 to 73 write at a multiplexed high speed even when multiple cells arrive at the same time, and the output line link speed Since the memory circuits 10 a to 10 d (1
Even if a number of cells within the capacity of 0e to 10h) converge at the same time, they will not be discarded. In addition, each memory circuit 1
In order to make the cell reservation amount as uniform as possible between 0a to 10d (10e to 10h), the space switch 4 connects memory circuits 10a to 10d (10e to 10h) with a small amount of cell reservation.
), the memory circuits 10a to 10d (10e to 10h) have almost the same performance as one large memory circuit shared by all incoming lines, and are not discarded due to cell fluctuations. make the rate even lower. In the above embodiment, the number of input ports and the number of output ports of the entire cell exchange switch are the same, but they may be different. Furthermore, although the number of stages of the output stage cell exchange switch module has been shown as one stage, it may be expanded by sequentially connecting multiple stages. In addition, in the embodiment, the number of input and output ports of the entire cell switching device was set to 16 each, and this was divided into 4 each, and the cell switching switch modules at the input stage and the output stage were configured in a 4 x 4 configuration. It may also be configured as a single cell exchange switch without being divided into such modules. In addition, for the address in the cell header section, an example was shown in which the outgoing line number is assigned to two address sections in correspondence with the two-stage output stage cell exchange switch module, but the coded number is assigned to one address section. You may perform some kind of conversion processing such as giving. Furthermore, in the above embodiment, a case has been described in which one cell is output to only one output port, but depending on how the address is specified, the output stage cell selection circuit can be set to output to multiple output ports. It is possible to do so, and a broadcasting function may be added. . Alternatively, the header section and the data section may be separated structurally, circuits with different speeds may be used, and the header section and the data section may be respectively assigned to a plurality of signal lines arranged in parallel. In the above embodiment, the link speed of the input port and the output port are the same, but the output stage memory circuit 10 of FIG.
Traffic concentration is possible by making the read speed from a to 10d faster than the link speed of the input port, and conversely, it is also possible to make the link speed of the input port faster than the speed of the output port. It is assumed that the multiplexing speed of the signal j is the same as the multiplexing speed of the signal e,
By increasing the multiplexing speed of signal j, the cell discard rate between output stage cell exchange switch module stages can be further reduced. Furthermore, in the above embodiment, one outgoing line corresponding address FIFO is provided for each outgoing line of the output stage cell exchange switch module, but a plurality of FIFOs are provided on the priority side for each outgoing line, and the cell It is also possible to multiplex cells with higher priority first based on a code indicating priority added to the header part in addition to the address. In addition, in the read right granting circuit, 4
Although we have shown an example in which two FIFOs are read out in succession when more than one FIFO is accumulated, other values may be used. It may be. In addition, if operating speed restrictions are required, serial/parallel conversion circuits are installed before and after this switch. A parallel/serial conversion circuit may be added to process the signals as parallel signals.

【Effect of the invention】

As described above, according to the present invention, when the input stage cell exchange switch module receives cells that have been multiplexed and sorted by destination, the output stage cell exchange switch module transfers the cells to the cell storage level. The cells are configured to be written preferentially to the storage means with the least amount of data, and after re-multiplexing the cells read from each storage means for each destination under the control of the storage control means, the cells are distributed to each output port. Therefore, blocking does not occur, and
Even if cells are concentrated on a specific output port, the probability of cells being discarded is low, and there is an effect that a cell switching device can be obtained that can perform switching without affecting cells to other output ports.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a cell switching device according to an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration 5 of an output stage cell switching switch module, and FIG. 3 is a block diagram showing an input cell switching device of this embodiment. FIG. 4 is an explanatory diagram showing the format and time relationship of signals in each part of the module. FIG. 4 is an explanatory diagram showing the format and time relationship of signals in each part of the output cell exchange switch module. FIG. 5 shows a conventional cell switching device. It is a principle diagram. 2 is an input port, 3 is a cell switching device, 4 is a space switch, 5 is an output port, 7 is an input stage cell multiplexing means (input stage cell multiplexing circuit), 8a to 8h are storage means (10h)
11 is a storage control means (storage control circuit);
2 is an output stage cell multiplexing means (output stage cell multiplexing circuit);
13a to 13h are output stage cell selection means (output stage cell selection circuit), 14a to 14h are speed conversion means (speed conversion circuit), 15 is a counter for each storage circuit, 16 is an address exchange unit (address exchange circuit), 17a- 17h is an outgoing line corresponding address storage unit (outgoing line corresponding address FIFO), 18 is a read right granting unit (read right granting circuit), 19a to 19h
is free address management means (free address management circuit), 6
0~63 are input stage cell exchange switch modules, 70~
73 is an output stage cell exchange switch module, 80 to 83
is a cell output stage module. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Q 2. Be Bebe Procedural Corrections Specialist (Voluntary) ■.・Indication of the subject matter ÷−← Japanese Patent Application No. 1-182215 2゜Name of the invention Relationship to the cell exchange device amendment case Patent applicant address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name Name (601) Mitsubishi Electric Corporation Representative Moriya Shiki 4, Agent Postal code 105 Address
1-4-10 Nishi-Shinbashi, Minato-ku, Tokyo 6゜Contents of the amendment (1) The phrase "Area's Inn" in the third line of page 4 of the specification is amended to read "Area's Inn." (2) On page 6, line 13 of the specification, the phrase ``proposed, but certain output'' is corrected to ``proposed, but this method also has a certain output.'' (3) From line 15 on page 6 of the specification to line 16 on the same page, there was a problem in that [ was blocked and other... was king. ``There is a problem that it is easy to get blocked.''
and correct it. (4) In the 18th line of page 6 of the specification, the phrase "has been made" has been replaced with "by making the individual buffer memories common to all input lines and making the amount of reserved cells uniform." and correct it. (5) In the 20th line of page 6 of the specification, the phrase "Do not affect the cell to G" should be amended to "Do not affect the cell to G as much as possible." (6) In the third line of page 9 of the specification, "output port" should be corrected to "input port." (7) In the 12th line of page 23 of the specification, "Input to cell exchange switch modules 70 to 71" is corrected to "Input to cell exchange switch modules 70 to 73." (8) On page 28, line 14 of the specification, the phrase "output cell replacement" is corrected to "output stage cell replacement."that's all

Claims (1)

[Claims] In a cell switching device, each of which has a header section and a data section, and outputs cells input from a plurality of input ports to output ports specified by the header section of the cell, the plurality of input ports a connected input stage cell exchange switch module, one or more output stage cell exchange switch modules connected to the input stage cell exchange switch module, and a final stage connected to the output stage cell exchange switch module. a cell output stage module to which the output port is connected; input stage cell multiplexing means for time division multiplexing cells input to the input port by the input stage cell exchange switch module;
Among the cells output from the input stage cell multiplexing means,
an input stage cell selection means for selecting and passing cells destined for a predetermined destination, and the output stage cell exchange switch module is arranged at the input stage cell selection means of the input stage cell exchange switch module or at a previous stage. A spatial switch that performs switching by spatially arranging contacts for the cells output from the output stage cell selection means of the output stage cell exchange switch module, and a destination of the cells output from the spatial switch are analyzed. a header processing means for
storage means capable of writing and reading cells output from the header processing means by specifying an address; and an address exchange unit that allocates the address at which the cell has been written to the storage means according to the destination while referring to the header processing means. , an outgoing line corresponding address storage unit in which the output address of the address exchange unit can be written and read on a first-come, first-served basis for each destination; and an outgoing line corresponding address storage unit that sequentially outputs the addresses output from the outgoing line corresponding address storage unit and stores the cells from the storage means. a read right granting unit that enables reading; and a memory control means comprising a memory circuit-specific counter that counts the number of cells reserved in the memory means and sends the count to the space switch; and an output from the memory control means. vacant address management means that reads a cell from the storage means using the address written in the cell, stores the address as a vacant address, and outputs it as a write address when the storage means writes a new cell; output stage cell multiplexing means for multiplexing cells read out from the storage means; and an output stage for selecting and passing cells destined for a predetermined destination from among the cells output from the output stage cell multiplexing means. cell selection means, the cell output stage module is connected to the output stage cell selection means of the output stage cell exchange switch module at the last stage, and the cell output stage module is connected to the output stage cell selection means of the output stage cell exchange switch module at the final stage, and the cell output stage module is connected to the output stage cell selection means of the output stage cell exchange switch module at the final stage, A cell switching device characterized by having a speed converting means for converting into a speed.