JPH034552A - Electronic device - Google Patents

Abstract

PURPOSE:To surely prevent the generation of crosstalk by a method wherein a conductor layer, in which the capacity between opposed electrodes and an inter-wiring capacity are easy to generate, is constituted so as to connect to a fixed potential. CONSTITUTION:An epitaxial layer 13 directly under a bonding pad 1c is insularly isolated from other semiconductor layer and at the same time, this layer 13 is connected to a VCC power line 4. Accordingly, a crosstalk signal to go from the layer 13 toward a semiconductor substrate escapes to the wiring 4, whereby a crosstalk pass from the layer 13 to the substrate 12 is interrupted and an adverse effect to a receiving side transistor 6 is stopped. Moreover, as the layer 13 and the substrate 12, which is positioned under this layer 13, are formed into a conductivity type inverse to each other, the crosstalk pass from the layer 13 to the substrate 12 is hardly passed compared to a case where the layer 13 and the substrate 12 are formed into the same conductivity type and the signal is liable to escape to the side of this wiring 4.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a technique that is effective when applied to electronic devices that handle high-frequency signals or large-amplitude signals. The present invention relates to a technique that is effective for use in semiconductor devices such as monolithic ICs in which electrodes and/or wiring that handle high-frequency signals or large-amplitude signals are formed.

[Prior Art] A bonding pad that functions as an input/output terminal in a semiconductor device is formed on a semiconductor layer such as an epitaxial layer formed on a semiconductor substrate with an insulating film interposed therebetween. In the device, circuit elements such as transistors are mounted on one main surface of the semiconductor layer.

[Problem to be solved by the invention] In a semiconductor device configured in this way.

A considerable amount of parasitic capacitance is formed between this bonding pad and the semiconductor layer directly below this bonding pad, and moreover, when the semiconductor layer and the semiconductor substrate are formed with opposite conductivity types, Since a parasitic capacitance (pn junction capacitance) C2 is formed between the semiconductor layer and the semiconductor substrate, the coupling (series connection) of the parasitic capacitances C4 and C2 causes a There was a fear that a crosstalk path to the transistor would be formed.

This crosstalk becomes particularly noticeable and becomes a problem when the bonding pad handles a high frequency signal or a large amplitude signal, that is, when it is an electrode (input/output terminal) that handles a high frequency signal or a large amplitude signal.

Therefore, it is necessary to avoid the above problems. Conventionally, the area around the transistor on the receiving side of crosstalk is isolated, and this isolation layer is connected to the ground line, and the input terminal and output terminal of the signal are physically connected. Countermeasures were taken, such as separating the terminals from each other, arranging the AC ground terminal between the input and output terminals, and preventing the wiring from crossing each other, but these measures were only marginally effective.

Moreover, as mentioned above, the signal generation source of this crosstalk is often formed directly under the bonding pad (electrode) that handles high-frequency signals or large-amplitude signals, but it is not limited to this location. Alternatively, there is a risk that a signal generation source may be formed under the wiring section that handles large-amplitude signals.

In other words, there is a risk that a crosstalk path may be formed from the wiring to the transistor via the semiconductor substrate.

Further, this problem of crosstalk may similarly occur in a multilayer wiring board having two or more layers and an electronic device including, for example, a plurality of vacuum tubes arranged on the multilayer wiring board. In other words, electrodes and/or wiring that handles electrical signals are formed on the surface layer and connected to a certain vacuum tube, and a second wiring layer (conductor layer) is formed below this with an insulating film interposed therebetween.
There is a problem in that a parasitic capacitance is formed between the tube and the tube, and a crosstalk path is formed to other vacuum tubes.

The present invention has been made in view of the above problems, and an object of the present invention is to provide an electronic device (including a semiconductor device) in which crosstalk is reliably prevented.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

That is, in an electronic device in which electrodes and/or wiring for handling electrical signals are formed on a conductive layer via an insulating film,
A conductor layer that is likely to cause capacitance between a counter electrode and/or a pair of wires is connected to a fixed potential.

[Function] According to the above-described means, since the conductor layer that tends to generate capacitance between the counter electrode and/or pair wire is connected to a fixed potential, it is possible to connect the conductor layer that tends to generate capacitance between the counter electrode and/or pair wire due to the effect that crosstalk signals can escape to the fixed potential.

The crosstalk path from the conductor layer is now blocked, and the above objective of reliably preventing crosstalk is achieved.

[Example] Embodiments of the present invention will be described below with reference to the drawings.

1 and 2 show an embodiment of a semiconductor device as an example of an electronic device according to the present invention.

The outline is as follows.

In FIGS. 1 and 2, reference numeral 11 indicates a semiconductor chip, and a number of bonding pads 1, which are electrodes, are arranged on the periphery of the chip 11. As shown in FIG. Here, 1a is a bonding pad at a fixed potential of VcC, 1b is a bonding pad at ground potential, and 1c
2 respectively indicate a bonding pad that handles a high frequency signal or a large amplitude signal, that is, a bonding pad that is a source of crosstalk signal generation, and these bonding pads la, lb, and lc are P #! type on the n-type epitaxial layer 13 formed on the type semiconductor substrate 12. It is formed with a lamina 9 interposed therebetween. The epitaxial layer 13, which is a semiconductor layer directly under the above-mentioned bonding pad 1c, is isolated in an island shape from other semiconductor layers by a p-type isolation layer 8.
This isolated epitaxial layer 13
is in contact with a Vcc power line (aluminum wiring) 4 connected to the Vcc potential bonding pad 1a via a diffusion layer 1o. On the other hand, code 6 is n
An n-type emitter diffusion layer 14, a p-type base diffusion layer 15 . A highly sensitive bipolar transistor consisting of an n-type collector diffusion layer 16 is shown. This high-sensitivity bipolar transistor 6 is isolated from other semiconductor layers by a p-type isolation layer 7, and this isolation layer 7 is connected to the ground potential of the bonding pad 1b.
It is connected to a ground power line 3 which is connected to the ground power line 3.

Here, as shown in FIG. 2, a parasitic capacitance C□ is formed between the bonding pad 1c and the epitaxial layer 13 directly below the bonding pad IC, and the epitaxial layer 13 and the semiconductor substrate 12 Since these are formed to have opposite conductivity types, a parasitic capacitance (pn junction capacitance) C2 is formed between the epitaxial layer 13 and the semiconductor substrate 12.

However, in this embodiment, as described above, the epitaxial layer 13 immediately below the bonding pad IC, that is, the semiconductor layer 13 where capacitance between the counter electrodes is likely to occur, is isolated in an island shape from other semiconductor layers. ing(
Since the isolated epitaxial layer 13 is connected to the Vcc power supply line 4,
The crosstalk signal that conventionally went from this epitaxial layer 13 to the semiconductor substrate 12 is at the fixed potential (Vcc).
The crosstalk path from the epitaxial layer 13 to the semiconductor substrate 12 is cut off, and the receiving transistor 6
adverse effects on the environment are prevented. Furthermore, as described above, the epitaxial layer 13 and the semiconductor substrate 12, which is the semiconductor layer located below, are of opposite conductivity types, so the crosstalk path from the epitaxial layer 13 to the semiconductor substrate 12 is of the same conductivity type. In addition, since the wiring 4 connected to the fixed potential (Vcc) is made of aluminum, the wiring impedance is extremely low. It's getting easier.

Further, in this embodiment, as described above, the high-sensitivity bipolar transistor 6 on the crosstalk receiving side is isolated, and this isolation layer 7 is connected to the ground connected to the bonding pad 1b at the ground potential. Since it is connected to the power supply line 3, the crosstalk prevention effect for the high sensitivity bipolar transistor 6 is further enhanced.

Incidentally, in this embodiment, the AC signal passing through the bonding pad 1c has a frequency of 3 MI (z or more) or a signal level of 0.5 Vp-p (peak-to-peak) or more, and has such a large amplitude and high frequency. Since crosstalk signals are particularly likely to occur directly under the bonding pad (electrode) that handles signals, the application of this embodiment is particularly effective.

In this way, the signal generation source of crosstalk is often directly under the bonding pad (electrode) that handles high-frequency signals or large-amplitude signals, but it is not limited to this location. It goes without saying that it is better to apply the present invention to the semiconductor layer under such a wiring position, since there is a possibility that the wiring under the position where the signal is handled also becomes a signal generation source.

Here, the epitaxial layer 13 directly below the bonding pad IC is connected to the vCC power supply line 4, but it is also possible to connect it to another power supply line, and even with this configuration, the epitaxial layer 13 is connected to the semiconductor substrate. Since the crosstalk signal that was heading to the epitaxial layer 12 can now escape to another power supply line, it is possible to block the crosstalk path from the epitaxial layer 13 to the semiconductor device 12. Therefore, the same effect can be expected even if the epitaxial layer 13 is connected to a fixed potential by connecting it to a completely independent low-impedance power supply pad (a pad not used as another power supply). Crosstalk prevention will be achieved.

According to the semiconductor device configured in this way, the following effects can be obtained.

That is, in a semiconductor device in which an electrode 10 and/or a wiring for handling an electrical signal is formed on a semiconductor layer 13 via an insulating film 9, the semiconductor layer 13 is likely to have a counter-electrode capacitance C1 and/or a pair-to-wire capacitance. The isolation layer 8
The conductivity type of the semiconductor layer 13 is opposite to that of the semiconductor layer (semiconductor substrate) 12 located below.
is connected to the wiring 4 connected to a fixed potential (Vcc) la, so that the semiconductor substrate 12 is connected to the conductor layer 13 where the counter-electrode capacitance C1 and/or the pair-wiring capacitance tends to occur.
The crosstalk signal that was heading towards the fixed potential (Vc
c) Due to the action of being able to escape to the 4 side, the semiconductor layer 13
The crosstalk path from to the semiconductor substrate 12 is now cut off.

As described in the prior art section, the above embodiments are applicable to electronic devices expanded to devices consisting of a multilayer wiring board with two or more layers and, for example, a plurality of vacuum tubes arranged on the multilayer wiring board. is equally applicable, in which case
It is sufficient to connect the second wiring layer (conductor M) only in the areas where counter electrode and/or pair wiring capacitance is likely to occur to a fixed potential, and configure the wiring layers on the other two calendar days as normal wiring. With such a configuration, crosstalk signals from the conductor layer that tends to cause capacitance between the counter electrode and/or the pair wire can escape to the fixed potential, and the crosstalk path from the conductor layer can be cut off. become.

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Nor.

For example, in the above embodiment, the isolation is performed by pn junction separation, but it is also possible to perform the isolation by using an oxide film.

Further, in the above embodiments, the electrodes that handle electrical signals are used as bonding pads (input/output terminals), but they may also be terminals connected to an internal oscillation circuit.

Furthermore, although the above embodiment describes an application example using an n-type semiconductor substrate as the substrate, it goes without saying that it can be similarly applied to an n-type semiconductor substrate of the opposite conductivity type. do not have.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, in an electronic device in which electrodes and/or wiring for handling electrical signals are formed on a conductive layer via an insulating film,
Since the conductor layer that tends to generate capacitance between the counter electrode and/or pair wire is configured to be connected to a fixed potential, crosstalk signals from the conductor layer that tends to generate capacitance between the counter electrode and/or pair wire escape to the fixed potential. You will get it. the result,
The crosstalk path from the conductor layer is now cut off, making it possible to reliably prevent crosstalk.

[Brief explanation of drawings]

FIG. 1 is a plan view of an embodiment of an electronic device (semiconductor device) according to the present invention, and FIG. 2 is a sectional view taken along line AA in FIG. 1a...fixed potential, 1c...electrode, 4...
Power line, 8...Isolation layer, 9...
- Insulating film, 12... semiconductor substrate, 13... semiconductor layer, C1... parasitic capacitance. n ■ r\

Claims (3)

[Claims] 1. In an electronic device in which electrodes and/or wiring for handling electrical signals are formed on a conductor layer via an insulating film, the conductor layer that tends to generate capacitance between counter electrodes and/or pair wirings is configured to be connected to a fixed potential. An electronic device characterized by: 2. In electronic devices in which electrodes and/or wiring for handling electrical signals are formed on a semiconductor layer via an insulating film, the semiconductor layer that tends to generate capacitance between counter electrodes and/or pair wirings is isolated and separated, and the 1. An electronic device characterized in that the semiconductor layer is of a conductivity type opposite to the semiconductor layer located thereon, and the isolated semiconductor layer is connected to a fixed potential. 3. Claim 1, wherein the electrode and/or wiring on the conductor layer that tends to cause capacitance between the counter electrode and/or pair wiring is an electrode and/or wiring that handles a high frequency signal or a large amplitude signal. Electronic devices as described in section.