JPH0345438Y2 - - Google Patents
Info
- Publication number
- JPH0345438Y2 JPH0345438Y2 JP4223986U JP4223986U JPH0345438Y2 JP H0345438 Y2 JPH0345438 Y2 JP H0345438Y2 JP 4223986 U JP4223986 U JP 4223986U JP 4223986 U JP4223986 U JP 4223986U JP H0345438 Y2 JPH0345438 Y2 JP H0345438Y2
- Authority
- JP
- Japan
- Prior art keywords
- package
- lead
- partition wall
- contact
- socket
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000005192 partition Methods 0.000 claims description 43
- 230000002093 peripheral effect Effects 0.000 claims description 3
- OQCFWECOQNPQCG-UHFFFAOYSA-N 1,3,4,8-tetrahydropyrimido[4,5-c]oxazin-7-one Chemical compound C1CONC2=C1C=NC(=O)N2 OQCFWECOQNPQCG-UHFFFAOYSA-N 0.000 description 5
- 238000003780 insertion Methods 0.000 description 3
- 230000037431 insertion Effects 0.000 description 3
- 102100025490 Slit homolog 1 protein Human genes 0.000 description 1
- 101710123186 Slit homolog 1 protein Proteins 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Connecting Device With Holders (AREA)
Description
【考案の詳細な説明】
〔産業上の利用分野〕
本考案は、フラツト型ICパツケージの試験用
として好適なICソケツトの構造に関するもので
ある。[Detailed Description of the Invention] [Industrial Field of Application] The present invention relates to the structure of an IC socket suitable for testing flat type IC packages.
従来フラツト型ICパツケージには、第7図に
示される如く、パツケージPのリードP′の基部
P′a及び実装の際半田付される接触部P′bが段状
に成形されていて、これにより実装に対する便が
図られている。一方、フラツト型ICパツケージ
Pの試験用ICソケツトに関し、従来例えば第6
図乃至第10図に示される如く、基盤11上には
装着されるべきICパツケージのリードP′に接続
されるコンタクトピン15が列設されていると
(第10図参照)共に、各コンタクトピン15は
仕切壁13によつて相互に仕切られている。斯し
て、ICパツケージPが基盤11の収容部12内
へ収納された際各リードP′は対応するスリツト1
4内へ挿入されると共にICパツケージPの本体
が押え板17により押圧されることによつてリー
ドP′及びコンタクトピン15の接続が行われる。
又、この接続の際、リードP′の変形、損傷又はコ
ンタクトピンとの電気的接続及びICパツケージ
Pの位置決め等これらの点につき試験用ソケツト
として十分な配慮がなされることが必要である。
In the conventional flat type IC package, as shown in Figure 7, the base of the lead P' of the package P is
P′a and the contact portion P′b to be soldered during mounting are formed in a stepped shape, thereby facilitating mounting. On the other hand, regarding IC sockets for testing flat type IC packages P, conventional
As shown in FIGS. 10 to 10, contact pins 15 connected to leads P' of an IC package to be mounted are arranged in rows on the substrate 11 (see FIG. 10), and each contact pin 15 are separated from each other by a partition wall 13. Thus, when the IC package P is housed in the accommodating portion 12 of the base 11, each lead P' is inserted into the corresponding slit 1.
4 and the main body of the IC package P is pressed by the holding plate 17, thereby connecting the leads P' and the contact pins 15.
Further, when making this connection, it is necessary to take sufficient consideration to prevent deformation or damage of the lead P', electrical connection with the contact pin, positioning of the IC package P, etc. as the socket is used for testing.
しかしながら、従来のICソケツトでは、リー
ドP′の仕切壁13との接触又は衝突による該リー
ドP′の変形等を防止するため仕切壁13の高さを
低くし、又は仕切壁13の厚さを薄くし且つスリ
ツト14の幅を広げる等した場合には、パツケー
ジPの正確な位置決めが困難となり、このためリ
ードP′とコンタクトピン14との接触が不完全と
なることから両者の電気的接続が十分確保され得
ない。更に、仕切壁13自体の損傷を来す等の不
都合が生じていた。又、ICパツケージPが基盤
11の収容部12内へ収容された際(第10図参
照)、リードP′の先端の接触部P′bの下面がコンタ
クトピン15に対し接触せしめられるため該下面
の変形、損傷等が生じ、この結果ICパツケージ
Pの実装時電気的接続が不十分になるので問題で
あつた。更に、収容部12内でパツケージPがガ
タつくのを防止するため該収容部12を隔てた仕
切壁13,13間の距離l1(第8図参照)はパツ
ケージP本体の幅l2(第7図参照)とほぼ等しく
(l1≧l2)なるようにしなければならないが、この
場合、仕切壁13はリードP′の基部P′aに至る部
分に対して、即ちリードP′のほぼ全長に亘つてこ
れをスリツト14内へ案内することにより位置決
めがなされることとなる。これにより、該リード
P′とコンタクトピンとの位置決め及び電気的接続
は確実になされ得るが、同時に第9図に示される
如く、ICパツケージPが仕切壁13に対し傾斜
した状態で離脱せしめられる場合には、リード
P′が仕切壁13の角や側面に当接し、その結果該
リードが変形又損傷せしめられるという問題が生
じる。かかる問題に対し仕切壁13によるリード
P′の案内を浅くする、即ちリードP′の先端部のみ
によつて位置決めがなされるようにした場合、
ICパツケージが収容部2内でガタついてしまい
リードP′とコンタクトピン14との電気的接続が
不安定となる。
However, in conventional IC sockets, the height of the partition wall 13 is lowered or the thickness of the partition wall 13 is reduced in order to prevent deformation of the lead P' due to contact or collision with the partition wall 13. If it is made thinner and the width of the slit 14 is increased, it becomes difficult to accurately position the package P, and as a result, the contact between the lead P' and the contact pin 14 becomes incomplete, and the electrical connection between the two becomes difficult. cannot be adequately secured. Furthermore, there have been other inconveniences such as damage to the partition wall 13 itself. Furthermore, when the IC package P is housed in the housing portion 12 of the base plate 11 (see FIG. 10), the lower surface of the contact portion P'b at the tip of the lead P' is brought into contact with the contact pin 15. This was a problem because the IC package P was deformed and damaged, resulting in insufficient electrical connection when the IC package P was mounted. Furthermore, in order to prevent the package P from wobbling within the housing section 12, the distance l 1 (see FIG. 8) between the partition walls 13, 13 that separate the housing section 12 is equal to the width l 2 (the width of the package P main body). (see Figure 7) should be approximately equal (l 1 ≧ l 2 ), but in this case, the partition wall 13 should be approximately equal to the portion of the lead P' that reaches the base P'a, that is, approximately the same as that of the lead P'. Positioning is accomplished by guiding it into the slit 14 along its entire length. This allows the lead to
The positioning and electrical connection between P' and the contact pin can be ensured, but at the same time, if the IC package P is removed in an inclined state with respect to the partition wall 13, as shown in FIG.
A problem arises in that P' comes into contact with the corner or side surface of the partition wall 13, and as a result, the lead is deformed or damaged. To solve this problem, the partition wall 13 can be used as a lead.
When guiding P′ is made shallow, that is, when positioning is performed only by the tip of lead P′,
The IC package becomes loose within the housing section 2, and the electrical connection between the lead P' and the contact pin 14 becomes unstable.
本考案はかかる実情に鑑み、ICパツケージP
のソケツトへの実装に際し、リードP′の変形又は
損傷が生ずることなく、該リードP′及びコンタク
トピンの電気的接続が確実になされると共に、ス
リツト14に対するリードP′の挿入又は抜去が極
めて円滑に行なわれ得るICソケツトを提供する
ことを目的とする。 In view of these circumstances, this invention is designed to
When the lead P' is mounted in the socket, the electrical connection between the lead P' and the contact pin is ensured without deforming or damaging the lead P', and the insertion and removal of the lead P' into and out of the slit 14 is extremely smooth. The purpose is to provide an IC socket that can be used for
本考案によるICソケツトでは、ICパツケージ
を表裏反転して収容し得る凹部が基盤に形成され
ると共に、該凹部の周壁上にはICパツケージの
リードに接続されるように上記基盤内に収容され
たコンタクトピン相互を仕切る仕切壁が配設さ
れ、又、上記仕切壁群両端以外の仕切壁かさ内方
側へと突出して形成され、上記ICパツケージの
揺動を規制する突部が形成されている。
In the IC socket according to the present invention, a concave portion capable of accommodating the IC package upside down is formed in the base, and a concave portion is provided on the peripheral wall of the concave portion to be connected to the lead of the IC package housed in the base. A partition wall is provided to partition the contact pins from each other, and a protrusion is formed to protrude inwardly from the partition wall other than at both ends of the partition wall group, and to restrict the swinging of the IC package. .
第1図乃至第5図は本考案によるICソケツト
の一実施例を示し、図中、1は基盤、2は該基盤
1の中央に成形され、ICパツケージPを表裏反
転しても収容し得るようになつている凹部として
の孔、3は凹部2の周壁上に立設されICパツケ
ージPのリードP′と同ピツチで列設された仕切
壁、3′は仕切壁3群の中央に配設された中央仕
切壁(第2,3,4図参照)、3″は仕切壁3群の
左右両側に配設され仕切壁3,3′より高く形成
された両端仕切壁、3aは図において仕切壁3群
の各上端左側に形成され、上記リードP′の挿入と
離脱をガイドするテーパ部、3bはテーパ部3a
同様の目的で仕切壁3群の各上端右側に形成され
たテーパ部、4は相隣れる仕切壁3,3′,3″に
よつて画成されパツケージPが収容部2内に収容
された際リードP′の接触部P′bを受容するように
形成されたスリツト、5は接続されるべきリード
P′に対応して基盤1に列設され各仕切壁3,3′,
3″によつて仕切られると共にリードP′との接続
部5aがスリツト4内に配置されているコンタク
トピン、6は仕切壁3群のうち各々の列上では間
隔を隔てると共に該列間では相互に対向する適所
の仕切壁3から収容部2内へこれとICパツケー
ジPとで形成される間隙以下の寸法だけ突出し、
該パツケージPが収容部2内へ収容せしめられた
際これを複数の点P1,P2,P3,P4(第2図参照)
位置で案内する等、7は基盤1に開閉可能に軸着
せしめられたICパツケージPの押え板である。
1 to 5 show an embodiment of the IC socket according to the present invention. In the figures, 1 is a base, 2 is molded in the center of the base 1, and can accommodate an IC package P even if it is turned upside down. A hole 3 is a recess shaped like this, a partition wall 3 is provided upright on the peripheral wall of the recess 2 and is arranged in a row at the same pitch as the leads P' of the IC package P, and 3' is a hole arranged in the center of the group of partition walls 3. The central partition wall (see Figures 2, 3, and 4) is provided, 3'' is a partition wall at both ends that is provided on both the left and right sides of the 3 group of partition walls and is higher than the partition walls 3 and 3', and 3a is the partition wall in the figure. A tapered portion 3b is formed on the left side of the upper end of each of the three groups of partition walls and guides the insertion and removal of the lead P′.
A tapered part 4 formed on the right side of the upper end of each group of partition walls for the same purpose is defined by adjacent partition walls 3, 3', and 3'', and a package P is accommodated in the storage part 2. A slit formed to receive the contact portion P′b of the lead P′, 5 is the lead to be connected.
Each partition wall 3, 3', arranged in a row on the base 1 corresponding to P',
The contact pins 6 are separated by 3" and the connecting portions 5a with the leads P' are arranged in the slits 4. The contact pins 6 are spaced apart on each row of the 3 groups of partition walls and are separated from each other between the rows. protrudes into the housing part 2 from the partition wall 3 at a suitable location facing the IC package P by a dimension equal to or less than the gap formed between the partition wall 3 and the IC package P;
When the package P is accommodated in the storage section 2, it is placed at a plurality of points P 1 , P 2 , P 3 , P 4 (see Fig. 2).
Reference numeral 7 denotes a holding plate for the IC package P, which is pivotally attached to the base 1 so as to be openable and closable.
本考案によるICソケツトは、上記のように構
成されているから、スリツト4の開口端の幅はテ
ーパ部3a,3bによりその底部の幅l(第3図
参照)よりも実質上広くなつており、従つて、凹
部2内へICパツケージPを収容する際、該スリ
ツト4内へのリードP′の挿入はテーパ部3a,3
bが案内となつて極めて容易に行なわれ得る。こ
の際、リードP′はその全長に亘つてスリツト4内
へ挿入されず、即ち基部P′aは挿入されることな
く第2図に示されるように両側の仕切壁3,3′,
3″とICパツケージPの本体との間には夫々間隙
g=(l1−l2)/2が形成されるが、突部6はICパ
ツケージPを複数の点P1,P2,P3,P4の側面を
介してその位置を規制するので、該パツケージP
は収容部2内で正確に位置決めされる。従つて各
リードP′の接触部P′bと対応するコンタクトピン
5の接続部5aは確実且つ安定的に電気的に接続
される。尚、この場合、仮にリードP′が変形して
いたとすると、そのままでは従来のソケツトでは
該リードが仕切壁に衝突してしまうため、スリツ
ト内への挿入が不可能となつてしまうような場合
であつても、かかる変形したリードはテーパ部3
a,3bによつて案内されるから、スリツト内へ
の挿入が可能であり、一旦挿入せしめられれば該
リードP′はその挿入の際正しい形状に矯正され得
る。更に、収容部2内に収容せしめられたICパ
ツケージPを取り出すに際し、第3図に示される
如く、該パツケージPが仕切壁3等に対して傾斜
した状態で抜き出される場合でも、テーパ部3b
によつてリードP′に対する逃げが形成されている
から、該リードP′は仕切壁3,3″に当接するこ
となくスリツト4より無理なく抜き去られ得、
又、第3図に示された状態とは逆にICパツケー
ジPが左上がりに傾斜した状態で取り出される場
合でもテーパ部3aによつて逃げが形成されるか
ら、これら何れの場合もパツケージPは仕切壁
3,3′によつて変形されることなく極めて円滑
に収容部2から離脱せしめられる。又、凹部2
は、第4図及び第5図に示される如く、ICパツ
ケージPが表裏反転されて収容され得るに十分な
深さを有するから、この場合、押え板7から突出
したパツド部7a等によつてリードP′の接触部
P′bが押圧され、上記と同様リードP′とコンタク
トピン5との確実且つ安定した電気的接続が行な
われ得る。この時リードP′の基部P′aは接続部P′b
に対し該リードP′の段状の隔差分だけ下方に位置
付されるため、パツケージPが仕切壁に対し傾斜
した状態で抜き取られる場合、該基部P′aは仕切
壁に当接しようとするが、突部6は両端の仕切壁
3″以外の中央寄りの適宜の仕切壁3より突出し
ているので、実際には基部P′aは仕切壁に当接す
ることはない。このICパツケージPが表裏反転
した姿勢で収容された場合には、接続部P′bの上
側の面がコンタクトピン5の接続部5aと接続せ
しめられる結果となるから、パツケージPの実装
時に半田付されるべき該接触部P′bの下面は損傷
又は変形せしめられることなく、これによりパツ
ケージPの実装の際にリードP′の電気的接続は極
めて確実になされ得る。 Since the IC socket according to the present invention is constructed as described above, the width of the opening end of the slit 4 is substantially wider than the width l of the bottom part (see Fig. 3) due to the tapered parts 3a and 3b. Therefore, when the IC package P is accommodated in the recess 2, the lead P' is inserted into the slit 4 through the tapered parts 3a and 3.
This can be done very easily with b as a guide. At this time, the lead P' is not inserted into the slit 4 over its entire length, that is, the base P'a is not inserted, and as shown in FIG.
A gap g=(l 1 −l 2 )/2 is formed between the IC package P and the main body of the IC package P, but the protrusion 6 connects the IC package P to a plurality of points P 1 , P 2 , P 3 , its position is restricted through the side of P4 , so that the package P
is accurately positioned within the housing 2. Therefore, the contact portion P'b of each lead P' and the corresponding connection portion 5a of the contact pin 5 are electrically connected reliably and stably. In this case, if the lead P' were to be deformed, the lead would collide with the partition wall in a conventional socket, making it impossible to insert it into the slit. Even if there is such a deformed lead, the tapered part 3
a, 3b, it is possible to insert the lead P' into the slit, and once inserted, the lead P' can be corrected into the correct shape during insertion. Furthermore, when taking out the IC package P housed in the storage section 2, even if the package P is taken out in an inclined state with respect to the partition wall 3, etc., as shown in FIG.
Since the relief for the lead P' is formed by
Further, even when the IC package P is taken out in a state in which it is tilted upward to the left, contrary to the state shown in FIG. It can be removed from the housing part 2 very smoothly without being deformed by the partition walls 3, 3'. Also, recess 2
As shown in FIGS. 4 and 5, the IC package P has a sufficient depth to accommodate the IC package P turned upside down. Contact part of lead P′
P'b is pressed, and a reliable and stable electrical connection between lead P' and contact pin 5 can be established in the same manner as above. At this time, the base P′a of lead P′ is the connection point P′b
However, since the lead P' is positioned downward by the step-like distance difference, when the package P is pulled out in an inclined state with respect to the partition wall, the base P'a tends to come into contact with the partition wall. However, since the protrusion 6 protrudes from an appropriate partition wall 3 near the center other than the partition walls 3'' at both ends, the base P'a does not actually come into contact with any partition wall. If the package P is housed in an inverted position, the upper surface of the connection part P'b will be connected to the connection part 5a of the contact pin 5, so the contact that should be soldered when the package P is mounted. The lower surface of the portion P'b is not damaged or deformed, so that the electrical connection of the leads P' can be made very reliably during the mounting of the package P.
尚、上記実施例におけるテーパ部3a,3b等
の角度、寸法は適用されるべきICパツケージに
応じて適宜の値になされ又、必要により形成され
るべき突部6の数は増減される。 Incidentally, the angles and dimensions of the tapered portions 3a, 3b, etc. in the above embodiment are set to appropriate values depending on the IC package to which it is applied, and the number of protrusions 6 to be formed may be increased or decreased as necessary.
上述のように本考案によるICソケツトは、IC
パツケージの機能を損なうことなく極めて円滑且
つ確実なICパツケージの試験を可能ならしめ、
更に、試験後のICパツケージは実装に際して何
ら支障を来すことがない等の利点を有する。
As mentioned above, the IC socket according to the present invention
It enables extremely smooth and reliable testing of IC packages without impairing the functionality of the package.
Furthermore, the IC package after testing has the advantage that it does not cause any problems during mounting.
第1図乃至第5図は本考案のICソケツトの一
実施例を示し、第1図はICパツケージを収容し
得る基盤の要部の構造を示す部分斜視図、第2図
はICパツケージが収容されている状態のソケツ
トの要部の平面図、第3図はスリツトから抜き去
られる際のICパツケージのリードと仕切壁との
関係を示す部分断面図、第4図及び第5図はIC
パツケージが表裏反転して収容された場合の状態
を示す夫々基盤の要部断面図、第6図乃至第10
図は従来のICソケツトに係り、第6図は全体の
構造を示す斜視図、第7図は収容されるべきIC
パツケージの斜視図、第8図は基盤の要部を示す
斜視図、第9図はスリツトから抜き去られる際の
ICパツケージのリードと仕切壁との関係を示す
図、第10図は該パツケージが収容されている状
態のソケツト要部の縦断面図である。
1……基盤、2……凹部、3,3′,3″……仕
切壁、3a,3b……テーパ部、4……スリツ
ト、5……コンタクトピン、6……突部、7……
押え板。
Figures 1 to 5 show an embodiment of the IC socket of the present invention, Figure 1 is a partial perspective view showing the structure of the main part of the base that can accommodate the IC package, and Figure 2 shows the structure of the main part of the base that can accommodate the IC package. Figure 3 is a partial sectional view showing the relationship between the IC package leads and the partition wall when the IC package is removed from the slit, and Figures 4 and 5 are
6 to 10 are cross-sectional views of the main parts of the respective bases showing the state when the package cage is housed upside down.
The figures relate to a conventional IC socket, Fig. 6 is a perspective view showing the overall structure, and Fig. 7 is an IC to be accommodated.
A perspective view of the package, Figure 8 is a perspective view showing the main parts of the base, and Figure 9 is a perspective view of the package when it is removed from the slit.
FIG. 10, which is a diagram showing the relationship between the leads of the IC package and the partition wall, is a longitudinal sectional view of the main part of the socket in which the package is housed. DESCRIPTION OF SYMBOLS 1...Base, 2...Recess, 3, 3', 3''...Partition wall, 3a, 3b...Tapered part, 4...Slit, 5...Contact pin, 6...Protrusion, 7...
Presser plate.
Claims (1)
ジをソケツト基盤に装着して、上記リードが該ソ
ケツト基盤に収容されたコンタクトピンに接続さ
れるようになつているICソケツトにおいて、上
記基盤に形成され、上記ICパツケージを収容す
る凹部と、該凹部の周壁上に列設され上記コンタ
クトピンとコンタクトピンとを仕切る仕切壁と、
該仕切壁群の両端以外に位置する一部の仕切壁か
ら内側に向つて突出して形成され上記凹部に収容
される上記ICパツケージの側面に近接乃至は当
接する突部とを備えていることを特徴とするIC
ソケツト。 In an IC socket, a flat IC package having stepped leads is attached to a socket base, and the leads are connected to contact pins housed in the socket base. a recess for accommodating an IC package; a partition wall arranged in a row on a peripheral wall of the recess to partition the contact pins;
and a protrusion that protrudes inward from some of the partition walls located at positions other than both ends of the partition wall group and that protrudes from or comes into contact with a side surface of the IC package accommodated in the recess. Featured IC
socket.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4223986U JPH0345438Y2 (en) | 1986-03-22 | 1986-03-22 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4223986U JPH0345438Y2 (en) | 1986-03-22 | 1986-03-22 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS62153784U JPS62153784U (en) | 1987-09-29 |
JPH0345438Y2 true JPH0345438Y2 (en) | 1991-09-25 |
Family
ID=30857965
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4223986U Expired JPH0345438Y2 (en) | 1986-03-22 | 1986-03-22 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0345438Y2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012103161A (en) * | 2010-11-11 | 2012-05-31 | Shindengen Electric Mfg Co Ltd | Positioning device and positioning method |
-
1986
- 1986-03-22 JP JP4223986U patent/JPH0345438Y2/ja not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS62153784U (en) | 1987-09-29 |
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