JPH0344895A - Non-volatile semiconductor memory - Google Patents

Abstract

PURPOSE:To suppress the degradation of reading speed by providing a drain voltage supply circuit to apply a bias voltage, which is almost constant to a power supply voltage and equipped with negative temperature gradient to temperature, in the drain of a cell selected at the time of reading. CONSTITUTION:The bias voltage, which is kept almost constant to the power supply voltage and equipped with the negative temperature gradient to the temperature, is applied to the drain of a memory cell MC, which is selected at the time of reading by a drain voltage supply circuit 10 and the danger of software write with the reduction of the temperature is compensated by the reduction of the bias voltage. Thus, even at the high power supply voltage and low temperaute, there is no danger in the software writing and it is not necessary to lower the potential of a bit line at the time of normal reading while considering excess margin. Then, the degradation of the reading speed can be suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a nonvolatile semiconductor memory device, and particularly to means for supplying a bias voltage to the drain of a memory cell during reading.

(Prior Art) FIG. 5 shows a memory cell in a conventional EPROM (ultraviolet erasable/rewritable read-only memory) and a memory cell peripheral circuit used during reading. Fifth
In the figure, MA is a memory cell array, and memory cells M are made up of floating gate MOS transistors that hold data by accumulating charge in their floating gates.
C... are arranged in a matrix, and WL...
BL is a word line for selection in the row direction, and BL . . . is a bit line for selection in the column direction. This bit line BL is connected to a sense amplifier circuit SA via an N-channel MOS transistor C8 for column selection.

Further, an N-channel M for bit line potential clamping is connected between the Vcc power supply and the drain of the column selection transistor C8.
An OS transistor 51 is connected, and an N-channel MOS transistor 52 for a transfer gate is connected between the column selection transistor C8 and the sense amplifier circuit SA. The output voltage of the bias circuit 53 is applied to the gates of the bit line potential clamping transistor 51 and the transfer gate transistor 52.

Assume that one cell MC is currently selected. At this time, the control gate of the cell MC in the selected row is “
H" level (usually 5V) is applied, and the control gates of cells MC in unselected rows become "L" level. Therefore, the selected bit line BL is connected to the selected cell MC.
A cell current corresponding to the threshold voltage flows. This cell current flows through the selected column selection transistor C8 and
A flow also flows into the transfer gate transistor 52 connected to this, and the sense amplifier circuit S is determined by this cell current.
The human power @ potential of A is detected and amplified, and "1" O data is performed.

At this time, the potential of the bit line BL of the selected column (the drain voltage of the selected cell MC) is set by the bias circuit 53.
Set by. That is, the output voltage of this bias circuit 53 is applied to the N channel M for clamping the vb1 bit line potential.
If the threshold value of the OS transistor 51 is Vt, the bit line potential of the selected column becomes (Vb-Vt).

Here, the output voltage V of the bias circuit 53 at the time of reading
b1 The dependence of the bit line potential (vb-vB on the power supply voltage Vcc) of the selected column is shown in FIG.
Although the fluctuations in b are more relaxed than the fluctuations in the power supply voltage Vcc, the bias circuit 53 is basically a resistance divider circuit,
It is subject to fluctuations of about half of the power supply voltage fluctuations. Along with this,
The bit line potential (Vb-Vt) of the selected column is also subject to fluctuations.

Incidentally, in an EFROM memory cell, writing is performed by applying a high voltage to the control gate and drain to inject electrons into the floating gate and raising the threshold value as seen from the control gate. A written cell is defined as a "0" cell according to its output data. Taking a 4M-bit EFROM cell as an example, the threshold value variation with respect to the cell write time Tpw is as shown in FIG. That is, the control gate of the selected cell is set to about 12.5V, and the drain is set to about 7V.
By maintaining the write state at V for about 25 μs, the threshold of this cell increases by about 4V. The time it takes for this threshold to rise steeply (critical time T
crlt) depends on the control gate voltage and drain voltage applied to the cell.

In contrast, a cell that has not been written yet (“1” cell)
For this, the critical time T crit under the bias conditions of the control gate and drain during continuous operation under a certain power supply voltage Vce must be equal to or greater than a certain value. This is because repeated reading may cause a change in cell threshold value, leading to a risk of malfunction. This malfunction is called a "soft write." Practical values are, under a 5.5Vffi source, the control gate of the cell is about 5V and the drain is about 1
．． Critical time Tcrlt when set to 2V is 10
Must be at least 20 years old.

In addition, the E P ROM is used to check the amount of data written.
During testing, a high potential (for example, about 9V) power supply voltage VCC is often applied, and at this time, about 9V is applied to the control gate of the cell, and about 4V is applied to the drain.

When the write time Tpw is approximately 100 seconds, the critical time T crit is required to be one hour or more. In reality, high potential electricity I! Since the application of the voltage Vcc also serves as a screening of the elements that make up the large-scale integrated circuit, the requirements for the critical time T crit are stricter during testing than during normal serial testing, and the bit Line potential (drain voltage of selected cell)
decide.

However, conventionally, a resistor-divided bias circuit 53 having power supply voltage dependence, which is composed of ~10S transistors as shown in FIG. 5, is used. Vb-Vt) becomes lower than necessary, leading to a decrease in the cell current during normal readout, leading to the problem that the readout speed cannot be increased.

Moreover, the lower the temperature, the more severe the soft light is, -4
If the temperature is guaranteed down to 0° C., it is necessary to further reduce the bit line potential (vb-vt) during normal reading to allow for a margin, which further deteriorates the reading speed. Furthermore, the specifications for these soft lights are becoming stricter, especially for miniaturized cells with design rules of less than 1 μm.

(Problems to be Solved by the Invention) As mentioned above, conventional nonvolatile semiconductor memory devices are
S) Since a resistor-divided type voltage ti made up of transistors and a bias circuit with voltage dependence are used, the bit line potential during normal readout becomes lower than necessary, which reduces the drop in cell current during normal readout. However, there is a problem that the reading speed cannot be increased.

Moreover, the lower the temperature, the more severe the soft light is, =4
If the temperature is guaranteed down to 0° C., there is a problem that the read speed will further deteriorate.

The present invention has been made to solve the above-mentioned problems, and its purpose is to eliminate the risk of soft write even under high power supply voltages and low temperatures, and to provide an excessive margin for the bit line potential during normal reading. It is an object of the present invention to provide a nonvolatile semiconductor memory device that can suppress deterioration of successive output speed without requiring a reduction in speed.

[Structure of the Invention (Means for Solving the Problems)] The present invention provides a non-volatile semiconductor memory device having an array of memory cells consisting of floating gate MOS transistors that retain data by accumulating charge in their floating gates. , to the drain of the cell selected during reading,
The device is characterized in that it includes a drain voltage supply circuit that provides a bias voltage that is substantially constant with respect to the power supply voltage and has a negative temperature gradient with respect to temperature.

(Function) A bias voltage that is kept almost constant with respect to the power supply voltage and has a negative temperature gradient with respect to temperature is applied to the drain of the cell selected at the time of continuous writing, so that the soft write as the temperature decreases. It becomes possible to compensate for the danger by lowering the bias voltage.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a memory cell in an EFROM and a memory cell peripheral circuit used for reading, and compared to the conventional EFROM described above with reference to FIG. The transistor 52 and the bias circuit 53 are omitted,
A drain voltage supply circuit 10 is provided that applies a bias voltage vb'' that is substantially constant with respect to the power supply voltage Vcc and has a negative temperature gradient with respect to temperature to the bit line BL of the selected column during reading.

For example, as shown in FIG. 2, the drain voltage supply circuit 10 includes a power conversion circuit 11, an NPN bipolar transistor QN to which the output of the power conversion circuit 11 is applied to its base, and an emitter of the NPN transistor QN. It consists of an N-channel MO3I-transistor C8 for column selection inserted between the bit line and the bit line.

The power conversion circuit 11 is a band gap type power supply that is composed of a bipolar transistor and a MOS transistor formed on the same semiconductor, and outputs a voltage Vr that is almost independent of the power supply voltage Vec and almost independent of the temperature T. A conversion circuit is used. Moreover, the NPN transistor QN is
The emitter output is connected to the drains of the memory cells MC through the column selection transistor C8 and the bit line BL, and the sense amplifier circuit SA is connected to the collector.

The drain voltage supply circuit 10 configured in this way has N
By using the temperature dependence of the forward voltage drop of the PN junction diode of the PN transistor QN, a bias voltage vb'' having a negative temperature gradient with respect to temperature is applied to the drain of the selected cell MC at the time of reading.

Note that, as shown by the dotted line, a write transistor TW is connected between the write voltage Vl)p supply terminal and the emitter of the NPN transistor QN.

Next, the operation of the above EPROM will be explained. Above EFRO
The basic operation of M is similar to that of the conventional E described above with reference to FIG.
Although it is similar to a PROM, since a drain voltage supply circuit 10 is provided, the following operations are performed.

According to the present inventor's intensive analysis of data regarding miniaturized cells with a design rule of less than 1 μm, for example, 4 Mbit EP ROM cells, the control gate voltage of the cell MC selected at the time of reading (normally, Power supply voltage V
cc) is constant, the critical time T crlt
changes in proportion to e45°AVd with respect to change ΔVd in drain voltage Vd of cell MC. On the other hand, this cell M
When the control gate voltage and drain voltage Vd of C are constant, the critical time T crit changes in proportion to e-0, oo76xa'r with respect to temperature change ΔT.

Therefore, the drain voltage Vd of the cell MC selected during reading is kept almost constant with respect to the power supply voltage Vcc,
And, ΔVd/ΔT-(-0,0
076/4.5) If a bias voltage vb" having a negative temperature coefficient such as V/°C knee 1.7 mV/'C is applied from the drain voltage supply circuit 10, the voltage at room temperature and Vcc
The bit line potential (cell drain voltage) at -9V can be set to the maximum value that can guarantee readout during a one-hour test.

Moreover, by eliminating the dependence of the drain voltage Vd of the cell MC on the power supply voltage, while maintaining soft write margin,
Since the cell current can be maximized, access time can be increased.

In other words, there is no danger of soft writes even under high power supply voltages and low temperatures, and there is no need to lower the bit line potential during normal successive readouts with excessive margin, making it possible to suppress deterioration in read speed. be.

Next, the operation of the drain voltage supply circuit 10 will be explained. The base-emitter forward voltage Vbe of the NPN transistor QN is expressed as Vbe=Vgx(IT/
Tp)+Vbe0(T/Tp)...(1) Since Vg (band gap of silicon) hardly depends on temperature, ΔVbe/ΔT=-(Vg-Vbe0)/
Tp=-1.7 mV/"C-(2). On the other hand, the potential drop of the column selection transistor C3 can be almost ignored.

Therefore, as far as cells applied to the 4M bit EFROM are concerned, it can be seen that ΔVd/ΔT=ΔVbe/ΔT−(3).

Therefore, if a potential V'' with no temperature gradient is applied to the base potential of the NPN transistor QN, the drain voltage Vd of the cell MC will drop to cancel out the soft write effect as the temperature decreases, which is severe for soft writes. In general, the mutual conductance gm of a MOS transistor tends to increase as the temperature decreases, so the cell MC
Even if the drain voltage Vd decreases, the access time does not deteriorate.

Note that whether ΔVd/ΔT = ΔV be/ΔT in the above equation (3) depends on the device design of the cell MC. This does not mean that it is not necessary to do so, but it is necessary to provide temperature compensation commensurate with the soft light characteristics of the cell.

FIG. 3 shows a specific example of a bandgap type circuit as an example of the power conversion circuit 11. In FIG. 3, a first NPN is connected between the Vcc power supply and the VSS power supply (ground potential).
A transistor Q1, a first resistor R1, and a second NPN transistor Q2 whose collector and base are connected to each other are connected in series.

The base of a third NPN transistor Q3 is connected to the collector of this second NPN transistor Q2.
A second resistor R2 is connected between the emitter of the NPN transistor Q3 and the Vss power supply.

Additionally, a fourth NPN is connected between the Vcc power supply and the Vss power supply.
Transistor Q4, third resistor R3 and fourth resistor R
4 are connected in series, and a third NPN transistor Q is connected to the series connection point of this third resistor R3 and fourth resistor R4.
3 collectors are connected.

Further, a first P-channel MOS transistor P1 whose gate and drain are connected to each other, a fifth NPN transistor Q5, and a fifth resistor R5 are connected in series between the Vcc power supply and the VSS power supply. Power supply and VSS
between the power supply and the second P-channel MO5! - transistor P2 and a sixth NPN) transistor Q6 are connected in series.

The base of this sixth NPN transistor Q6 is connected to the series connection point of the third resistor R3 and the fourth resistor R4, and the first P-channel MOS transistor P1 and the second P-channel MOS transistor P2 are gate mutual,
The sources are connected to each other to form a P-channel current mirror circuit CM, and a fifth NPN transistor Q5
and a fourth NPN transistor Q4 and a first NPN transistor Q4
The bases of the PN transistor Q1 are connected to the power output node 3.
1, and the output voltage Vout (-Vr) of this power supply output node 31 is connected to the NPN) transistor QN.
given on the basis of.

Since this power conversion circuit 11 itself is well known, a description of its operation will be omitted, but the fourth NPN transistor Q4
If the current value flowing through the NPN transistor QN is designed to be the same as the current value flowing through the NPN transistor QN, and the voltage drop Vbe between the base and emitter of each is made equal, the bit line potential of the selected column (V r - Vbe ) is the fourth N
The emitter potential of the PN transistor N4 is approximately equal to the potential V]-. This emitter potential V1 is Vl= (R3/R2) (kT/q)ilnK+ (
1+ R3/R4)Vbe(4) ΔVl/ΔT T.

... (5) Here, k is the Boltzmann constant, T is the absolute temperature, q is the electron charge ffi, and K is the ratio of the current density flowing through the emitters of the second NPN transistor Q2 and the third NPN transistor Q3. be. In a 4 Mbit EFROM cell, it is sufficient to select a resistance value such that ΔVl/ΔT−1.7mVSV1=1.2V.

On the other hand, the dependence of the emitter potential V1 on the power supply voltage Vcc is calculated from both equations (4) as ΔVl/ΔVcc −(1+R3/R4)ΔV be/ΔVcc −(6
) However, the current of the sixth NPN transistor Q6 is I6
Expressed as: Vbe-(kT/Q) In (1B/Is)
=-(7), so even if 16 changes due to a change in the power supply voltage Vcc, Vbe hardly changes. Furthermore, since a P-channel current mirror circuit CM is connected to the collector of the sixth NPN transistor Q6,
The influence of fluctuations in the power supply voltage Vcc of I6 itself can be almost eliminated. Therefore, the power supply voltage V during testing
It is also possible to eliminate the influence of noise on the bit line on the CC or power supply voltage Vcc during reading, and also prevent deterioration of access time due to noise.

Note that the drain voltage supply circuit 10 is not limited to the above embodiment, and various modifications are possible.
A MOS transistor may be used instead of N.

In addition, with miniaturization, the breakdown voltage between the base and emitter and the breakdown voltage between the collector and emitter of the NPN transistor QN decreases, so the write voltage Vl)I) at the time of writing decreases from the NPN l
- In order to protect the transistor QN, an N-channel MOS transistor S for switching is inserted between the emitter of the NPN transistor QN and the column selection transistor C8, as in the drain voltage supply circuit 40 shown in FIG. Then, this transistor SW may be controlled to be in an OFF state during writing and to be in an ON state during continuous writing.

Furthermore, the drain voltage supply circuit 10.40 may be configured without using a bandgap type power conversion circuit.

The present invention is also applicable to EEPROM (electrically erasable and rewritable read-only memory).

[Effects of the Invention] As described above, according to the nonvolatile semiconductor memory device of the present invention, there is no danger of soft write even under high power supply voltages and low temperatures, and the bit line potential during normal reading can be set with an excessive margin. There is no need to lower the speed, and deterioration of the successive output speed can be suppressed.

[Brief explanation of drawings]

FIG. 1 is a configuration explanatory diagram showing a memory cell of an EPROM according to an embodiment of the present invention and a memory cell peripheral circuit during reading, and FIG. 2 is a circuit diagram showing a specific example of the drain voltage supply circuit in FIG. 1. 3 is a circuit diagram showing a specific example of the power conversion circuit in FIG. 2, FIG. 4 is a circuit diagram showing a modification of the drain voltage supply circuit in FIG. 2, and FIG. 5 is a circuit diagram showing a modification of the drain voltage supply circuit in FIG.
FIG. 6 is a configuration explanatory diagram showing the memory cell of FIG. 5 and the memory cell peripheral circuit at the time of reading. FIG. ) power supply voltage Vce
FIG. 7 is a diagram showing the dependence, and is a diagram showing the write characteristics of the EPROM cell in FIG. 5. MA...memory cell array, MC...memory cell,
WL...word line, BL...bit line, C8...
Column selection transistor, QN... NPN transistor, SA... sense amplifier circuit, 10.40...
Drain voltage supply circuit, 11...power conversion circuit.

Claims (4)

[Claims] (1) In a non-volatile semiconductor memory device that has an array of memory cells consisting of floating gate MOS transistors that hold data by accumulating charge in their floating gates, a power supply voltage is applied to the drain of a selected cell during reading. 1. A nonvolatile semiconductor memory device comprising a drain voltage supply circuit that provides a bias voltage that is substantially constant with respect to temperature and has a negative temperature gradient with respect to temperature. (2) The drain voltage supply circuit includes a bandgap type power conversion circuit consisting of a bipolar transistor and a MOS transistor formed on the same semiconductor, and a bipolar transistor whose base is supplied with the output of the power conversion circuit or the power supply voltage. M whose output is given to the gate
Claim 1 characterized by comprising an OS transistor.
The nonvolatile semiconductor memory device described above. (3) The nonvolatile semiconductor memory according to claim 1, wherein the drain voltage supply circuit gives a negative temperature gradient to the voltage output by using the temperature dependence of the forward voltage drop of the PN junction diode. Device. (4) The drain voltage supply circuit is composed of a bipolar transistor and a MOS transistor formed on the same semiconductor, and includes a bandgap power conversion circuit that outputs a voltage that is almost independent of power supply voltage and temperature; The output of the power conversion circuit is applied to the base, the sense amplifier circuit is connected to the collector side, and the emitter output is connected to the drain of the memory cell via the column selection transistor. The nonvolatile semiconductor memory device according to claim 1.