JPH0344718B2 - - Google Patents

Info

Publication number
JPH0344718B2
JPH0344718B2 JP59156846A JP15684684A JPH0344718B2 JP H0344718 B2 JPH0344718 B2 JP H0344718B2 JP 59156846 A JP59156846 A JP 59156846A JP 15684684 A JP15684684 A JP 15684684A JP H0344718 B2 JPH0344718 B2 JP H0344718B2
Authority
JP
Japan
Prior art keywords
processor
connection
call
information
time division
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59156846A
Other languages
Japanese (ja)
Other versions
JPS6135696A (en
Inventor
Atsushi Moryama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP15684684A priority Critical patent/JPS6135696A/en
Publication of JPS6135696A publication Critical patent/JPS6135696A/en
Publication of JPH0344718B2 publication Critical patent/JPH0344718B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04MTELEPHONIC COMMUNICATION
    • H04M3/00Automatic or semi-automatic exchanges
    • H04M3/22Arrangements for supervision, monitoring or testing
    • H04M3/24Arrangements for supervision, monitoring or testing with provision for checking the normal operation
    • H04M3/241Arrangements for supervision, monitoring or testing with provision for checking the normal operation for stored program controlled exchanges
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q11/00Selecting arrangements for multiplex systems
    • H04Q11/04Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0407Selecting arrangements for multiplex systems for time-division multiplexing using a stored programme control

Description

【発明の詳細な説明】 (技術分野) 本発明は蓄積プログラム制御交換機における、
障害発生時の接続呼保持再開方式に関する。
DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a storage program control switch.
This invention relates to a method for maintaining and resuming connected calls when a failure occurs.

(従来技術) 従来、この種の再開方式は、主記憶メモリ内の
接続状態メモリの内容(以下呼情報と云う)を磁
気記憶装置等の外部記憶装置に退避し、障害発生
時に前記外部記憶装置より呼情報を読出し、主記
憶メモリに設定すると共に回線を制御して再関し
ていた。
(Prior Art) Conventionally, this type of restart method saves the contents of the connection state memory (hereinafter referred to as call information) in the main memory to an external storage device such as a magnetic storage device, and when a failure occurs, the contents of the connection state memory are saved in the external storage device. The call information was read out and set in the main memory, and the line was controlled and reconnected.

従つて呼情報を退避する為に外部記憶装置が必
要になり、更に大容量交換機においては、膨大な
記憶容量が必要となり外部記憶装置が高価なもの
になつていた。また、接続状態の如何に拘らず定
期的に呼情報を退避していたために、処理装置の
処理能力が低下するという欠点があつた。
Therefore, an external storage device is required to save the call information, and in large-capacity exchanges, an enormous storage capacity is required, making the external storage device expensive. Furthermore, since call information is periodically saved regardless of the connection state, there is a drawback that the processing capacity of the processing device is reduced.

(発明の目的) 本発明の目的は時分割スイツチ制御プロセツサ
の記憶メモリに記憶されている時分割スイツチの
リンク情報を用いる事により上記欠点を除去し、
外部記憶装置を設ける事無く接続呼保持再開を可
能とする接続呼保持再開方式を提供することにあ
る。
(Object of the Invention) The object of the present invention is to eliminate the above drawbacks by using the link information of the time division switch stored in the storage memory of the time division switch control processor.
An object of the present invention is to provide a connection call holding/resuming method that enables holding/resuming a connected call without providing an external storage device.

(発明の構成) 本発明によると蓄積プログラム制御交換機にお
いて、回線(ライン及びトランク)の接続状態を
記憶し状態変化が生起した際にこの接続状態をも
とにして次に成すべき接続をプログラムで随時識
別して前記回線を制御する第1のプロセツサと、
時分割スイツチのリンク情報及び局情報を記憶し
前記第1のプロセツサからのリンク制御要求をも
とに前記時分割スイツチを制御する第2のプロセ
ツサとを有し、前記第1のプロセツサに障害が発
生した際に前記第2のプロセツサの記憶メモリに
記憶されているリンク情報をもとに呼の連続性を
保持したまま前記障害が発生した第1のプロセツ
サを再開させる事を特徴とする接続呼保持再開方
式が得られる。
(Structure of the Invention) According to the present invention, in a storage program controlled exchange, the connection status of lines (lines and trunks) is stored, and when a change in status occurs, a program determines the next connection to be made based on this connection status. a first processor that identifies and controls the line at any time;
a second processor that stores link information and station information of a time division switch and controls the time division switch based on a link control request from the first processor; A connection call characterized in that the first processor in which the failure occurs is restarted while maintaining call continuity based on link information stored in the storage memory of the second processor when the failure occurs. A hold-resume method is obtained.

(実施例) 次に本発明の実施例について図面を参照して説
明する。
(Example) Next, an example of the present invention will be described with reference to the drawings.

第1図は本発明が適用される蓄積プログラム制
御交換機の一例の中継方式図である。
FIG. 1 is a relay system diagram of an example of a storage program control switch to which the present invention is applied.

回線制御プロセツサ(第1のプロセツサ)
LTC1〜LTC3は回線の状態を監視し、状態変
化が生起した際に接続状態をもとにして次に成す
べき接続をプログラムで随時識別し回線を制御す
る中央処理装置であり、回線の収容位置対応に接
続状態番号と接続先収容位置情報から成る接続状
態を記憶する主記憶装置MM1〜3を有してい
る。
Line control processor (first processor)
LTC1 to LTC3 are central processing units that monitor the line status and, when a change in status occurs, identify the next connection to be made based on the connection status using a program and control the line. It has main memory devices MM1 to MM3 that store connection states corresponding to connection state numbers and connection destination accommodation position information.

時分割スイツチ制御プロセツサ(第2のプロセ
ツサ)NMCは回線制御プロセツサLTCからのリ
ンク制御要求をもとに時分割スイツチを制御する
中央処理装置であり、時分割スイツチのタイムス
ロツト対応にスイツチの入側収容位置と出側収容
位置から成るリンク情報及び局情報を記憶する主
記憶装置NM4を有している。また各プロセツサ
は、データ転送バスP−BUSに接続されており、
プロセツサ相互でデータ転送可能な構成となつて
いる。
The time division switch control processor (second processor) NMC is a central processing unit that controls the time division switch based on link control requests from the line control processor LTC. It has a main memory device NM4 that stores link information and station information consisting of the accommodation position and the exit accommodation position. Each processor is also connected to a data transfer bus P-BUS.
The configuration is such that data can be transferred between processors.

第2図は、前記主記憶装置MM1〜MM3に記
憶されている各回線の接続状態メモリの構成図、
第3図は、前記主記憶装置MM4に記憶されてい
る各リンクのリンク情報メモリの構成図である。
FIG. 2 is a configuration diagram of the connection state memory of each line stored in the main storage devices MM1 to MM3;
FIG. 3 is a configuration diagram of the link information memory of each link stored in the main memory device MM4.

第1図において、回線制御プロセツサLTC1
は加入者SUB−AおよびSUB−Bのライン回路
LC1,LC2を、回線制御プロセツサLTC2は加
入者SUB−CおよびSUB−Dのライン回路LC
3,LC4を、回線制御プロセツサLTC3は発信
トランクTRK−EおよびTRK−Fのトランク回
路TRK−1およびTRK−2をそれぞれ収容し、
各回線制御プロセツサの主記憶装置MM1,MM
2,MM3の接続状態メモリには、それぞれの加
入者および発信トランクの接続状態(接続状態番
号,接続先の収容位置情報)が回線収容位置に対
応して記憶されている。
In Figure 1, line control processor LTC1
is the line circuit of subscribers SUB-A and SUB-B
LC1 and LC2 are connected to the line control processor LTC2, and the line control processor LTC2 is connected to the line circuit LC of subscribers SUB-C and SUB-D.
3. LC4, line control processor LTC3 accommodates trunk circuits TRK-1 and TRK-2 of outgoing trunks TRK-E and TRK-F, respectively;
Main memory device MM1, MM of each line control processor
2. In the connection state memory of the MM 3, the connection state (connection state number, connection destination accommodation location information) of each subscriber and outgoing trunk is stored in correspondence with the line accommodation location.

また、時分割スイツチ制御プロセツサNMCの
主記憶装置MM4には、時分割スイツチSWNET
の収容位置を示すリンク情報と、その収容位置に
接続されている端末(ライン回路、トランク回
路)の種別が記憶されている。
In addition, the main memory device MM4 of the time division switch control processor NMC contains the time division switch SWNET
The link information indicating the accommodation position of the terminal and the type of terminal (line circuit, trunk circuit) connected to the accommodation position are stored.

ここでは第1図に示すように、内線相互接続状
態にある加入者SUB−BとSUB−Cのうち、加
入者SUB−Bのライン回路LC2を収容している
回線制御プロセツサLTC1に、例えばメモリこ
ろび等の要因により障害が発生した場合の再開処
理を例に説明する。なお多くの加入者を収容する
大容量電子交換機の回線制御プロセツサは通常冗
長性を有しており、本実施例においても各プロセ
ツサは二重化されているものとする。
Here, as shown in FIG. 1, among subscribers SUB-B and SUB-C in an extension interconnection state, the line control processor LTC1 accommodating the line circuit LC2 of subscriber SUB-B has, for example, a memory. An example of restart processing when a failure occurs due to factors such as a fall will be explained. Note that the line control processors of a large-capacity electronic exchange that accommodates many subscribers usually have redundancy, and it is assumed that each processor is duplicated in this embodiment as well.

回線制御プロセツサLTC1に障害が発生する
と、現用プロセツサは停止し、予備プロセツサ
(図示せず)から障害発生時の接続呼(第1図の
例ではSUB−B)の識別要求をP−SUBを介し
て、時分割スイツチ制御プロセツサNMCに転送
する。この識別要求を受けた時分割スイツチ制御
プロセツサNMCは、主記憶装置MM4に記憶さ
れているリンク情報から接続呼だけを識別し、第
3図に示すようにその接続呼が収容されている時
分割スイツチSWNETの収容位置情報を読出す
(第1図の例では第3図に示すLINK1)。更にこ
の収容位置情報からその収容位置に接続されてい
る端末種別を、主記憶装置MM4に記憶されてい
る局情報から識別し、その端末種別を読出す。リ
ンク情報から読出した時分割スイツチSWNET収
容位置情報と局情報から読出した端末種別情報と
から、回線制御プロセツサLTC1の接続呼の接
続状態を示す所定の接続状態番号に編集する。第
1図の例では、回線制御プロセツサLTC1の接
続呼である加入者SUB−Bの接続状態番号は、
第2図に示すように内線相互接続状態を示す
「1」で、その接続先収容位置は「SUB−C」で
ある。
When a failure occurs in the line control processor LTC1, the active processor stops, and a standby processor (not shown) sends an identification request for the connection call (SUB-B in the example in Figure 1) via P-SUB. and transfers it to the time division switch control processor NMC. Upon receiving this identification request, the time division switch control processor NMC identifies only the connected call from the link information stored in the main memory device MM4, and as shown in FIG. Read the accommodation position information of the switch SWNET (in the example of FIG. 1, LINK1 shown in FIG. 3). Further, based on this accommodation position information, the type of terminal connected to the accommodation position is identified from the station information stored in the main storage device MM4, and the terminal type is read out. A predetermined connection status number indicating the connection status of the connection call of the line control processor LTC1 is edited from the time division switch SWNET accommodating position information read from the link information and the terminal type information read from the station information. In the example of FIG. 1, the connection state number of subscriber SUB-B, which is the connection call of line control processor LTC1, is
As shown in FIG. 2, "1" indicates the extension interconnection state, and the connection destination accommodation position is "SUB-C".

こうして時分割スイツチ制御プロセツサNMC
は、回線制御プロセツサLTC1のすべての接続
呼(第1図の例では加入者SUB−Bのみ)の接
続状態を接続状態番号に編集後、P−BUSを介
して回線制御プロセツサLTC1へ転送する。こ
のデータを受信した回線制御プロセツサLTC1
は、通話状態にある接続呼はそのまま接続状態を
主記憶装置MM1の接続状態メモリに再設定し、
空状態,発呼中,応答待状態にある回線(加入者
ラインおよびトランクライン)は主記憶装置MM
1の接続状態メモリを初期化する。
Thus, the time division switch control processor NMC
edits the connection states of all connected calls (only subscriber SUB-B in the example of FIG. 1) of line control processor LTC1 into connection state numbers, and then transfers the calls to line control processor LTC1 via P-BUS. Line control processor LTC1 that received this data
For the connected call that is in the talking state, the connection state is reset to the connection state memory of the main storage device MM1,
Lines (subscriber lines and trunk lines) that are idle, calling, or waiting for a response are stored in the main memory MM.
1 connection state memory is initialized.

これにより、障害を発生した回線制御プロセツ
サLTC1は正常状態に復旧し、その結果呼の連
続性を保持したまま障害発生による再開処理を完
了し、正常時の呼処理状態に復元する。
As a result, the faulty line control processor LTC1 is restored to a normal state, and as a result, the restart processing due to the fault occurrence is completed while maintaining call continuity, and the call processing state is restored to the normal state.

(発明の効果) 本発明は、以上説明した様に、時分割スイツチ
のリンク情報及び局情報より接続呼の接続状態を
識別する事により、外部記憶装置を設ける事な
く、呼の連続性を保持したまま罹障LTCを再開
できる効果がある。
(Effects of the Invention) As explained above, the present invention maintains call continuity without providing an external storage device by identifying the connection status of a connected call from the link information and station information of a time division switch. It has the effect of allowing the affected LTC to be restarted while the patient is still suffering.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の適用される蓄積プログラム制
御交換機の一例の中継方式図、第2図は主記憶メ
モリに記憶されるライン、トランク等の接続状態
メモリの構成図、第3図は主記憶メモリに記憶さ
れる時分割スイツチのリンク情報メモリの構成図
である。 LTC……回線制御プロセツサ、NMC……時分
割スイツチ制御プロセツサ、MM1〜MM4……
主記憶メモリ、P−BUS……プロセツサ間デー
タ転送バス、SWNET……スイツチネツトワーク
(時分割スイツチ)、LINK1〜LINK4……接続
リンク、LC1〜LC4……ライン回路、TRK1
〜TRK2……トランク回路、SUB−A〜SUB−
D……内線加入者、TRK−E〜TRK−F……発
着信トランク。
Fig. 1 is a relay system diagram of an example of a storage program control exchange to which the present invention is applied, Fig. 2 is a configuration diagram of connection status memory such as lines and trunks stored in the main memory, and Fig. 3 is a diagram of the main memory. FIG. 2 is a configuration diagram of a link information memory of a time division switch stored in a memory. LTC...Line control processor, NMC...Time division switch control processor, MM1 to MM4...
Main memory, P-BUS...Inter-processor data transfer bus, SWNET...Switch network (time division switch), LINK1 to LINK4...Connection link, LC1 to LC4...Line circuit, TRK1
~TRK2...Trunk circuit, SUB-A~SUB-
D... Extension subscriber, TRK-E to TRK-F... Outgoing/incoming trunk.

Claims (1)

【特許請求の範囲】[Claims] 1 蓄積プログラム制御交換機において、回線
(ライン及びトランク)の接続状態を記憶し状態
変化が生起した際にこの接続状態をもとにして次
に成すべき接続をプログラムで随時識別して前記
回線を制御する第1のプロセツサと、時分割スイ
ツチのリンク情報及び局情報を記憶し前記第1の
プロセツサからのリンク制御要求をもとに前記時
分割スイツチを制御する第2のプロセツサとを有
し、前記第1のプロセツサに障害が発生した際に
前記第2のプロセツサの記憶メモリに記憶されて
いるリンク情報をもとに接続呼の収容位置情報と
端末種別情報を識別し、前記接続呼の接続状態を
示す接続状態番号と接続先収容位置を前記第1の
プロセツサに通知し、前記第1のプロセツサは通
話状態にある接続呼に対しそのまま接続状態を再
設定することにより、呼の連続性を保持したまま
前記障害が発生した第1のプロセツサを再開させ
る事を特徴とする接続呼保持再開方式。
1 In a storage program controlled exchange, the connection status of lines (lines and trunks) is stored, and when a change in status occurs, the next connection to be made is identified by a program at any time based on this connection status, and the line is controlled. a second processor that stores link information and station information of a time division switch and controls the time division switch based on a link control request from the first processor; When a failure occurs in the first processor, the accommodation location information and terminal type information of the connected call are identified based on the link information stored in the storage memory of the second processor, and the connection status of the connected call is identified. The first processor is notified of the connection state number indicating the connection state and the connection destination accommodating position, and the first processor maintains call continuity by resetting the connection state of the connected call that is currently in the communication state. A connection call holding/resuming method characterized in that the first processor in which the fault has occurred is restarted while the first processor remains in the state where the fault has occurred.
JP15684684A 1984-07-27 1984-07-27 Holding and resuming method of connection call Granted JPS6135696A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15684684A JPS6135696A (en) 1984-07-27 1984-07-27 Holding and resuming method of connection call

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15684684A JPS6135696A (en) 1984-07-27 1984-07-27 Holding and resuming method of connection call

Publications (2)

Publication Number Publication Date
JPS6135696A JPS6135696A (en) 1986-02-20
JPH0344718B2 true JPH0344718B2 (en) 1991-07-08

Family

ID=15636649

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15684684A Granted JPS6135696A (en) 1984-07-27 1984-07-27 Holding and resuming method of connection call

Country Status (1)

Country Link
JP (1) JPS6135696A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58141063A (en) * 1982-02-17 1983-08-22 Nec Corp Save method for call information

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58141063A (en) * 1982-02-17 1983-08-22 Nec Corp Save method for call information

Also Published As

Publication number Publication date
JPS6135696A (en) 1986-02-20

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