JPH0344261A - Signal output circuit for image scanner - Google Patents

Abstract

PURPOSE:To reduce number of signal transmission lines connecting an image scanner and a main body and to reduce the scale of the hardware and software of the main body side by adding a circuit means to the image scanner side to output a START signal synchronized to the main body. CONSTITUTION:Synchronizing circuit means 1-3 for synchronizing a start pulse (1) and an encoder pulse (2) are provided to an image scanner and only a start pulse (7) valid when the encoder pulse (2) only exists is sent. The synchronizing circuit means 1-3 output the start pulse (1) to a transmission line only when the encoder pulse (2) exists and the start pulse (1) is masked when no encoder pulse (2) exists to block the transmission. Thus, it is not required to send the encoder pulse (2) to the main body and then a line for sending the encoder pulse is not required and the provision of the hardware and software for synchronization is not required to the main body.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image scanner, and more particularly to a signal output circuit for an image scanner configured to reduce the number of output signal lines.

[Conventional technology]

In handheld image scanners, etc., the main scanning is performed by a self-scanning line sensor, and the sub-scanning is performed by the movement of the operator's device (handset) to read the image on the medium and send it to the main body (host computer, etc.). , at least a start signal, a clock pulse for timing data signal reading, and a data (
A total of 7 pulses (this count pulse can be used as a clock pulse), data signal, encoder pulse, +VT source and ground (6 pulses if used as both a count pulse and a clock pulse) line was needed. Note that a color image scanner requires 9 lines (8 lines).

Since it is necessary to synchronize the start signal and encoder pulses on the main body side, software and circuits for this are required on the main body side.

FIG. 4 is an explanatory diagram of the principle of an image scanner according to the prior art, in which (a) is a schematic block diagram and (b) is an explanatory diagram of operation timing, where 10 in <a> is a COD
, a self-scanning line sensor such as a MOS type, 11 a rotary encoder (hereinafter simply referred to as an encoder) that generates a reference signal for a sub-scanning signal, 12 a controller, 13, 14
゜15, 16, and 17 are output lines that send signals to the main unit, respectively: start signal (START), count signal (COUNT), clock signal (CLOCK), data signal (DATA), and encoder signal (ENCODER).
lines, and 18.19 supply power from the main unit.
They are a 12V line and a ground line (GND).

The operation of the above configuration is as shown in FIG.
Based on the generation of T), the image is read and scanned at the timing of the clock pulse (CLOCK). but,
In reality, a two-dimensional image cannot be read unless the handset is moved and an encoder pulse, which is a sub-scanning signal, is generated, so the main body must synchronize the two so that only the start pulse after the encoder pulse is valid. Since it is necessary to take the start pulse (START)
and an encoder pulse (ENCODER) are independently transmitted to the main body side.

[Problem to be solved by the invention]

In the above conventional technology, as shown in Figure 4, at least seven (six) lines are required (particularly in the case of a color scanner, data lines are used to transmit red, blue, and green color signals). Since 3 pieces are required, it is 9 pieces (8 pieces), and
This method requires software and circuitry for the synchronization processing on the main body side, which has the drawback that the configuration is complicated and the burden on the main body side is large.

SUMMARY OF THE INVENTION An object of the present invention is to provide a signal output circuit for an image scanner that eliminates the drawbacks of the prior art described above, reduces the number of signal lines connecting the scanner and the main body, and reduces the burden on hardware and software on the main body. It is about providing.

[Means to solve the problem]

The above object is achieved by providing the image scanner with a synchronization circuit means for synchronizing the start pulse and the encoder pulse, and transmitting only the start pulse that is valid during the period when the encoder pulse exists.

[Effect]

The synchronization circuit means outputs a start pulse to the transmission line only when the encoder generates an encoder pulse,
During periods when encoder pulses are not present, the start pulses are masked and transmission of start pulses is prevented, so there is no need to transmit encoder pulses to the main body.Therefore, there is no need for a line for transmitting encoder pulses, and There is no need to provide hardware and software for the synchronization.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 is a detailed explanatory diagram of the present invention, (a) is a block diagram showing the outline of the image scanner, (b) is an operation timing diagram, and in (a) 10 is a CCD, MO
Self-scanning line sensor consisting of S, etc., 11 is an encoder, 12 is a controller, 13, 14, 15, 16 are 5TART, C0UNT, CLOCK, DATA, respectively.
Output line for transmission of each signal, 18.19 is +12V
, the GND line.

The configuration and operation in this figure are almost the same as those shown in FIG. be.

As shown in FIG. 4(b), the controller 12 outputs only the 5TART pulses (A) and (C) during the period when the ENCODER pulse shown in FIG. 5TART during no pulse period
Pulses (mouth) and (d) do not output, that is, 5
Only when the TART pulse and the ENCODER pulse are synchronized, the 5TART pulse is transmitted to the main body side, and the 5TART pulse is masked during the period when the ENCODER pulse is not present. This eliminates the need to send an ENCODER pulse to the main unit, and
A line for DER transmission becomes unnecessary.

FIG. 1 is a block diagram showing the configuration of an embodiment of the signal output circuit of an image scanner according to the present invention, in which 1 is a rising edge detection circuit (first edge detection circuit), 2 is a falling edge detection circuit (second edge detection circuit), and 2 is a falling edge detection circuit (second edge detection circuit). edge detection circuit), 3 is a flip-flop circuit, 4 is an AND gate, 5 is an inverter, 6 is a 5TART
Pulse input terminal, 7 is ENCODER pulse input terminal,
8 is a 5TART pulse output terminal.

FIG. 2 is a timing diagram for explaining the operation of FIG. 1, and 1 to 2 indicate waveforms of portions with the same reference numerals in FIG. 1, respectively.

The operation shown in FIG. 1 will be explained below along with FIG. 2.

The 5TART pulse from the 5TART pulse input terminal 6 is applied to the rising edge detection circuit 1 and the AND gate (gate circuit) 4. On the other hand, the ENCODER pulse (2) from the ENCODER pulse input terminal 7 is inverted by the inverter 5 and applied to the fall detection circuit 2 as an inverted signal (2).

The rising edge detection circuit 1 and the falling edge detection circuit 2 each detect the edge of the input signal pulse, and apply the detection signals (2) and (2) to the flip-flop circuit 3.

The rising detection signal (2) of the 5TART pulse is applied to the set input S of the flip-flop circuit 3, and the falling detection signal (2) of the inverted signal of the ENCODER pulse is applied to the reset input R of the flip-flop circuit 3.

The Q output ■ of the flip-flop circuit 3 is applied to the AND gate 4, and the AND output ■ is sent out to the output line as a 5TART pulse synchronized with the ENCODER pulse.

As shown in FIG. 2, the flip-flop circuit 3 is
Since it is reset by the falling detection signal of the CODER pulse inversion signal ■ and set by the rising detection signal ■ of the 5TART pulse, the AND of the output signal ■ and the 5TART pulse ■ is established during the period when the ENCODER pulse ■ exists. . That is, the 5TART pulse is masked during the period in which the ENCODER pulse does not exist. therefore,
The output of the AND gate becomes only the 5TART pulse synchronized with the ENCODER pulse.

In this way, the 5TART pulse output from the image scanner to the main body is always synchronized with the ENCODER pulse, and there is no need to perform processing to synchronize the two on the main body, and the E, N COD E R pulse No transmission line is required, and the burden on the main body can be reduced.

Note that edge detection of the start pulse and encoder pulse, which are input to the flip-flop circuit 3, is not limited to the method of detecting the rising edge and falling edge as in the above embodiment, but can detect either the falling edge or the rising edge. The object of the present invention can be achieved as long as it detects this or the arrival of each of these pulses. Furthermore, the circuit means provided on the image scanner side can be easily configured with a gate array or the like, and does not involve a large increase in cost.

〔Effect of the invention〕

As explained above, according to the present invention, synchronized 5TART signals are output to the main body by simply adding circuit means of a simple configuration to the image scanner, so that the image scanner and the main body can be connected. This makes it possible to reduce the number of signal transmission lines, as well as the hardware and software on the main body side.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the image scanner signal output circuit of the present invention, FIG. 2 is a timing diagram for explaining the operation of FIG. 1, and FIG. 3 is a detailed diagram of the present invention. FIG. 4 is an explanatory diagram of the principle of an image scanner according to the prior art. 1...Rise detection circuit (first edge detection circuit),
2...Falling detection circuit (second edge detection circuit),
3...Flip-flop circuit, 4...AND gate (gate circuit), 5...Inverter, 6...
・5TART pulse input terminal, 7...ENCODE
R pulse input terminal, 8...5TART pulse output terminal. ■ Second meal

Claims (1)

[Claims] A first edge detection circuit that detects a rising or falling edge of a start pulse, a second edge detecting circuit that detects a rising edge or a falling edge of an encoder pulse, and an output of the first edge detecting circuit and a second edge detection circuit. It consists of a flip-flop circuit that receives the output of the circuit as an input, and a gate circuit for masking the start pulse with the output of the flip-flop circuit. A signal output circuit for an image scanner, characterized in that it outputs a signal.