JPH0343835A - Paralleled process system - Google Patents

Abstract

PURPOSE:To automatically secure and release the necessary processors with high efficiency by producing automatically an instruction train which secures the processors in number necessary for production of an object program and then releases these processors when they are not required. CONSTITUTION:In an compiler 2 a source program 1 is analyzed by an analyzing means 21 for production of an intermediate text 24 and a paralleled means 22 analyzes the text 24 to extract the parts which can work in parallel with each other for production of a paralleled intermediate text 25. At the same time, the compiler 2 decides the number of processors which are actiated in parallel with each other. An object program generating means 23 produces an instruction train which secures the processor in number decided by the means 22 and releases these processors when they are not required. A linker 3 decides the number of processors to be secured and buries them into a program. An executing program generating means 32 connects the necessary object programs to each other and produces an execution mode program 6. In such a constitution, the processors are effectively secured and released in a parallel process and many processors can be effectively used.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a parallel processing method for processing a predetermined program in parallel using a plurality of processors.

[Prior Art] Conventionally, when a program was to be processed in parallel using multiple processors, the allocation/release of the processors was left to the task management function of the system when the well-known multitasking function was used.

There are also systems in which a user or system can secure a fixed processor to perform low-overhead parallel processing.

[Problem to be solved by the invention]

However, the method using the multitasking function has a problem in that the overhead in system task management is large and performance is poor when the amount of calculations to be processed in parallel is small.

In addition, in systems where the user or system secures a fixed number of processors, it is necessary to secure/release processors over a wide range in order to reduce the overhead of securing/releasing processors, which reduces the efficiency of processor usage. Furthermore, it is difficult to optimally allocate processors because the entire program must be examined to decide when to reserve/release processors.

The present invention has improved the conventional drawbacks, and its purpose is to improve the efficiency of securing/releasing processors during parallel processing, to make effective use of a large number of processors, and to significantly reduce the overhead of securing/releasing processors. The object of the present invention is to provide a parallel processing method that can reduce the number of parallel processes.

[Means for Solving the Problems] The parallel processing method of the present invention includes a compiler that inputs a source program and generates a target program that can be run on a plurality of processors, and a compiler that inputs the target program and generates a runtime program. The compiler has an analysis means that analyzes a source program and generates an intermediate text, and an analysis means that analyzes the intermediate text and extracts a part that can be operated in parallel, and generates a parallelized intermediate text. parallelization means for determining the number of processors to be operated in parallel;
Generates a target program from the parallelization intermediate text, generates instructions to secure the number of processors determined by the parallelization means, and releases the processors when they are no longer needed. and a target program generating means for generating an instruction sequence, the linker checks the target program associated with the target program for all target program programs, and selects an appropriate number of processors from among the number of processors set by the compiler. The present invention includes means for determining the number of processors to be secured in the program and embedding it in the program, and runtime program generation means for combining necessary target programs and generating a runtime program.

[Function] In the compiler, the analysis means analyzes the source program to generate intermediate text, the parallelization means analyzes the intermediate text, extracts parts that can be operated in parallel, and generates parallelized intermediate text. Determine the number of processors to operate in parallel. Thereafter, the target program generating means generates the target program from the parallelized intermediate text, but at this time, if the number of processors determined by the parallelizing means is not secured at the time when the program is required, it secures this. In addition, when a processor is reserved in a program, an instruction sequence is generated such that the processor is released when the processor is no longer needed by the program. In the linker, the number of processors determining means determines the appropriate number of processors set by the compiler as the number of processors to be secured by the program,
The program is embedded in the program, and a runtime program generation means combines necessary target programs to generate a runtime program.

〔Example〕

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a system to which the parallel processing method of the present invention is applied.

In FIG. 1, the compiler 2 includes a source program l
an analysis unit 21 that reads and parses the syntax to generate an intermediate text 24, and a parallelization unit 22 that analyzes the parallelism of the source program 1 from the intermediate text 24 and generates a parallelized intermediate text 25 based on the analysis result. , and a target program generation unit 23 that generates the target program 4 from the parallelized intermediate text 25. The parallelization unit 22 further includes a parallelism analysis unit 221 that analyzes the parallelism of the program and generates parallelized intermediate text, and a processor number determination unit 2 that determines the optimal number of processors to operate in parallel.
22, and the target program generation section 23 has a processor reservation instruction string generation section 231 and a normal instruction generation section 2.
32. Processor reservation instruction generation unit 231
If the number of processors determined by the program requires the number of processors determined by the parallelization unit 22 is not secured at the time, the processors are secured;
If the program has secured the processor, it will generate an instruction sequence that uses that processor, and if the program has secured the processor, it will generate an instruction sequence that will release the processor when it is no longer needed by the program. The normal instruction string generation unit 232 is designed to generate a normal instruction string.

The linker 3 also includes a processor number determination section 31 and a runtime program generation section 32. The processor number determination unit 31 reads the target program 4 and refers to the number of processors secured by the target program 4 from the target program 4. A processor that examines other target programs 5, including the reference target program and the reference target program, and secures an appropriate number of processors for the program from among the number of processors set by the processor reservation instruction string generation unit 231. The runtime program generation unit 32 combines necessary target programs and generates the runtime program 6.

Next, parallel processing in such a configuration will be specifically explained using FIGS. 2 and 3.

FIG. 2 shows programs A, B, and programs to which this embodiment is applied.
C and BB are shown, and in FIG.
= 1'' means that program A requires one processor, n b = 3'' means that program B requires three processors, nc = 1'' means that program C requires one processor, and ``nbb = 4''. indicates that program BB requires four processors.

Further, program A calls program B and program C, and program B calls program BB. Further, program B and program BB include a parallel execution portion, that is, a portion that uses a plurality of processors.

Note that FIG. 3 shows the runtime program 6 generated based on FIG. 2.

The compiler 1 first reads the programs shown in FIG. 2 one by one and generates intermediate texts 1 to 24 by the analysis section 21. The parallelism analysis unit 221 in the parallelization unit 22 detects, for example, a parallel execution portion of program B, and generates parallelized intermediate text 25.

In addition, the number of processors at the time of parallelization is determined by the number of processors determining unit 22.
2, it is determined that "n b = 3". The target program generation unit 23 generates an instruction sequence for securing a processor, for example, "get" of program A in FIG. 3, and an instruction sequence for releasing a processor, for example, "r" for program A in FIG.
"elease" is inserted by the processor reservation instruction string generating section 231 before and after the parallel execution part and the external program call.When the target program 4 is generated by the normal instruction string generating section 232, it is passed to the linker 3.

The processor number determining unit 31 of the linker 3 inputs the target program for the program A in FIG. 2, for example, and checks the programs B and C1 called from the program A, and the program BB called from the program B. Here, program A is ti, program B is 3,
Since program C requests 1 processor and program BB requests 4 processors, for example, 4 processors are secured for program A to prevent requests for additional processors from occurring in the future. Determine the number of processors. Further, the determined number is set in the program by the runtime program generation unit 32. After performing the above processing on the input target program, the runtime program generation unit 32 combines the target programs and generates a third
A runtime program 6 as shown in the figure is generated.

When the program shown in FIG. 3 is executed, after a processor is secured in program A, even if a processor reservation request is made in program B, it is ignored. Further, even if a processor release request is made by program B, it is ignored. Processor reservation/release requests in program BB are similarly ignored. When execution of programs B and BB is completed and program A issues a processor release request, since program A is the program that has secured the processor, the request is accepted and the processor is released.

Note that although program C is called in program A, since program C is not executed in parallel, the processor is not secured/released.

(Effect of the invention) As explained above, in the present invention, in the compiler,
The linker automatically generates an instruction sequence that allocates the necessary number of processors when generating the target program and releases them when they are no longer needed. Since the appropriate number of processors is secured by the program as the number of reserved processors, the required processors can be automatically and efficiently secured/released, thereby making effective use of a large number of processors. This has the effect of automatically reducing the overhead of securing/releasing processors.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a diagram showing an example of a program to which the present invention is applied, and FIG. 3 is a diagram showing an example of a program to which the present invention is applied. FIG. 2 is a diagram showing the state of the program. In FIG. 1, 1...source program, 2...
Compiler, 3... Linker, 4... Target program, 5... Other target program, 6... Runtime program, 21... Analysis section, 22... Parallelization section, 23.
...Objective program generation unit, 24...Intermediate text,
25 parallelization intermediate text, 31... processor number determination unit, 32... runtime program generation unit, 221...
Parallelism analysis section, 222...Prosensor number determination section, 23
1... Processor reservation instruction string generation unit, 232... Normal instruction generation unit.

Claims (1)

[Claims] 1. It has a compiler that inputs a source program and generates a target program that can be run on multiple processors, and a linker that inputs the target program and generates a runtime program, and the compiler analyzes the source program. a parallelizing means that analyzes the intermediate text to extract parts that can be operated in parallel, generates a parallelized intermediate text, and determines the number of processors to operate in parallel; Generate a target program from text, and at this time generate an instruction sequence that secures the number of processors determined by the parallelization means, and also generate an instruction sequence that releases the processors when they are no longer needed. and a target program generating means for generating a target program, the linker checks target programs related to the target program for all target programs,
A means for determining the number of processors to be set in the program by determining an appropriate number of processors set by the compiler as the number of processors to be secured in the program, and a means for determining the number of processors to be embedded in the program, and a runtime program for generating a runtime program by combining a necessary target program. A parallel processing method characterized by comprising: program generation means.