JPH0342725Y2 - - Google Patents

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Publication number
JPH0342725Y2
JPH0342725Y2 JP14208284U JP14208284U JPH0342725Y2 JP H0342725 Y2 JPH0342725 Y2 JP H0342725Y2 JP 14208284 U JP14208284 U JP 14208284U JP 14208284 U JP14208284 U JP 14208284U JP H0342725 Y2 JPH0342725 Y2 JP H0342725Y2
Authority
JP
Japan
Prior art keywords
conductor
inductance element
delay line
distributed constant
width dimension
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP14208284U
Other languages
Japanese (ja)
Other versions
JPS6157607U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP14208284U priority Critical patent/JPH0342725Y2/ja
Publication of JPS6157607U publication Critical patent/JPS6157607U/ja
Application granted granted Critical
Publication of JPH0342725Y2 publication Critical patent/JPH0342725Y2/ja
Expired legal-status Critical Current

Links

Description

【考案の詳細な説明】[Detailed explanation of the idea]

〔産業上の利用分野〕 本考案は超高周波帯において良好な遅延特性の
得られる分布定数型電磁遅延線の改良に関する。 〔従来の技術〕 この種の分布定数型電磁遅延線としては、例え
ば、板状のアース電極の外周に誘電体層を形成
し、この誘電体層の周りに導体を複数ターン単層
ソレノイド状にスペース巻きしてなる構成を有す
るものがある。 本考案者は、このような分布定数型電磁遅延線
について検討を加えたところ、良好な遅延特性を
確保し、かつ小型化およびコストダウンを図るた
めに、さらに改良を加える余地のあることが分か
つた。 〔考案が解決しようとする問題点〕 本考案はこのような状況の下になされたもの
で、小型かつ安価で、超高周波帯における良好な
遅延特性が得られる分布定数型電磁遅延線の提供
を目的とする。 〔問題点を解決するための手段〕 この問題点を解決するために本考案は、幅寸法
Wとこれにより十分小さい厚み寸法Tで導体を複
数ターン所定のピツチPで単層ソレノイド状にス
ペース巻きして偏平なインダクタンス素子を形成
し、誘電体層を介してアース電極をその導体に対
向配置させてなる分布定数型電磁遅延線であつ
て、各ターンにおける略半ターン進みかつその幅
寸法W側に位置する導体の位置が、そのインダク
タンス素子の軸方向に0・5ピツチより大きく進
められるとともに、その導体がインダクタンス素
子の軸方向に傾けて巻かれて構成されている。 〔作用〕 このような本考案の構成によれば、各ターンに
おける略半ターン進んだ導体の位置が、インダク
タンス素子の軸方向に0・5ピツチより大きく進
められているので、インダクタンス素子を形成す
るその導体間に生じる正負の結合に関し、隣合う
導体間で生じるじる正の結合に対して離れた導体
間で生じる負の結合の影響が相対的に強まる。 〔実施例〕 以下、本考案の詳細を説明する。 第1図および第2図は本考案に係る分布定数型
電磁遅延線の一実施例を示す正面図および側面図
である。 両図において、細長い板状のアース電極1の外
周には誘電体層としてふつ素樹脂層3が形成さ
れ、幅方向の寸法W(以下Wという)が厚み方向
の寸法T(以下Tという)に対して十分大きな偏
平で細長いボビン5が形成されている。 このボビン5の外周には、導体条7がピツチP
で複数ターン単層ソレノイド状にスペース巻きさ
れてインダクタンス素子9が形成され、このイン
ダクタンス素子9並びにこのインダクタンス素子
9の導体条7とアース電極1間に形成される静電
容量によつて分布定数型電磁遅延線が構成されて
いる。 図中の符号WおよびTは正確にボビン5を挟ん
で対向する導体条7の中心間の距離であり、導体
条7は両W側にてインダクタンス素子9の長手方
向に各々直交し、かつ並行に形成されている。 そして、インダクタンス素子9の導体条7は、
一方のW側(図中上面側)に位置する各導体条7
aから略半ターン進んだ各導体条7b(図中下面
側)が、インダクタンス素子9の軸方向に各導体
条7aより0・5ピツチ+Bだけ進んだ位置に配
置されている。 すなわち、各導体条7のターン内において、ボ
ビン5を挟んで対向する導体条7a,7bがイン
ダクタンス素子9の軸方向に0・5ピツチ+Bず
れている。換言すれば、偏平なインダクタンス素
子9の巻線ピツチPに対して半ターンピツチが巻
線ピツチPの半分より大きくなるようにインダク
タンス素子9の軸方向に傾けて導体条7が巻かれ
ている。 このように構成された分布定数型電磁遅延線
は、上述したBの値を適当に選定することによ
り、後述する利点を有するとともに良好な遅延特
性を得ることが可能である。 本考案者は、従来と本考案に係る分布定数型電
磁遅延線について、厚み0・07mm、幅15mmのアー
ス電極1の外周に厚さ0・7mmのふつ素樹脂層3
を形成し、幅18mmのインダクタンス素子9が得ら
れるようにその外周に厚さ0・035mm、幅2mmの
導体条7を単層ソレノイド状にピツチP=3mmで
10ターン形成し、Bの値をOから順次大きくして
実験した。 すると、第3図A〜Cに示すパルス応答波形が
測定されるとともに、遅延時間(以下tdとする)、
立ち上がり時間(以下trとする)および特性イン
ピーダンスzo(以下zoとする)として以下の表に
示す値が得られた。
[Industrial Application Field] The present invention relates to an improvement of a distributed constant electromagnetic delay line that can obtain good delay characteristics in an ultra-high frequency band. [Prior Art] This type of distributed constant electromagnetic delay line is constructed by, for example, forming a dielectric layer around the outer periphery of a plate-shaped ground electrode, and forming a plurality of turns of a conductor around this dielectric layer in the form of a single-layer solenoid. Some have a space-wound configuration. After studying this kind of distributed constant electromagnetic delay line, the inventor found that there is room for further improvements in order to ensure good delay characteristics and to reduce size and cost. Ta. [Problems to be solved by the invention] The present invention was made under these circumstances, and aims to provide a distributed constant electromagnetic delay line that is small, inexpensive, and has good delay characteristics in the ultra-high frequency band. purpose. [Means for solving the problem] In order to solve this problem, the present invention space-wraps a conductor in a single-layer solenoid shape with multiple turns of a width dimension W and a sufficiently small thickness dimension T at a predetermined pitch P. This is a distributed constant electromagnetic delay line in which a flat inductance element is formed, and a ground electrode is arranged opposite to the conductor through a dielectric layer, and each turn advances approximately half a turn and its width dimension W side. The position of the conductor located at is advanced by more than 0.5 pitch in the axial direction of the inductance element, and the conductor is wound at an angle in the axial direction of the inductance element. [Function] According to the configuration of the present invention, the position of the conductor advanced by approximately half a turn in each turn is advanced by more than 0.5 pitch in the axial direction of the inductance element, so that the conductor can be formed into an inductance element. Regarding positive and negative coupling occurring between conductors, the influence of negative coupling occurring between distant conductors is relatively stronger than the positive coupling occurring between adjacent conductors. [Example] The details of the present invention will be explained below. 1 and 2 are a front view and a side view showing an embodiment of a distributed constant electromagnetic delay line according to the present invention. In both figures, a fluorine resin layer 3 is formed as a dielectric layer on the outer periphery of an elongated plate-shaped earth electrode 1, and the width direction dimension W (hereinafter referred to as W) becomes the thickness direction dimension T (hereinafter referred to as T). In contrast, a sufficiently large flat and elongated bobbin 5 is formed. On the outer periphery of this bobbin 5, a conductor strip 7 is arranged at a pitch P.
The inductance element 9 is formed by space-winding a plurality of turns in the shape of a single-layer solenoid, and the distributed constant type An electromagnetic delay line is configured. The symbols W and T in the figure are exactly the distances between the centers of the conductor strips 7 facing each other with the bobbin 5 in between, and the conductor strips 7 are perpendicular to the longitudinal direction of the inductance element 9 on both W sides, and parallel to each other. is formed. The conductor strip 7 of the inductance element 9 is
Each conductor strip 7 located on one W side (top side in the figure)
Each conductor strip 7b (lower surface side in the drawing), which has advanced approximately half a turn from a, is arranged at a position that has advanced 0.5 pitch+B from each conductor strip 7a in the axial direction of the inductance element 9. That is, within the turn of each conductor strip 7, the conductor strips 7a and 7b facing each other with the bobbin 5 in between are shifted by 0.5 pitch +B in the axial direction of the inductance element 9. In other words, the conductor strip 7 is wound at an angle in the axial direction of the inductance element 9 so that the half-turn pitch is larger than half of the winding pitch P of the flat inductance element 9. The distributed constant electromagnetic delay line configured in this manner has the advantages described below and can obtain good delay characteristics by appropriately selecting the value of B described above. The inventor of the present invention has proposed a fluorine resin layer 3 with a thickness of 0.7 mm on the outer periphery of a ground electrode 1 with a thickness of 0.07 mm and a width of 15 mm for the distributed constant type electromagnetic delay line according to the conventional and the present invention.
A conductor strip 7 with a thickness of 0.035 mm and a width of 2 mm is formed on the outer periphery of the inductance element 9 with a pitch of P=3 mm in the form of a single layer solenoid so as to obtain an inductance element 9 with a width of 18 mm.
An experiment was conducted by forming 10 turns and increasing the value of B sequentially from O. Then, the pulse response waveforms shown in FIGS. 3A to 3C are measured, and the delay time (hereinafter referred to as td),
The values shown in the table below were obtained for the rise time (hereinafter referred to as tr) and the characteristic impedance zo (hereinafter referred to as zo).

〔考案の効果〕[Effect of idea]

以上説明したように本考案の電磁遅延線は、幅
寸法Wおよびこれにより十分小さい厚み寸法Tで
導体が偏平に巻かれたインダクタンス素子につい
て、各ターンにおける半ターン進みその幅寸法W
側の導体位置がインダクタンス素子の軸方向に
0・5ピツチより大きく進められてインダクタン
ス素子の軸方向に斜めになるように巻かれた構成
としたから、良好な遅延特性を有し、小型かつ安
価である。
As explained above, the electromagnetic delay line of the present invention advances by half a turn in each turn with respect to an inductance element in which a conductor is wound flat with a width dimension W and a sufficiently small thickness dimension T.
Since the conductor position on the side is advanced by more than 0.5 pitch in the axial direction of the inductance element and wound diagonally in the axial direction of the inductance element, it has good delay characteristics, is small and inexpensive. It is.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図および第2図は本考案に係る分布定数型
電磁遅延線の一実施例を示す正面図(一部断面で
示す)および側面図、第3図A〜Cは分布定数型
電磁遅延線による出力パルス波形図、第4図およ
び第5図は本考案に係る分布定数型電磁遅延線の
他の実施例を示す正面図(一部断面で示す)であ
る。 1,19……アース電極、3,17……誘電体
層(ふつ素樹脂層)、5,11……ボビン、7,
13……導体(導体条)、9,15……インダク
タンス素子。
1 and 2 are a front view (partially shown in cross section) and a side view showing an embodiment of a distributed constant electromagnetic delay line according to the present invention, and FIGS. 3A to 3C are distributed constant electromagnetic delay lines. FIGS. 4 and 5 are front views (partially shown in section) showing other embodiments of the distributed constant electromagnetic delay line according to the present invention. 1, 19... Earth electrode, 3, 17... Dielectric layer (fluorine resin layer), 5, 11... Bobbin, 7,
13... Conductor (conductor strip), 9, 15... Inductance element.

Claims (1)

【実用新案登録請求の範囲】 幅寸法Wとこれより十分小さい厚み寸法Tで導
体が複数ターン所定のピツチPで単層ソレノイド
状にスペース巻きされた偏平なインダクタンス素
子と、 誘電体層を介して前記導体に対向配置されたア
ース電極とを具備してなる分布定数型電磁遅延線
において、 各ターンにおける略半ターン進みかつ前記幅寸
法W側に位置する前記前記導体の位置が、前記イ
ンダクタンス素子の軸方向に0・5ピツチより大
きく進められ、前記導体が前記軸方向に傾けて巻
かれてなることを特徴とする分布定数型電磁遅延
線。
[Scope of Claim for Utility Model Registration] A flat inductance element in which a conductor is space-wound in a single-layer solenoid shape with a plurality of turns at a predetermined pitch P, with a width dimension W and a thickness dimension T that is sufficiently smaller than the width dimension W, and a dielectric layer interposed therebetween. In a distributed constant electromagnetic delay line comprising a ground electrode disposed opposite to the conductor, the position of the conductor that is approximately half a turn ahead of each turn and located on the width dimension W side is such that the position of the conductor is located on the width dimension W side of the inductance element. 1. A distributed constant electromagnetic delay line, characterized in that the conductor is wound in an axial direction with a pitch greater than 0.5, and the conductor is wound at an angle in the axial direction.
JP14208284U 1984-09-18 1984-09-18 Expired JPH0342725Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14208284U JPH0342725Y2 (en) 1984-09-18 1984-09-18

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14208284U JPH0342725Y2 (en) 1984-09-18 1984-09-18

Publications (2)

Publication Number Publication Date
JPS6157607U JPS6157607U (en) 1986-04-18
JPH0342725Y2 true JPH0342725Y2 (en) 1991-09-06

Family

ID=30700414

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14208284U Expired JPH0342725Y2 (en) 1984-09-18 1984-09-18

Country Status (1)

Country Link
JP (1) JPH0342725Y2 (en)

Also Published As

Publication number Publication date
JPS6157607U (en) 1986-04-18

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