JPH0342513A - Differential transformer conversion system - Google Patents

Differential transformer conversion system

Info

Publication number
JPH0342513A
JPH0342513A JP17703689A JP17703689A JPH0342513A JP H0342513 A JPH0342513 A JP H0342513A JP 17703689 A JP17703689 A JP 17703689A JP 17703689 A JP17703689 A JP 17703689A JP H0342513 A JPH0342513 A JP H0342513A
Authority
JP
Japan
Prior art keywords
output
circuit
differential transformer
subtraction
value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17703689A
Other languages
Japanese (ja)
Inventor
Nobuyoshi Yamazaki
宣悦 山崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
REIDEITSUKU KK
Sakata Denki Co Ltd
Original Assignee
REIDEITSUKU KK
Sakata Denki Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by REIDEITSUKU KK, Sakata Denki Co Ltd filed Critical REIDEITSUKU KK
Priority to JP17703689A priority Critical patent/JPH0342513A/en
Publication of JPH0342513A publication Critical patent/JPH0342513A/en
Pending legal-status Critical Current

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  • Transmission And Conversion Of Sensor Element Output (AREA)

Abstract

PURPOSE:To output the difference value between input voltages as it is as the measured output without dividing it by a reference value by using a reference voltage source, an error amplifier, and a multiplying circuit to fix the sum of inputs of a subtracting circuit to a set value. CONSTITUTION:An error amplifier 21 which amplifies the difference voltage V1 and the output voltage of a synchronous detecting circuit 16 on the addition to a voltage higher by at least by one figure, and a multiplying circuit 22 which multiplies the output of this amplifier 21 by the oscillation output of an oscillating circuit 11 and sends the result to the primary coil of a differential transformer 13 as the output signal from the transmission side are additionally provided to this system, and the output of the circuit 16 on the subtraction side is outputted as a measured output VP. That is, the sum of inputs VA and VB of a subtracting circuit 15 is fixed to a set value to accurately and stably output the difference value between voltages VA and VB as the output VP without dividing it by a reference value V0.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は差動トランスを用いた変換器のの信号変換方式
に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a signal conversion system for a converter using a differential transformer.

[従来技術] 従来、差動トランスを用いた変換器を製作する場合、変
換回路と差動トランスを同一容器内に組込む方式が多く
用いられているが、土木用計器のように回収不能な状態
で長期間使用される計器に於いては、信頼性の点からも
電子回路は地上に置くことが望ましい。このことから、
差動トランスと変換回路の間にはセンサケーブルが介在
することとなり、このケーブルの抵抗が差動トランスの
変換精度に影響を与えることとなる。このため差動トラ
ンスの2次コイル出力VAおよびVBから■A+VBお
よびvA−VBの信号ヲ作す、vAまたはVBの信号に
よって同期検波を行い、除算回路におイテ(VA −V
a ) / (VA 十Vs ) (7)演算を行って
ケーブルの抵抗等に影響されない出力を得る方式が用い
られている。
[Prior art] Conventionally, when manufacturing a converter using a differential transformer, the conversion circuit and the differential transformer are often assembled in the same container, but this method is often used in cases where the converter is not recoverable like civil engineering instruments. For instruments that will be used for long periods of time, it is desirable to place the electronic circuits on the ground from the standpoint of reliability. From this,
A sensor cable is interposed between the differential transformer and the conversion circuit, and the resistance of this cable affects the conversion accuracy of the differential transformer. Therefore, from the secondary coil outputs VA and VB of the differential transformer, A+VB and vA-VB signals are generated. Synchronous detection is performed using the vA or VB signal, and input to the divider circuit (VA-V
a) / (VA + Vs) (7) A method is used in which calculation is performed to obtain an output that is not affected by cable resistance or the like.

第2図は上記f) (VA −Ve ) / (VA 
+VB )の演算を行う方式の構成を示す図である。発
振回路11の出力電圧はバッファアンプ12およびケー
ブルの抵抗「を介して差動トランス13の1次側に加え
られ、2次側に生じた2つの2次出力信号はケーブル抵
抗「を介して加算回路14および減算回路15へ入力電
圧vAとV、として加えられ、加算回路で得られた加算
値vA+VB及び減算回路で得られた減算値V^−V、
は同期検波回路16及び17でそれぞれ同期がとられ、
同期のとられた加算値及び減算値は除算回路18で除算
され、測定出力(VA −Va ) / (VA +V
!1 )が得られる構成に成っている。
Figure 2 shows the above f) (VA - Ve ) / (VA
+VB ) is a diagram showing the configuration of a method for calculating. The output voltage of the oscillation circuit 11 is applied to the primary side of the differential transformer 13 via the buffer amplifier 12 and the cable resistance, and the two secondary output signals generated on the secondary side are added via the cable resistance. The input voltages vA and V are applied to the circuit 14 and the subtraction circuit 15, and the addition value vA+VB obtained by the addition circuit and the subtraction value V^-V obtained by the subtraction circuit,
are synchronized by synchronous detection circuits 16 and 17, respectively,
The synchronized addition value and subtraction value are divided by the division circuit 18, and the measurement output (VA - Va) / (VA +V
! 1).

この方式によれば、測定出力として2つの2次出力信号
の差値そのものではなく、これを2つの2次出力信号の
和の参照値で割った値をとっているので、ケーブル抵抗
「及び差動トランス13のコイル抵抗に影響されない測
定出力値を求めることが出来る。
According to this method, the measured output is not the difference value itself between the two secondary output signals, but the value obtained by dividing this by the reference value of the sum of the two secondary output signals. It is possible to obtain a measured output value that is not affected by the coil resistance of the dynamic transformer 13.

[発明が解決しようとする課題] しかしながらこの様にして得られる測定出力は、形の上
ではケーブル抵抗rの影響が無視出来るようになってい
るが、実際には正確な値を示さない。
[Problems to be Solved by the Invention] However, although the measurement output obtained in this manner is such that the influence of the cable resistance r can be ignored in appearance, it does not actually indicate an accurate value.

第2図から分かるように、上記の測定出力を求めるには
除算回路18を必要とする。しかしこの種の除算回路は
、外部にアナログ信号を出力する場合、A/D部分にD
C/DCの割算回路を必要とするので、DCドリフトの
影響が無視出来なくなり、正確な測定出力が得られなか
った。
As can be seen from FIG. 2, a division circuit 18 is required to obtain the above measurement output. However, when this type of division circuit outputs an analog signal to the outside, the A/D section
Since a C/DC divider circuit is required, the influence of DC drift cannot be ignored, and accurate measurement output cannot be obtained.

従って本発明は、安定した正確な測定出力を得ることの
出来る差動トランス変換方式を得ようとするものである
Therefore, the present invention aims to provide a differential transformer conversion system that can obtain stable and accurate measurement outputs.

[課題を解決するための手段] 本発明によれば、発振回路と、この発振回路側からの出
力信号を1次コイルに受け、2次コイルから2つの2次
出力信号を出力する差動トランスと、前記2つの2次出
力信号の和をとる加算回路と、前記2つの2次出力信号
の差をとる減算回路と、前記2つの2次信号の一方に同
期して前記加算回路および減算回路の出力信号の検波を
個々に行う2つの同期検波回路とを含み、前記減算側の
同期検波回路の出力を用いて測定出力を得るようにした
変換回路において、基準電圧と、この基準電圧と前記加
算側の同期検波回路の出力電圧の差電圧を少なくとも1
桁高い電圧に増幅する誤差増幅器と、この誤差増幅器の
出力を前記発振回路の発振出力に乗算して前記発信側か
らの出力信号として前記差動トランスの1次コイルに送
る乗算回路を付加して成り、前記減算側の同期検波回路
の出力を以て前記測定出力とすることを特徴とする差動
トランス変換方式が得られる。
[Means for Solving the Problems] According to the present invention, an oscillation circuit and a differential transformer whose primary coil receives an output signal from the oscillation circuit and output two secondary output signals from the secondary coil are provided. an adder circuit that takes the sum of the two secondary output signals; a subtracter circuit that takes the difference between the two secondary output signals; and the adder circuit and the subtracter circuit that are synchronized with one of the two secondary output signals. A conversion circuit includes two synchronous detection circuits that individually perform detection of output signals of , and obtains a measurement output using the output of the synchronous detection circuit on the subtraction side. The difference voltage between the output voltages of the synchronous detection circuit on the addition side is at least 1
An error amplifier that amplifies the voltage to an order of magnitude higher, and a multiplier circuit that multiplies the oscillation output of the oscillation circuit by the output of the error amplifier and sends the resultant signal to the primary coil of the differential transformer as an output signal from the transmitting side. As a result, a differential transformer conversion system is obtained in which the output of the synchronous detection circuit on the subtraction side is used as the measurement output.

[作 用] 上記の回路に於いては、増幅率の高い誤差増幅器を用い
て差動増幅幅器の2つの2次出力信号の和(参照値)を
常に基準電圧に固定し、減算側の同期検波回路から2つ
の2次出力信号の差をJIIJ定出力として正確にかつ
安定に出力する。
[Function] In the above circuit, the sum of the two secondary output signals (reference value) of the differential amplifier is always fixed to the reference voltage using an error amplifier with a high amplification factor, and the sum of the two secondary output signals of the differential amplifier is always fixed to the reference voltage. The synchronous detection circuit accurately and stably outputs the difference between two secondary output signals as a JIIJ constant output.

〔実施例] 次に本発明による差動トランス変換方式について実施例
を挙げ、図面を参照して説明する。
[Example] Next, an example of the differential transformer conversion system according to the present invention will be described with reference to the drawings.

第1図は本発明による一実施例の構成を示すブロック図
である。この実施例において、発振回路11の出力電圧
をvx1誤差増幅器21の出力電圧をMy、同じくゲイ
ンをに3、乗算回路22でvxとvvの積をとリバッフ
ァアンプ12を経た出力をv11加算側の同期検波回路
16の出力電圧をV。、基準電圧源23の出力である基
準電圧をVl、差・動トランス13の1次コイルと2次
コイルの結合係数をに2.1次コイルの抵抗をR12つ
の2次コイルの抵抗をともにR2,2つの2次出力信号
をv2とVlとすると、加算回路14および減算回路1
5の共通入力端子vA及びV。
FIG. 1 is a block diagram showing the configuration of an embodiment according to the present invention. In this embodiment, the output voltage of the oscillation circuit 11 is vx1, the output voltage of the error amplifier 21 is My, the gain is 3, the product of vx and vv is the product of vx and vv in the multiplier circuit 22, and the output after passing through the rebuffer amplifier 12 is v11 on the addition side. The output voltage of the synchronous detection circuit 16 is V. , the reference voltage that is the output of the reference voltage source 23 is Vl, the coupling coefficient between the primary coil and the secondary coil of the differential dynamic transformer 13 is 2. the resistance of the primary coil is R1, and the resistances of the two secondary coils are both R2. , the two secondary output signals are v2 and Vl, the addition circuit 14 and the subtraction circuit 1
5 common input terminals vA and V.

は、 VA −RV2 / (r+R2+R)−(RV+  
R2/  (2r+R+  )−Va  1/(r十R
2+R)      ・・・(1)Va  ””RVs
  /  (r  +R2+R)−(RV、  K2 
/  (2r+R,)  +V、]/(r十R2+R)
      ・・・(2)で表される。ここにRは加算
・減算回路14,15の人力インピーダンス、Vdは差
動トランス13のコアーに依存する電圧とする。
is VA −RV2 / (r+R2+R)−(RV+
R2/ (2r+R+)-Va 1/(r+R
2+R) ... (1) Va "" RVs
/ (r +R2+R)-(RV, K2
/ (2r+R,) +V,]/(r×R2+R)
...It is expressed as (2). Here, R is the human power impedance of the addition/subtraction circuits 14 and 15, and Vd is a voltage depending on the core of the differential transformer 13.

また、上記の加算回路14と減算回路15の共通入力端
子VAとV、および加算側同期検波回路16の出力電圧
V。は次のような関係にある。
Also, the common input terminals VA and V of the above-mentioned addition circuit 14 and subtraction circuit 15, and the output voltage V of the addition side synchronous detection circuit 16. has the following relationship.

Vo−VA十V、、          ++ (3)
この値は従来参照値として用いられていたものである。
Vo-VA ten V,, ++ (3)
This value has conventionally been used as a reference value.

一方電圧VISVx1■1、voSvRは、第1図の各
構成要素の配置から直ぐ分かるように、次のような関係
にある。
On the other hand, the voltages VISVx1■1 and voSvR have the following relationship, as can be readily seen from the arrangement of each component in FIG.

V、−VX−VY −Vx −に+  (V、 Vo 、    −(4)
ここで式(3)のVAと■8を式(1)と式(2)の形
で表し、得られた式中に含まれる■に式(4)の関係を
入れると、 Vo−2に2 RVx Kl  (V、−Vo )/(
(2r + R+ )  (r +R2+R) 1・・
・(5) と成る。この式(5)を■。について解くと、V、−2
に2RVxK、V、/ 1 (2r+R+ ) (r+R,+R) +2に2 
RVX Kl )       −(6)となる。ここ
で分母の第1項が無視出来る程度にに、の値を大きくす
れば、式(6)は Vo−V、             ・・・(7)と
なる。すなわち、従来参照値として用いられていた、入
力電圧VAとVBの和である加算側同期検波回路16の
出力電圧V。は、基準電圧V、に固定された値となる。
V, -VX-VY -Vx - + (V, Vo, -(4)
Here, if we express VA and ■8 in formula (3) in the form of formulas (1) and (2), and insert the relationship of formula (4) into ■ contained in the obtained formula, we get Vo-2. 2 RVx Kl (V, -Vo)/(
(2r + R+) (r +R2+R) 1...
・(5) becomes. This formula (5) is written as ■. Solving for V, -2
2RV x K, V, / 1 (2r+R+) (r+R, +R) +2 to 2
RVX Kl ) −(6). If the value of is increased to such an extent that the first term of the denominator can be ignored, equation (6) becomes Vo-V, . . . (7). That is, the output voltage V of the addition side synchronous detection circuit 16, which is the sum of the input voltages VA and VB, is conventionally used as a reference value. is a value fixed to the reference voltage V.

従って入力電圧vAとVBの差で表せる減算回路15の
出力は、参照値で除算することなくそのまま減算側の同
期検波間Fδ17から811定出力VPとして得られる
。すなわち、DCドリフトの生じる除算回路を用いるこ
となく測定出力を得ることが出来る。
Therefore, the output of the subtraction circuit 15, which can be expressed as the difference between the input voltages vA and VB, is obtained as is from the synchronous detection interval Fδ17 on the subtraction side as the 811 constant output VP without being divided by the reference value. That is, a measurement output can be obtained without using a division circuit that causes DC drift.

f記において、誤差増幅器21の増幅率に1の値として
は、計算上では10程度で有れば一応使えるが、精度と
安定性の面から言って実用上では102或いはそれ以上
を用いる。なおこの増幅率の設定は信号が交流であるか
直流であるかによって異なり、前者の場合は10ないし
5X102倍程度が、後者の場合は10′ないし10’
倍程度が目安と成る。このように範囲が異なるのは、主
として回路系の安定度が交流信号を用いると低下するこ
とによる。
In section f, as the value of 1 for the amplification factor of the error amplifier 21, a value of about 10 can be used in calculations, but in terms of accuracy and stability, a value of 102 or more is used in practice. The setting of this amplification factor differs depending on whether the signal is AC or DC, and in the former case it is about 10 to 5X102 times, and in the latter case it is 10' to 10'.
The standard is approximately double that. This difference in range is mainly due to the fact that the stability of the circuit system decreases when AC signals are used.

[発明の効果] 以上の説明から明らかなように、本発明に於いては、基
準電圧源、誤差増幅器および乗算回路を用いて減算回路
人力VAとVBの和を一定値に固定することにより、入
力電圧vAとV、の差値を参照値で除算することなくそ
のまま測定出力■。
[Effects of the Invention] As is clear from the above description, in the present invention, by fixing the sum of the subtraction circuit manual power VA and VB to a constant value using a reference voltage source, an error amplifier, and a multiplier circuit, The difference value between the input voltages vA and V is directly measured and output without dividing it by the reference value■.

として出力させることが出来る。従って得られる測定出
力は正確且つ安定であり、装置の信頼性が向上する。
It can be output as Therefore, the measurement output obtained is accurate and stable, improving the reliability of the device.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の構成を示す図、第2図は従
来の差動トランス変換方式の構成を示す図である。 記号の説明:11・・・発振回路、12・・・バッフ7
アンブ12.13・・・差動トランス、14・・・加算
回路。15・・・減算回路、16・・・同期検波回路(
加算側)、17・・・同期検波回路(減算側)、21・
・・誤差増幅器、22・・・乗算回路、23・・・裁準
電圧源。
FIG. 1 is a diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a diagram showing the configuration of a conventional differential transformer conversion system. Explanation of symbols: 11...Oscillation circuit, 12...Buffer 7
12.13...Differential transformer, 14...Addition circuit. 15... Subtraction circuit, 16... Synchronous detection circuit (
addition side), 17... synchronous detection circuit (subtraction side), 21.
...Error amplifier, 22...Multiplication circuit, 23...Adjudication voltage source.

Claims (1)

【特許請求の範囲】 1、発振回路と、この発振回路側からの出力信号を1次
コイルに受け、2次コイルから2つの2次出力信号を出
力する差動トランスと、前記2つの2次出力信号の和を
とる加算回路と、前記2つの2次出力信号の差をとる減
算回路と、前記2つの2次信号の一方に同期して前記加
算回路および減算回路の出力信号の検波を個々に行う2
つの同期検波回路とを含み、前記減算側の同期検波回路
の出力を用いて測定出力を得るようにした変換回路にお
いて、 基準電圧と、この基準電圧と前記加算側の同期検波回路
の出力電圧の差電圧を少なくとも1桁高い電圧に増幅す
る誤差増幅器と、この誤差増幅器の出力を前記発振回路
の発振出力に乗算して前記発振回路からの出力信号とし
て前記差動トランスの1次コイルに送る乗算回路を付加
して成り、前記減算側の同期検波回路の出力を以て前記
測定出力とすることを特徴とする差動トランス変換方式
[Claims] 1. An oscillation circuit, a differential transformer whose primary coil receives an output signal from the oscillation circuit, and whose secondary coil outputs two secondary output signals; an addition circuit that takes the sum of the output signals; a subtraction circuit that takes the difference between the two secondary output signals; and a detection circuit that individually detects the output signals of the addition circuit and the subtraction circuit in synchronization with one of the two secondary signals. to do 2
A conversion circuit that includes two synchronous detection circuits and obtains a measurement output using the output of the synchronous detection circuit on the subtraction side. an error amplifier that amplifies the differential voltage to a voltage that is at least one order of magnitude higher; and a multiplier that multiplies the oscillation output of the oscillation circuit by the output of the error amplifier and sends the resultant signal to the primary coil of the differential transformer as an output signal from the oscillation circuit. A differential transformer conversion method comprising an additional circuit, wherein the output of the synchronous detection circuit on the subtraction side is used as the measurement output.
JP17703689A 1989-07-11 1989-07-11 Differential transformer conversion system Pending JPH0342513A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17703689A JPH0342513A (en) 1989-07-11 1989-07-11 Differential transformer conversion system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17703689A JPH0342513A (en) 1989-07-11 1989-07-11 Differential transformer conversion system

Publications (1)

Publication Number Publication Date
JPH0342513A true JPH0342513A (en) 1991-02-22

Family

ID=16024026

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17703689A Pending JPH0342513A (en) 1989-07-11 1989-07-11 Differential transformer conversion system

Country Status (1)

Country Link
JP (1) JPH0342513A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4721643U (en) * 1971-02-28 1972-11-10
JPS6412328A (en) * 1987-07-06 1989-01-17 Brother Ind Ltd Interface for printer

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4721643U (en) * 1971-02-28 1972-11-10
JPS6412328A (en) * 1987-07-06 1989-01-17 Brother Ind Ltd Interface for printer

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