JPH0341820A - Output buffer circuit - Google Patents

Abstract

PURPOSE:To obtain an output buffer able to be used without causing malfunction by driving a couple of parallel PE-IGFET and NE-IGFET at the final stage with a separate inverter, individually. CONSTITUTION:PE-IGFETQ025, Q027 and NE-IGFETQ026, Q028 are added to a final stage of an output buffer circuit OUT 1. On the other hand, 3rd and 4th inverters driving gates of the FETQ027, Q028 are provided respectively. When a sense output SOUT changes from L to H, the FETQ025 having a small ratio of a gate width and a gate length is small at the final stage is energized and dIP/dt is decreased. Thus, the moment the FETQ025 is energized by the switching of the final stage of the circuit OUT 1, quantity of noise CC1, SS1 superimposing on a power supply CC1, ground SS1 is decreased. That is, when the output buffer circuit OUT 1 is used for a semiconductor storage device, malfunction of a sense amplifier circuit or the like is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a novel configuration of an output buffer circuit in a semiconductor memory device whose main component is an insulated gate field effect transistor (hereinafter referred to as IGFET). .

BACKGROUND OF THE INVENTION FIG. 4 is a circuit diagram showing a typical configuration of an output buffer circuit UT3 used in a semiconductor memory device. In addition, in FIG. 4, FETQ, , Q03, Qo9, Qo7
, Qo3, Qo+o s Qo13 and Q. , 5 is P
Channel type enhancement CFET (hereinafter referred to as PE-
), and FET Q O2, Q
o3, Qo6, Qo[1SQo, , QoI□, Q O
+4 and Q. 16 is an N-channel enhancement type IGFET (hereinafter referred to as NE-IGFET).

In FIG. 4, CCL indicates a power pin of the case of the semiconductor memory device connected to an external power supply, and ccP indicates a power band of the semiconductor memory device. Also, L,
cc represents parasitic inductance caused by self-inductance of case leads and bonding wires added between CCL and CCP as a lumped constant.

In addition, CCI is the power supply for the internal circuit, and RCCl is the CC
This diagram schematically shows the parasitic resistance caused by the wiring resistance of aluminum or polysilicon added between P and CC1, where CC2 is the internal power supply dedicated to the final stage of the output buffer circuit, and ReO2 is the It shows the parasitic resistance added between CCP and CC2.

On the other hand, SSL connects the GND pin of the semiconductor storage device case that is connected to external ground, and SSP connects the GND pin of the semiconductor storage device case to external ground.
Each represents an ND pad, and LSS represents a parasitic inductance added between SSL and SSP. Further, SSI schematically indicates GND of the internal circuit, and R8,1 schematically indicates a parasitic resistance added between SSP and 5SIO.

Further, SS2 indicates an internal GND dedicated to the final stage of the output buffer circuit, and R552 indicates a parasitic resistance added between SSP and SS2.

DouL is the output of the output buffer circuit and is connected to the output pin of the semiconductor memory device. Further, S out is the output of the sense amplifier circuit within the semiconductor memory device. R.D.
is a signal generated by a control circuit in the semiconductor memory device and becomes "H" in the read mode, and RD is an inverted signal of Ib.

In the circuit shown in FIG. 4, the reason why a dedicated power supply and GND are used at the final stage of the output buffer circuit is as follows.

That is, the ratio of the gate width to the gate length in the final stage of the output buffer circuit (hereinafter referred to as CWGAT/Lll, ATY) is the capacitance added to Dout (usually 10
For example, [WaAt,! /LGATE]=500/5, which is generally designed to be large. Therefore, if the internal circuit is connected to the power supply and GND in common, the noise generated when the final stage of the output buffer circuit switches may enter the internal circuit's power supply and GND, causing malfunction of the sense amplifier circuit, etc. It is.

FIG. 5 is a signal waveform diagram for explaining the operation of the output sofa circuit shown in FIG. 4. More specifically, FIGS. 5(a), et al.) and (C) show that at timing t, S o
u t goes from 'L' to 'H', S at timing t2.

The voltage waveform at each node when uL changes from "H" to L', the current 1p3 flowing through FETQo+s, and FETQ
Fig. 4 shows the time change of the current [Na flowing through the terminals o and 6, respectively, and the displayed symbols correspond to the symbols of each node in Fig. 4.

In addition, since the following explanation is exclusively about the read mode of the output buffer circuit, RD is 11 HII, RD
It is assumed that the signal is kept in the "L" state.

In addition, here, the semiconductor memory device has an 8-bit output, and 8 bits.
It is assumed that two output buffer circuits are connected to each output pin of each output Dout.

Now, as shown in FIG. 5(a), at timing t1, S
. When ut changes from “L” to “HII,” node OA changes to “
'H' → 'L', node OB goes 'L'-H'1.:, node OC goes 'H' → 'L', node OD goes 'L' → 'H', node ○E goes ' H” → “L” respectively, therefore, F E T QOI5 On the other hand,
Q(116 becomes non-conductive.

At this time, generally in the output buffer circuit, the power supply and GN
To prevent noise in D, the node OE is designed to go from "H" to "L" earlier than the node OC, and as a result, FETQo+s and Q. The structure is such that no through current flows through the capacitor 16. On the other hand, in this state,
A charging current shown as P3 flows from CCL to DOut through FETQo+s, and the voltage of Dout gradually rises from OV and is balanced at [Vcc:].

Here, RCC2=10Ω, FETQo+s(
WGAT+! /LcATt:] is 1000/5, and if all eight output buffer circuits such that [I, 3) = 20mA change from °"L" to "IIH"', CC2 becomes conductive, The amount of decrease ΔVCC2 from CVcc] is ΔVCC2=
10X 8 Xo, 02 = 1.6V. Further, at this time, the voltage drop of CC2 becomes negative, and current also flows oscillatingly to the LCD and RCCI.

Here, the capacity IEctc (not shown) added to Rcc+, CCL, CCP, and CC1 and LCC are R-L
-C circuit is formed, so as shown in the fifth opening), the C circuit is formed.
The voltage of CI oscillates and gradually attenuates, and finally reaches (Vcc)
Equilibrium at . Its amplitude and period are LCC and Ro. , and C
It is determined by a coefficient determined by a value of 70. CC1 in FIG. 5 shows this situation.

That is, at timing t, CCI [vo. ] is the current change (d[■P
3]/dt>. Therefore, C of FETQO,
WGA? The larger the E/L at I ratio is designed, the more noise will be added to the CCI.

Also, since CC1 and SS1 are coupled by capacitance,
The noise on CC1 also rides on SSI, this noise changes in the same phase as CCI, and its amplitude is smaller than the amplitude of CCI.

Conversely, S at timing t2. 0. is “H” → 11 L
When changing to II, node OA changes from “L” to “H”, node OB changes from “H” to “L”, node ○C changes from “L” to “H″′, and node ○D changes from “H”. → to “L”, node ○E changes from “L” to “H”, F E T Qols becomes non-conductive, and Q
Q+6 becomes conductive.

At this time, in this output buffer circuit ○UT3, the node OC is generated earlier than the node OE for the above-mentioned noise countermeasure.
Since it is laterally throttled so that it changes from "L" to "H," a discharge current flows from DouL to SS2 through FETQo+s, as shown as L3 in Figure 5 (C). It gradually decreases from [vcc] and reaches equilibrium at OV.

Here, Rss+=5Ω, FETQo+e (WGAT
! /LGA? 1! When E is 100015 (I ws
Assuming that all eight output buffer circuits change from “H” to “L” so that “J = 20mA”, SS2
The amount of increase ΔVSS2 from QV is; ΔVSS2=5 x 8 xO, 02=0.8v. Moreover, at this time, the voltage rise of SS2 acts as a trigger, and current also flows oscillatedly through LSS and R55I.

Therefore, as in the previous case, RS S l, 5SLX
Since the capacitance CTS (not shown) added to SSP and SS1 and LSS form an R-L-C circuit, as shown in FIG. 5(b), as well as CC1, the voltage of SS1 vibrates.

Here, the amount by which SS1 rises from OV at timing t2 is ``■'' at timing t2. Current change (d (r
, ]/d t), so Qo,.

The larger the [WGAT/LGATII, the greater the amount of noise riding on the SSI. Note that noise is also added to CCl with the same phase as SS1, and the amplitude of CC1 becomes smaller than the amplitude of SSI.

As described above, in the output buffer circuit, noise is generated in the power supply and GND when the final stage of the output buffer circuit switches. Therefore, conventionally, the final stage power supply #GND of the output buffer circuit is connected to the power supply and GND of other internal circuits.
D or PE-I in the final stage of the output buffer circuit.
Measures were taken to prevent noise from affecting the internal circuit, such as by adopting a configuration in which the CFET and NE-IGFET were not conductive at the same time.

However, on the other hand, the demand for higher speed circuits as described above has increased significantly in recent years, and it has become necessary to design the final stage of the output buffer (W G Ap/LcAtp) to be large. This is explained above (d CIp
t) / d t ) and (d [: IX3] / d
t) becomes large, which means that the noise caused by the switching of the final stage of the output buffer is
This means that it becomes easier to wrap around D. That is, in a design aimed at high-speed operation, a problem arises in that highly sensitive circuits such as a sense amplifier circuit malfunction due to vibrations generated in the power supply and GND of the internal circuit.

FIG. 6 is a circuit diagram showing the configuration of a circuit using FAMO3 as a memory element as a typical example of the sense amplifier circuit as described above.

That is, in this circuit, the node SC is connected to the FETQS3
and Q8. Because it is biased near the logic threshold, it is extremely sensitive and operates at high speed.

FETQ, ,Q,3 are PE-IGFETs, FE
TQ12, Q82, and QSS are NE-IGFETs.

Furthermore, it is assumed that Mll and M21 are memory elements, and "0" is stored in memory element M, and "1" is stored in memory element M1□. Furthermore, X11X2 is the output of decoder X, YI is the output of decoder Y, and when selected, [V c c ] is applied to each of them.

Note that this sense amplifier circuit is connected to an output buffer circuit via an inverter 11.

FIG. 7 is a diagram showing signal waveforms for explaining the operation of the sense amplifier circuit shown in FIG.
Memory element M is selected at timing t, and memory element M2 is selected at timing t. 3 shows the voltage waveform of the signal at each node when is selected.

Note that each symbol shown in FIG. 7 corresponds to the symbol of each node shown in FIG.

In FIG. 7, VSA(Off) is the equilibrium voltage of the node SA when a memory element storing "0" is selected.
SA (On) indicates the equilibrium voltage at the node SA when a memory element storing "l" is selected. In addition, vsn (on) is the equilibrium voltage of the node SB when a memory element that stores "1" is selected, and VS (off) is the equilibrium voltage of the node SB when a memory element that stores "0" is selected. The balanced voltages are shown respectively.The waveforms shown by dotted lines show the voltage waveforms at each node when a malfunction described later does not occur.

Now, at timing t3, xl is “H” and YI is “H”
Assume that the memory elements M and l are selected. At this time, since the memory element M is non-conductive, the voltage at the node SC increases, the voltage at the node SB decreases, the voltage at the node SA increases, and the voltage at the node SB becomes VSB (off). Opposite, node SA
The voltage of goes towards v, A(off).

Here, h detects the voltage change at node SA and outputs S. u
t changes to "L". Therefore, as shown in Figure 5,
Output buffer circuit output. ut is “H” to “L”
Changes to

Further, with this operation, the voltage of SSI increases instantaneously, so the voltage difference between the gate and source of FET Qs4 of the sense amplifier circuit becomes small, and FET QS4 becomes non-conductive. Then, the voltage at the node SB rises again as if the memory element storing "1" was selected, and the voltage at the node SA drops again. For this reason,
S out and ri. U.

The voltage also changes from "L" to "H". At this time, if the level of noise at SS1 is light, the voltages at nodes SA and SB return to their original equilibrium voltages, as shown in FIG.

Due to the above operation, the switching speed of a semiconductor memory device using this conventional output buffer circuit is
This results in a delay of td with respect to the original switching speed.

On the other hand, when X2 becomes "H" at timing t4 and memory element M21 is selected, memory element M2 becomes conductive, so the voltage at node SC decreases, the voltage at node SB increases, and the voltage at node SA increases. decreases, the voltage at node SB goes towards Vsn (on), and the voltage at node SA
The voltage of VsA (On) goes to VsA(On).

Here, h detects the voltage change at node SA, and the output S o
ut changes to "H". Therefore, the output of the output buffer circuit. t changes from "L" to "H".

Along with this, the voltage of CC1 drops momentarily, so
The voltage difference between the gate and source of QH in the sense amplifier circuit shown in FIG. 6 becomes small, Q53 becomes non-conductive, and the voltage at node SB decreases as if the memory element storing "D" had been selected. It decreases again, and the voltage at node SA increases again.

For the above operation, S out and R. ut
The voltage also changes from "H'" to "L". Here, CC1
When the level of noise is light, the voltages at nodes SA and SB return to their original equilibrium voltages, as shown in FIG.

Therefore, when the conventional output buffer circuit is used, the switching speed of the semiconductor memory device will be delayed by td2 with respect to the original switching speed.

Furthermore, if the degree of noise as mentioned above is larger,
When Dout outputs "H", the power supply voltage drops and the sense amplifier circuit malfunctions, causing Do.

will now output “L”. As a result, the GND potential rises and Dout now outputs °H, causing positive feedback between the sense amplifier circuit and the output buffer circuit, causing the circuit to oscillate. .

Problems to be Solved by the Invention As mentioned above, in general output buffer circuits, in order to speed up the operation, the PE-ICFET and NE-IGFET (W G
It is necessary to set A t□/LGAT Yu] large,
In that case, an extremely large charging current (IF5.' flows) at the moment the final stage PE-TGFET becomes conductive.

Therefore, (d (Ipa)/d t ) or (d
ClN5)/dt) increases, and L of the case
The sense amplifier circuit, etc. is affected by the parasitic inductance added to the EAD and bonding wire, and the parasitic resistance of the aluminum wiring or polysilicon wiring connected from the power supply pad or GND pad to the internal circuit power supply or GND. There is a drawback that noise is generated in the power supply GND of the highly sensitive internal circuit, inducing malfunction.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to solve the above-mentioned problems of the prior art and provide a novel output cover sofa circuit configuration that can be used without inducing malfunctions even in semiconductor memory devices that operate at high speed. The purpose is

Means for solving the problem, that is, according to the present invention, a first P-channel field effect transistor whose source is connected to a power supply and whose drain is connected to an output terminal; a first inverter connected to the gate of the first P-channel field-effect transistor; and in parallel with the first P-channel field-effect transistor, the source is connected to the power supply and the drain is connected to the output terminal. a second P-channel field-effect transistor whose input is connected to the input signal and whose output is connected to the gate of the second P-channel field-effect transistor; a first N-channel field effect transistor whose source is connected to ground at the output terminal; an input receiving an input signal; and an output receiving an input signal of the first N-channel field effect transistor; a second N-channel field effect transistor whose drain is connected to the output terminal and whose source is connected to ground in parallel with the first inverter and the first N-channel field effect transistor; , an input receives an input signal, an output receives an input signal of the second N-channel field effect transistor, and an output of the second inverter, the logic threshold of the first inverter; and a logic threshold of the second inverter are set to be different from each other, and a logic threshold of the third inverter and a logic threshold of the fourth inverter are set to be different from each other. An output buffer circuit is provided.

Function: In contrast to the conventional output buffer circuit described above, in the output buffer circuit according to the present invention, the final stage PE-IGFET is composed of first and second PE-TGFETs that are parallel to each other, and these pair The PE-IGFET is
Each of them is configured to be driven by a separate inverter.

In addition, the final stage NE-IGFET is also connected to the first
and a second NE-'IGFET, whose gates are similarly driven by different inverters.

Therefore, one PE-IGFET and NE-ICFE
Since T [WGATE/LGATI:) can be set small without considering the operating speed, the charging current [Il
, ] or discharge current [INII:] can be reduced.

Also, (d[:IPll]/dt') and <
d[INII)/dt) can be made smaller compared to conventional output buffer circuits, so the amount of noise that gets on the power supply GND of the internal circuit at the moment the final stage of the output buffer circuit switches is reduced. . Therefore,
When used as an output buffer of a semiconductor memory device, malfunction of the sense amplifier circuit will not be induced. Also,
of the second PE-IGFET and the second NE-IGFET (
W G AT P: / L G AT I! ) by setting a large value, the switching speed of the output buffer circuit can be increased, so that it can also be used in semiconductor memory devices that require high-speed operation.

Hereinafter, the present invention will be described in more detail with reference to the drawings, but the following disclosure is only one embodiment of the present invention, and does not limit the technical scope of the present invention in any way.

Embodiment 1 FIG. 1 is a circuit diagram showing a specific configuration example of an output buffer circuit according to the present invention. In FIG. 1, the same components as those in the conventional circuit shown in FIG. 4 are given the same reference numerals and their explanations are omitted.

In addition, in FIG. 4, F ETQO2+ , QO23
, Qo2s1Qo2. is a PE-IGFET, and FE
TQO22, QO24, QO21! , Q[+211 are NE-I GFETs.

In comparison with the conventional example shown in FIG. 4, the output buffer circuit ○UTI shown in FIG.
E -I G F ETQa2s plus a second P
E-I GF ETQa2t and FE
The gate of TQo2t is connected to FETQo2+ and Q O2
The difference is that it is driven by a third inverter composed of two.

Here, FETQO2S and Q. In common with 27, the source is connected to the power supply and the drain is connected to the output terminal. In addition, FETQO22 is larger than FETQoa [W
The GA/LGAT is designed to be small. still,
In this example, Qos: CWGATE/LaATp) = 30
/ Qoe for 3: [WGAT+! / L.G.A.
T! ]=30/10. Therefore, the node O
The timing when F changes from “H” to “L” is at node ○C
The timing is later than the timing at which the signal changes from “H” to “L”. By designing in this way, F E T Qo,
The timing at which FETQO2S becomes conductive can be made later than the timing at which FETQO2S becomes conductive.

In addition, this output buffer circuit has a first
NE IGFETQo2g plus a second NE
I G F E T QO28 and F
FETQO23 and Q that drive the gate of ETQO28
The present invention is also different from the conventional example in that it includes a fourth inverter constituted by o24.

Here, the drains of the FET QO26 and Q028 are commonly connected to the output terminal, and the sources are connected to the ground. Also, F E T Q1123 is F E T
TQ. CWr than I3, A r p / L G A
T□] is designed to be small. In this embodiment, QO+3: [:WGATE/Lc^↑E)
QO23 for =60/4: [WcATp/L
It is set as cAtel=60/10. Therefore,
The timing at which the node ○G changes from L" to "H" is later than the timing at which the node ○C changes from 'L" to "H". By designing in this way, FETQO2 [
The timing when 1 becomes conductive is later than the timing when FET Q02B becomes conductive.

In the output buffer circuit having the i8 function configured as described above, when S5uL changes from "L" to "H" and the final stage switches, FETQO25 first becomes conductive. Start charging U, and after a certain period of time,
FETQO27 is conducting. Further charge U to CVcc). Furthermore, the timing at which FETQ,2□ conducts is determined by [Wc・AvE/LGATII of Qo2゜]
It can be controlled by

Also, in this output buffer circuit, 5out is “H”
” to “L” and the final stage switches,
First, after FETQO26 becomes conductive and DOut begins to be discharged, FETQO2B becomes conductive after a certain period of time has elapsed. Further discharge ut to OV. Furthermore, FETQo
The timing at which 2e becomes conductive is CW c A t ! of F ET QO23. ! / L7. ].

FIGS. 2(a), (b), and (C) show FETs QQ2+ and Q in the output buffer circuit shown in FIG.

, and FETQO24 and Q. , , and DV, respectively.
GAtp/LeeeT! ] are the same, and FETQ (122, Q Q 23, Qo2., Qo
26, QO27 and Q028 CW G A t t
/ L c A T e :l・each・30/
10.60/10.20015.100/5.120
FIG. 4 is a signal waveform diagram for explaining the operation of this circuit when configured to have a ratio of 0/5 and 600/5. More specifically, FIGS. 2(a), 2) and (C) are
Respectively, S Ou L is timing 1. So “L′″→
'H', the voltage waveform at each node when it changes from "H" to "L" at timing t2, the current ■, 1 flowing through FETQozs, and the time of the current (Ip++ + IP+2) flowing through FETQo2s and Qo27. Change and FETQ
Current INI+ flowing through O□6 and FET Q112
11 and Q. 28 shows the time change of the current (INll+1□2) flowing through 28.

As shown in FIG. 1(a), timing 1. In S
01. When changes from "L# to "H", node ○C changes to "H" - ten "L", as already explained for the conventional example. Now, node ○E changes from "L#" to "H" earlier than node Or. H"
→If the circuit is designed to change to “L”, then
First, FETQ, □ becomes conductive, and charging current IP11 flows to Dout as shown in FIG. 2(C).
As shown in a), the voltage of Dout increases from OV.

Here, in the case of this embodiment, FETQ0□ is (Wcarp/LGAT
Since F is set small, (Ip, +] is (
IP3: ] will be less. Therefore, the rate of increase in the voltage of Dout is slower than in the conventional example until timing t11.

Next, as shown in FIG. 2(a), when the node OF changes from "H" to "L" at timing t, F E T
Qo2t becomes conductive. Therefore, FETQO2S and Q.

7. As shown in FIG. 2(C), the charging current (Ip+++ IP+2) increases from CC2 to D08. As shown in Figure 2(a), Dou
The voltage at t further increases and equilibrates at (Vcc).

On the other hand, as shown in FIG. 2(a), at timing t2, S
When out changes from “H” to “L”, node ○E
changes from "L' to "H". Here, assuming that the circuit is designed so that the rate of change from "L" to "H" at node ○C is faster than at node ○E, first ,FET
QO28 becomes conductive, and the discharge current INII increases as shown in FIG. 2(C). Flows from 5t toward SS2, and the second
As shown in Figure (a), the voltage of Dout decreases from (Vccl).

In the case of this embodiment, FETQO26 is the conventional FETQo
Since (WGATE/LGA) is set smaller than 16, C15z] is smaller than [IN3], and the voltage drop rate of Dout is slower up to timing t21 than in the conventional example.

Next, at timing t21, as shown in FIG. 2(a), when the node OG changes from ll L II to II HI+, the FET QQ211 becomes conductive. Therefore, F.E.
TQO2[1 and Qo2a are both conductive, and as shown in Fig. 2 (C
), the discharge current (INll+IN+2) flows from Dout to SS2, and as shown in FIG. 2(a), the voltage at Dout further decreases and balances at OV.

In this way, in the output buffer circuit according to the present invention, S
When out changes from "L" to "H", first, CWGAtt/LGATL] is small at timing t.

Sai Q. 25 is conductive, so compared to the conventional circuit (
d[Ia, l/dt) becomes smaller. Therefore, the amount of noise CCI and SSI on the power supply CC1 and GNDSSI at the moment when Qa2s becomes conductive due to the switching of the final stage of the output buffer circuit is as shown in Figure 2 et al.), and that of the conventional circuit (Fig. 5 et al.). (CCI, 5SI) shown in . That is, when the output sofa circuit according to the present invention is used in a semiconductor memory device, malfunctions of the sense amplifier circuit and the like are prevented.

In addition, in the output vanofer circuit according to the present invention, at timing tl+, FETQ with a large [WaE/LGATE]
O27 becomes conductive, and after timing t11, FETQ
O2S and Q. 2. DOut is charged via.

That is, after timing tll, the speed is high. ut is (V
c c ).

On the other hand, in the output buffer circuit according to the present invention, S o
When uL changes from "H" to "L", first, at timing t2, CW G A r z / L G A t
Since the FET Qo 2 G with a small [a] is conductive, compared to the conventional one, (d[:I+t)/dt)
becomes smaller. Therefore, the moment the final stage of the output buffer circuit switches and FETQo2g becomes conductive, the GND
The amount of noise on the SSI and power supply CCI is reduced. That is, even in the change from "H" to "L"', malfunction of the sense amplifier circuit etc. is effectively prevented.

Also, at timing t21, (W r, A r E /
Since the large FET QO211 becomes conductive, from 2□ onwards, FET Q
O2B and Q. The charge on Dout is discharged through 28. Therefore, D(+ut is discharged at high speed.

As described above, the output buffer circuit according to the present invention is
When the final stage switches, the internal circuit power supply and G
Since the amount of noise generated in the ND is smaller than in the case of the prior art, even when used in a semiconductor memory device, malfunctions such as slow operation of the sense amplifier circuit or oscillation will not be induced.

Embodiment 2 FIG. 3 is a circuit diagram showing another configuration example of the output buffer circuit according to the present invention. In FIG. 1, the same components as those in the conventional circuit shown in FIG. 4 are given the same reference numerals and their explanations are omitted. Moreover, in FIG. 4, F E
T Qos+, Qo33, Qo3゜ and Qo,,
is a PE-IGFET, and FETQo, ,Q, ,
, Qo36 and Q. , , are NE-IGFETs.

Further, R1 and R2 are resistance elements.

In the output buffer circuit 0UT2 shown in FIG.
becomes “H” → 11 L at a timing later than node ○C
11, resistors R and t are inserted between the drain of FETQ, 3° and the drain of FETQQ3□. In addition, in order to set the node ○ to go from "L" to "H" at a later timing than the node OE, the drain of FETQQ33 and FETQ
A resistor R2 is inserted between the drain of o3-.

That is, as described above, by inserting the resistors R1 and R2, FETQo3t is set to conduct later than FETQO35, and FETQo3t is set to become conductive later than FETQO35.
, 38 are set to become conductive later than FETQO36. In other words, in the output buffer circuit 0UT2 according to the present embodiment, the timing at which FETQost becomes conductive and the timing at which FETQOI3 becomes conductive can be arbitrarily set by the resistance values of resistors R1 and R2, respectively.

In this embodiment, FETQO31, Qo34, Qo35,
QO36, QO3'? and Q. ,,8 CW c
A T E / L OA t E ], FETQ02+, Qo24, QO25, Qo26, Qo of Example 1
2. and Q. 28 CW G A T E / L
c, AT! ], and
As described above, by appropriately adjusting the resistance values of resistors R and R2, the timing at which the node OH changes from "H" to "L" is the same as the timing at which the node OF in Example 1 changes from "H" to "L". The transistors used are set to be the same. Similarly, the timing at which the node OI changes from "L" to "H" is
The node OG of the first embodiment changes from "L" to "H". The timing is set to be the same.

Therefore, the operation of this circuit is substantially the same as that of the output buffer circuit of the first embodiment, and when this circuit is used in a semiconductor memory device, it has the same effect as the output buffer circuit of the first embodiment. In this embodiment, the resistors R3 and R2 are described as resistive elements, but it goes without saying that they can be constructed from other elements such as IGFETs.

As described in detail of the invention, in the output buffer circuit according to the present invention, the final stage is constituted by a pair of PEIGFET and PE-IGFET that are parallel to each other, and each of these PE-IGFETs is It is configured to be driven by an inverter.

Therefore, one PE-IGFET and NEIGFET
(WGATE/LGAT!:) can be set small without considering the operating speed, so the charging current [:Ip] at the moment the final stage of the output buffer circuit switches
z] or the discharge current [:lN11] can be made small.

Also, (d[:I□,]/dt) and (d(INII
) /d t) can be made smaller compared to conventional output buffer circuits, so the maximum t of the output buffer circuit can be reduced.
The moment il& switches, the internal circuit power supply GND
The amount of noise on the board will be reduced.

Therefore, when used as an output buffer of a semiconductor memory device, malfunction of the sense amplifier circuit will not be induced. Also, a second PE-IGFET and a second NE-IGF
ET's [W G A T E / L G A T E
) by setting a large value, the switching speed of the output buffer circuit can be increased, so that it can also be used in semiconductor memory devices that require high-speed operation.

In the above embodiment, the final stage PE-IGFET and NE-IGFET of the output buffer circuit are each made up of two
Although we have disclosed an example of a configuration where each gate is connected in parallel, it is possible to achieve the same function no matter how many gates are connected in parallel, as long as each gate is driven by a separate inverter. , it goes without saying that this is included within the scope of the present invention.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a configuration example of an output buffer circuit according to the present invention, and FIGS. 2(a), (b), and (C) explain the operation of the circuit shown in FIG. 1. FIG. 3 is a circuit diagram showing a configuration example other than the output buffer 7 circuit according to the present invention, and FIG. 4 shows a typical configuration of a conventional output buffer circuit. 5(a), 5(c) are signal waveform diagrams for explaining the operation of the circuit shown in FIG. 4, and FIG. 6 is a signal waveform diagram for explaining the operation of the circuit shown in FIG. 4. 7 is a circuit diagram showing the configuration of a sense amplifier circuit of a semiconductor memory device used together with an output buffer circuit. FIG. 7 is a signal waveform diagram for explaining the operation of the sense amplifier circuit shown in FIG. 6. [Main reference symbols] Qol, Qol, QO4, Qo7, Qo9, QalO%
QO+3%QO15-°°6...P-channel enhancement IGFET (pH, -IGFET), Qo21 Qo5)Qo6・Q081Q,,,X Q
. ,,,Q,,4,Qo,61 6...N-channel type enhancement member) IGFET (NE-IGFE
T), ○UTL○UT2, ○UT3...Output buffer circuit, CCLSCCPSCC1, CC2...Power supply (power pin, power pad), DouL...Output of the output buffer circuit, S o u L ・...Sense amplifier circuit output, SSI, SS2, SSL, SSP...
・ ・GND (GND pin, GND pad), L
CC% L S S... Parasitic inductance RCC
I, RCC2, R55I, R552...parasitic resistance, R
D, RD...read signal

Claims (1)

[Claims] A first P-channel field effect transistor whose source is connected to a power supply and whose drain is connected to an output terminal; a first inverter connected to the gate of the channel field effect transistor; and a second P inverter in parallel with the first P channel field effect transistor, the source of which is connected to the power supply, and the drain of which is connected to the output terminal. a second inverter having an input receiving an input signal from an input terminal and having an output connected to the gate of the second P-channel field effect transistor; a drain connected to the output terminal; first N-channel field effect transistors each having a source connected to ground; an input receiving an input signal from an input terminal; and an output connected to the gate of the first N-channel field effect transistor. a third inverter; a second N-channel field-effect transistor whose drain is connected to the output terminal and whose source is connected to ground in parallel with the first N-channel field-effect transistor; and whose input is the input terminal. a fourth inverter receiving an input signal from the second inverter and having an output connected to the gate of the second N-channel field effect transistor; are set to be different from each other, and the logic thresholds of the third inverter and the fourth inverter are set to be different from each other. output buffer circuit.