JPH0340525A - Digital level adjusting circuit - Google Patents

Abstract

PURPOSE:To attain highly efficient level adjustment by simple constitution without increasing bit length by providing the digital level adjusting circuit with a multiplication circuit for multiplying the output data of a quantizing circuit by a prescribed constant k>=1 and supplying the multiplied value to a subtractor and controlling the constant (k) to adjust the level of the output data of the quantizing circuit. CONSTITUTION:A data y' outputted from the binary quantizing circuit 18 is multiplied by the prescribed constant k>=1 through the multiplier 19 and a difference data (e) between the multiplied value and the outputted data (y) of an adder 16 is calculated by a subtraction circuit 20 and supplied to a filter circuit 17. When the constant (k) of the multiplication circuit 19 is varied by a control signal supplied to a control terminal 21, the level of the data y' outputted from the circuit 18 can be adjusted. Consequently, highly efficient level adjustment can be attained by the simple constitution without increasing the bit length.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a digital level adjustment circuit that performs level adjustment such as volume adjustment by digital processing, and particularly relates to a digital level adjustment circuit that uses a delta-sigma modulator. It relates to a device configured using an oversampling type digital-to-analog converter.

(Prior Art) As is well known, in the field of digital audio equipment, it has been considered to perform level adjustment such as sound file adjustment through digital processing before digital-to-analog conversion. If level adjustment is performed digitally in this way, it will not only solve various problems such as signal distortion and aging deterioration caused by the conventional use of variable resistors, but it will also promote miniaturization and make it more economical. It can also be advantageous.

FIG. 6 shows such a conventional digital level adjustment circuit. That is, this means that the digital data supplied to the input terminal 11 is converted into a constant by the multiplication circuit 12.
(lak' aO) and output from the output terminal 13, and '' is added to this constant at the control terminal 14.
Level adjustment is performed by controlling with a control signal supplied to the control signal.

However, such conventional digital level adjustment circuits have the following problems. First, the digital multiplication circuit 12 has a much more complicated configuration and tends to be larger in circuit size than a digital addition circuit or the like. Furthermore, by multiplying the constant by ', the bit length of the digital data to be handled increases. For example'
-1/4 (attenuation rate 12 dB), the seventh
As shown in the figure, 16-bit digital data is increased by 2 bits to become 18-bit. 7 Furthermore, the attenuation rate is 1
Multiplying by a fraction like dB (-0,891) gives us
This results in an increase in the number of bits.

On the other hand, in digital audio equipment, digital data is ultimately converted from digital to analog, but increasing the number of bits of this digital to analog converter by 1 bit causes a considerable economic disadvantage, and also Increasing the number by more than a few bits becomes technically difficult. Furthermore, if the increased number of bits is rounded off or rounded off, there will be an inconvenience that if distortion occurs in the low-level signal, it will disappear.

(Problem to be Solved by the Invention) As described above, the conventional digital level adjustment circuit has a complicated and large circuit configuration, and also has the problem of ε, which causes performance deterioration and economic disadvantage due to an increase in bit length. have.

Therefore, this invention was made in consideration of the above circumstances, and provides an extremely good digital level that is economically advantageous and can perform high-performance level adjustment with a simple configuration without increasing the bit length. The purpose is to provide a regulating circuit.

[Structure of the Invention] (Means for Solving the Problem) A digital level adjustment circuit according to the present invention includes an addition means for adding human-powered digital data and feedback data, and a binary quantization of the output data of the addition means. It comprises a quantization means, a subtraction means for calculating the difference between the output data of the quantization means and the output data of the addition means, and a filter means for digitally processing the output data of the subtraction means to generate feedback data. The target is a delta-sigma modulation circuit.

Then, a predetermined constant kin) is applied to the output data of the quantization means.
The quantization means has a multiplication means that multiplies the result and supplies the result to the subtraction means, and is configured to adjust the level of the output data of the quantization means by controlling the value of the constant.

(Function) According to the above configuration, the full scale level of the delta-sigma modulation circuit can be increased by multiplying the output data of the quantization means by a predetermined constant k (1m1) and supplying the resultant to the subtraction means. Furthermore, the level of the input digital data can be equivalently lowered to adjust the level of the output data from the quantization means.

Also, considering that the output data of the quantization means is only binary, the multiplication means for multiplying this output data by
It can be configured with a simple logic circuit, and the circuit scale can be reduced.

Furthermore, the number of bits increases by multiplying the output data of the quantization means, but in a delta-sigma modulation circuit of second or higher order, the calculations within the loop are originally much larger than the number of bits of human-powered digital data. Therefore, as long as the value of the constant does not become extremely large, problems such as an increase in circuit scale and bit truncation will not occur.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings. In FIG. 1, 15 is an input terminal to which digital data is supplied. The digital data supplied to the input terminal 15 is added to the feedback data output from the filter circuit 17 by the adder circuit 1B. The data y output from this adder circuit 16 is supplied to a binary quantization circuit 18. This binary quantization circuit 18
As shown in FIG. 2, when input data y is positive, it is a 16-bit + side full scale value, and when it is negative, it is data y' corresponding to m 16-bit full scale values.
Output.

The data y' outputted from the binary quantization circuit L8 is multiplied by a predetermined constant k(al) in the multiplication circuit t9, and then the subtraction circuit 20 calculates the difference from the output data y of the addition circuit 1B. data e is calculated, and the filter circuit 1
7. Note that the constant of the multiplication circuit 19 can be varied by a control signal supplied to the control terminal 21. The filter circuit 17 generates the feedback data by digitally processing the data e so as to reduce the power of the quantization noise of the quantization circuit 18 in the low frequency region. In addition,
Data y' outputted from the binary quantization circuit 18 is converted into an analog signal by a 1-bit D/A (digital/analog) conversion circuit 22 and taken out from an output terminal 23.

Here, an adder circuit 1B excluding the multiplier circuit 19 described above.

Filter circuit 17. Binary quantization circuit 18 and subtraction circuit 2
0 constitutes a delta-sigma modulation circuit.

In this case, the number of bits of the adder circuit 16 is the first-order delta ◆
For sigma modulation, the number of bits may be the same as that of human digital data, but for second-order or higher delta-sigma modulation, 20 bits or more are required. Therefore, if the IS bit full-scale value output from the binary quantization circuit 18 is expressed in 20 bits, it becomes a 16-bit + side full-scale value 0000011111111111111116 bits m full-scale values 11111000000000000001.

If the value is used as it is around ε, the multiplier circuit 19 will be 2
This results in a bit length of 0 bits or more. Therefore, if we spread the full scale value by ILSB on both the positive and negative sides, we get a 16-bit positive full scale value oooooiooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo of 16 bits.

The m full-scale values of 16 bits are 11111000000000000000, which means that only the upper 5 bits need to be calculated.

This upper 5 bit data is supplied to the multiplication circuit 19. Since this multiplier circuit 19 has only two input values, it can be realized with a very simple configuration. That is, FIGS. 3 and 4 show the constant multiplied by the value ε and the result y' when the attenuation rate is set to 0 to 15 dB. As can be seen, the multiplication circuit 19 can be constructed using a simple logic circuit, ROM (read-only memory), or the like. There is no essential difference between FIG. 3 and FIG. 4 except that the number of operation bits is 12 bits and 8 bits, and the number of operation bits is determined by the degree of accuracy of the attenuation rate. Practically speaking, it is sufficient to use the number of bits shown in FIG.

Then, by multiplying the output of the binary quantization circuit 18 by the multiplication circuit 19, the signal component of the output of the binary quantization circuit 18 is attenuated to 1/k. The output signal of the conversion circuit 22 is also attenuated to 1/k.

Thereafter, the subtraction circuit 20 subtracts the output data y' of the multiplication circuit 19 from the output data y of the addition circuit 18. If the values shown in FIG. 4 are used, the number of bits for the subtraction circuit 20 will be 8 bits. The output data e of the subtraction circuit 20 is then supplied to the filter circuit 17 to generate feedback data. Characteristic H of this filter circuit 17
In the case of zero-order delta-sigma modulation, (Z) becomes )1(Z)-1-(1-Z-1).

FIG. 5 shows another embodiment of the invention.

That is, the output of the subtraction circuit 20 is supplied to the addition circuit 1B via the delay circuit 24, and the delta-sigma modulation is performed by an addition circuit 25, a filter circuit 26, a binary quantization circuit 271, a multiplication circuit 28, and a subtraction circuit 29. supply to the circuit. Then, by the subtraction circuit 30, the binary quantization circuit 2
7, the data delayed by the delay circuit 31 is subtracted, and the subtracted output is added to the output of the binary quantization circuit 18 by the addition circuit 32, and then sent to the 1-bit D/A conversion circuit 22. We are trying to supply it.

The circuit shown in FIG. 5, except for the multiplication circuits 19 and 28, is called a multi-stage noise shaping (MASH) type digital/analog conversion circuit, and by cascading delta-sigma modulation circuits, This is intended to reduce quantization noise. In this type of digital/analog conversion circuit, in exactly the same way as in the above embodiment, each output of a plurality of binary quantization circuits 18.27 is multiplied by a multiplication circuit 19.28. By supplying the signal to the subtraction circuits 20 and 29, high-performance digital level adjustment can be performed.

It should be noted that the present invention is not limited to the above-described embodiments, and can be implemented with various modifications without departing from the gist thereof.

[Effects of the Invention] As detailed above, according to the present invention, high-performance level adjustment can be performed with a simple configuration without increasing the bit length, and an extremely good digital level that is economically advantageous can be achieved. :A! 1 circuit can be provided.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram showing an embodiment of the digital level adjustment circuit according to the present invention, FIG. 2 is a characteristic diagram of a binary quantization circuit of the same embodiment, and FIGS. 3 and 4 are respectively the same embodiment. FIG. 5 is a block diagram showing another embodiment of the present invention; FIG. 6 is a block diagram showing a conventional digital level adjustment circuit; FIG. 7 is a diagram for explaining the problems of the conventional circuit. 11...Input terminal, 12...Multiplication circuit, 13...
Output terminal, 14...control terminal, 15...input terminal,
16...Addition circuit, 17...Filter circuit, 18.
...Binary quantization circuit, 19...Multiplication circuit, 20...
Subtraction circuit, 21...control terminal, 22...1 bit D
/A conversion circuit, 23... Output terminal, 24... Delay circuit, 25... Addition circuit, 2B... Filter circuit, 2
7... Binary quantization circuit, 28... Multiplication circuit, 29.
30... Subtraction circuit, 3t... Delay circuit, 32...
addition circuit.

Claims (1)

[Claims] Adding means for adding input digital data and feedback data, quantizing means for binary quantizing the output data of this adding means, and calculating the difference between the output data of this quantizing means and the output data of the adding means. In the delta-sigma modulation circuit, the delta-sigma modulation circuit is provided with a subtraction means for digitally processing the output data of the subtraction means to generate the feedback data, and a predetermined constant k(
≧1) and supplying the result to the subtracting means, the method is configured to adjust the level of the output data of the quantization means by controlling the value of the constant k. Features a digital level adjustment circuit.