JPH0339849U - - Google Patents
Info
- Publication number
- JPH0339849U JPH0339849U JP10052989U JP10052989U JPH0339849U JP H0339849 U JPH0339849 U JP H0339849U JP 10052989 U JP10052989 U JP 10052989U JP 10052989 U JP10052989 U JP 10052989U JP H0339849 U JPH0339849 U JP H0339849U
- Authority
- JP
- Japan
- Prior art keywords
- eyelets
- connects
- strip plate
- punched
- row
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 2
Landscapes
- Packaging Frangible Articles (AREA)
Description
第１図ａ，ｂは本考案の一実施例を示す平面図
、側面図、第２図ａ，ｂは従来のダイオードの組
立てに用いる半導体用ヘツダの一例を示す平面図
、断面図、第３図はキヤリアテープでヘツダを搬
送する状態の一例を示す側面図である。
１……アイレツト、２，３……リード、６……
主フレーム、７……連結フレーム。なお、各図中
同一符号は同一または相当する部分を示す。
1A and 1B are a plan view and a side view showing an embodiment of the present invention; FIGS. 2A and 2B are a plan view and a sectional view showing an example of a conventional semiconductor header used for assembling a diode; The figure is a side view showing an example of a state in which a header is transported using a carrier tape. 1... Eyelet, 2, 3... Lead, 6...
Main frame, 7...Connection frame. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
個のアイレツトを設け、該帯状板の上記アイレツ
トを連結する部分を打抜き加工により上記複数個
のアイレツトを一体に連結するリードフレーム状
に加工し、上記各アイレツトにそれぞれ所要のリ
ードを取付けた半導体用ヘツダ。 A plurality of eyelets are provided in a row at equal intervals on a strip plate by deep drawing, and a portion of the strip plate that connects the eyelets is punched into a lead frame shape that connects the plurality of eyelets together; A semiconductor header with the required leads attached to each of the above eyelets.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10052989U JPH0339849U (en) | 1989-08-30 | 1989-08-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10052989U JPH0339849U (en) | 1989-08-30 | 1989-08-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0339849U true JPH0339849U (en) | 1991-04-17 |
Family
ID=31649535
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10052989U Pending JPH0339849U (en) | 1989-08-30 | 1989-08-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0339849U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5314566A (en) * | 1976-07-26 | 1978-02-09 | Hitachi Ltd | Assembling method of cap sealed type semiconductor device |
-
1989
- 1989-08-30 JP JP10052989U patent/JPH0339849U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5314566A (en) * | 1976-07-26 | 1978-02-09 | Hitachi Ltd | Assembling method of cap sealed type semiconductor device |
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