JPH0336844A - Packet communication system - Google Patents

Abstract

PURPOSE:To easily attain transit from an STM node into an ATM node by arranging buffer memories collectively to an input section or an intermediate section of a multi-stage switching circuit network and excluding a buffer memory from each unit switch. CONSTITUTION:Packets distributed in a distributed network are stored tentatively in buffer memories (1-1)-(1-8). Unit switches (9-9)-(9-20) in a routing network decide an output port to be transferring an input cell with a destination header or a tag given to its cell. When collision takes place, one of two input packets is selected at random and the selected packet is transferred to an output circuit. Moreover, the incomplete transfer of the packet not selected to a sender buffer memory is informed. The buffer memory stores each packet till the transfer is finished. When the incomplete transfer is noticed, the packet is sent again. Thus, the replacement of a tag of the transmission line is applied by a packet disassembler and the result is outputted.

Description

[Detailed description of the invention] [Industrial application field] INDUSTRIAL APPLICATION This invention is utilized for the communication network for digital signals.

The present invention relates to a technique for facilitating migration from cross-connect nodes used in synchronous transmission networks. The present invention relates to a cross-connect node for an asynchronous transmission network.

[Conventional technology]

BACKGROUND OF THE INVENTION With the advancement of the information society, communications are diversified and have increased capacity, and large-capacity transmission systems for this purpose are being developed. In the future, in order to efficiently accommodate large-capacity lines on transmission lines, it is desired to realize large-capacity terminal stations with line setting functions. In this large-capacity terminal station, it has been found that a node configuration using self-routing switches is suitable for efficiently accommodating large amounts of information on the transmission path. A self-routing switch selects a switch and a route based on the header or tag of a packet 7) signal with a destination, and can configure a large-scale switch circuit with a smaller amount of hardware than a crossbar switch.

Conventional research on self-routing switches can be broadly divided into two types. The first is a synchronous relocation type non-blocking self-routing switch, which is suitable for a synchronous transmission network called STM. The second type is an asynchronous self-routing switch, which is suitable for an asynchronous transmission network called ATM. The present invention relates to the latter asynchronous closed self-routing switch.

FIG. 4 shows a configuration example of a conventional synchronous relocation type non-blocking self-runing switch suitable for STM. The configuration shown in FIG. 4 is an input buffer type Benes network, and the input signal is once set to 1 in buffer memories 1-1 to 1-8 at the input end, and speed conversion is performed by packet assemblers 21 to 2-8. As shown in Figure 3, this conversion assumes that the signal on the transmission path constitutes one frame in a certain unit time, and by increasing the speed of this 17 frames, space for the header is secured and the header is added. and packetize it. In this header, the number of the outgoing line to which the input signal should originally be output is expressed in binary. A packet signal for one frame to which a header is attached passes through the Benes network by self-routing.

When a line setting change occurs in this method, the relocation calculation circuit 5 calculates a passage route and attaches or replaces the header at the time of the setting change. This new header allows each input signal to pass through a different route within the Benes network to the output side.

On the output side, packet disassemblers 4-1 to 4-8
At , the header is removed, speed conversion is performed, and the output is performed. Further, in the case of temporary line relocation due to construction work, etc., a backup line can be specified in advance, and the line combinations at that time can be preloaded into the relocation calculation circuit.

Relocation calculation algorithms include the Looping algorithm for the Benes network, and the Lee algorithm.
) algorithm, connected network algorithm, etc. have been proposed.

When used in the above-mentioned ATM suitable for asynchronous self-routing and immediately processes packets that are input asynchronously, intensive relocation processing is not required for route setting in each asynchronous self-routing switch. A method is necessary.

FIG. 6 shows a conventional configuration when a Benes network is used as a self-routing switch.

This example consists of a distributed network in the first half and a routing network in the second half. Here, in the first half of the distributed network, unit switches 6-1 ~
6-8 randomly distributes input packets, and in the latter half of the routing network, each unit switch 6-9 to 6-2
0 determines the output port based on the tag attached to the input packet, and performs routing using distributed control. here,
As shown in FIG. 7, each unit switch consists of buffer memories 7-1 to 7-2.2×2 switches 8, and when contention for the same output port occurs, the buffer memory of this unit switch We will meet at . Therefore, this unit switch has no buffer memory.
It has a completely different configuration from the unit switches 3-1 to 3-20 in the figure.

[Problem to be solved by the invention]

It is expected that the network configuration will shift from STM to ATM in the future, and in that case, the STM cross-connect node shown in Figure 4 will be modified from the ATM cross-connect node shown in Figure 6. This is difficult because the configurations of the element unit switches are completely different. Therefore, it is necessary to replace the entire cross-connect node. Also, the number G
When switching high-speed signals of b/s or higher, the configuration of a unit switch with an ultra-high-speed buffer memory is as follows:
There are also drawbacks that are undesirable in terms of circuit device processing and heat generation.

An object of the present invention is to provide a cross-connect node that can easily migrate to ATM by utilizing most of the hardware configuration in STM.

[Means to solve the problem]

The present invention is characterized in that buffer memories are centrally arranged at the input section or intermediate section of a multi-stage switch network, and the buffer memories are removed from each unit switch. In the conventional technology, each unit switch has a buffer memory and packets are queued to avoid collisions, but in the present invention, the contents of the buffer memory are not temporarily discarded even after the packet is sent, and packet collisions occur. The difference is that if this occurs, it is notified to the input section or the buffer memory in the intermediate section, and retransmitted from there.

〔Example〕

FIG. 1 is a block diagram of a first embodiment of the present invention. Code 1-1
-1-8 is a buffer memory, 2-1 to 28 are packet assemblers, 4-1 to 4-8 are packet disassemblers, and 9-1 to 9-20 are unit switches used in the present invention.

The input packets are given output port numbers used within this node in the packet assemblers 2-1 to 2-28. In this configuration, unit switches 9-1 to 9-8
It can also be divided into a distributed network consisting of buffer memories 1-1 to 1-8 and a routing network consisting of unit switches 9-9 to 9-20. The purpose of the distributed network is to reduce the number of packet collisions in the routing network by averaging the amount of packets staying in the buffer memory in the intermediate section. There is a random distribution algorithm as a distribution algorithm, and the unit switch configuration in that case is shown in FIG. Here, codes 10-1 to 10-2
is an input circuit, 11 is a 2-input 2-output switch, 12 is an output control circuit, 13 is a random selection circuit, 14-1 to 14-
2 is an output circuit. Input circuit 10-l or (0-2
When a packet is input to , the random selection circuit 13 determines which output port should be output, and sets the switch 11 through the output control circuit 12 . If packets are input to both input circuits 10-1 and 10-2, both packets are output to the output circuit so as not to conflict.

Packets distributed in a distributed network are stored in buffer memory 1.
-1 to 1-8 are temporarily stored. The unit switches 9-9 to 9-20 in the routing network determine the output port to which an input cell should be transferred, based on the destination header or tag given to the cell.

The decision algorithm is the same as a normal algorithm when the routing network is viewed as an inverse baseline network. In each unit switch, if a packet is input to only one input circuit, or even if a packet is input to both input circuits, but the output circuits to which each packet should be transferred are different, the above-mentioned The data may be transferred to the output circuit determined by the method. However, if packets are input to both input circuits and the output circuits of the respective packets are the same, a collision will occur because each unit switch is not provided with a buffer memory.

If a collision occurs, one of the two input packets is randomly selected and only it is forwarded to the output circuit determined as described above. Furthermore, for packets that are not selected, the sender buffer memory is notified that the transfer has not been completed. The buffer memory stores each packet until the transfer is completed. Then, if a notification that the transfer is incomplete is received, the transfer is retransmitted. The packets that have passed through the final unit switch in this manner are tagged and retagged for the transmission path by a packet disassembler, and then output.

FIG. 3 is a configuration diagram illustrating a second embodiment of the present invention. This configuration can be divided into a distributed network consisting of unit switches 9-1 to 9-8 and a routing network consisting of unit switches 9-9 to 9-20. The purpose of the distributed network and routing network is the same as in the first embodiment. In the following, a case will be described in which the unit switches shown in FIG. 2 are used in a distributed network, similar to the first embodiment.

In the packet assemblers 2-1 to 28, input packets are given output port numbers used within this node. And that bucket 7) is the buffer memory l-1~
1-8 and transferred to the distributed network. When a packet is input to any of the unit switches 91 to 9-8 in the distributed network, the input circuit 1 of that unit switch
When a packet is input to 01 or 10-2, the random selection circuit 13 determines which output port should be output, and sets the switch 11 through the output control circuit 12. If packets are input to both input circuits 10-1 and 10-2, both packets are output to the output circuit so as not to conflict.

Packets distributed in the distributed network are immediately input to the routing network. Unit switches 9-9 to 9-20 in the routing network determine the output port to which an input cell should be transferred, based on the destination header or tag given to the cell.

The decision algorithm is the same as a normal algorithm when the routing network is viewed as an inverse baseline network. In each unit switch, when a packet is input to only one input circuit, or even when a packet is input to both input circuits, if the output circuit to which each packet should be transferred is different, the above-mentioned The data may be transferred to the output circuit determined by the method. However, if packets are input to both input circuits and the output circuits of the respective packets are the same, a collision occurs because each unit switch does not have a buffer memory.

In the event of a collision, one of the two human covers is selected at random and only it is transferred to the output circuit determined as described above. It also notifies the selector memory that the transfer has not been completed. In buffer memory,
Accumulate each packet until the transfer is completed,
If you receive a notification that the transfer is incomplete, resend. The packets that have passed through the final unit switch in this manner are tagged and retagged for the transmission path by a packet disassembler, and then output.

〔Effect of the invention〕

As explained above, by removing the buffer memory from each unit switch and concentrating the buffer memory in the input section or intermediate section, it is possible to easily control the buffer memory location even in STM by equipping a circuit for collision notification in advance. Just by changing from the input part to the middle part (first embodiment),
It is possible to easily migrate from an STM node to an ATM node. Furthermore, in the case of the second embodiment, there is no need to change the location of the buffer memory, making it easier to migrate from an STM node to an ATM node.

[Brief explanation of drawings]

FIG. 1 is a system diagram for explaining the first embodiment of the present invention. FIG. 2 is a block diagram of unit switches in a distributed network in the first embodiment. FIG. 3 is a system configuration diagram illustrating a second embodiment of the present invention. FIG. 4 is a configuration example of a synchronous relocation type non-blocking self-routing switch suitable for STM. FIG. 5 is an explanatory diagram of speed conversion in a packet assembler/disassembler. FIG. 6 shows the conventional configuration of an ATM node when a Benes network is used as a self-runing switch. FIG. 7 shows the configuration of a unit switch in a conventional configuration. 1-1 to 1-8...buffer memory, 2-1 to 2-8
...Bucket assembler, 3-1 to 3-20...S
Single-billion unit switch for TM - 1 to 4-8...Packet disassembler, 5...Relocation calculation circuit, 6-1 to 6
-20...ATM unit switch, 7-1 to 72...
・Buffer memory, 8...2X2 switch, 91~9
-20... ATM unit switch without buffer, 10-1 to 10-2... Input circuit, 11...2
Output switch, 12... Output control circuit, 13... Random selection circuit, 14-1 to 14-2... Output circuit.

Claims (1)

[Claims] 1. A multi-stage distributed circuit network configured with a plurality of 2×2 switches as unit switches, a multi-stage routing circuit network configured with a plurality of 2×2 switches as unit switches, and temporarily storing packets. In a packet communication system comprising a plurality of buffer memories, the plurality of buffer memories are arranged centrally at each input port of the multistage routing circuit network, and a collision between two packets occurs in the multistage routing circuit network. in case of,
The unit switch in which the collision occurred routes one of the packets, and for the other packet, it notifies the buffer memory into which the packet has been input of the occurrence of the collision and discards the packet, and the packet is routed from the buffer memory. A packet communication method characterized by having a means for retransmission. 2. A multi-stage distributed circuit network configured with a plurality of 2×2 switches as unit switches; a multi-stage routing circuit network configured with a plurality of 2×2 switches connected after the multi-stage distributed circuit network as unit switches; A packet communication system comprising a plurality of buffer memories for temporarily storing packets, wherein the buffer memories are arranged centrally at the front stage of the multi-stage distributed circuit network for each port of the distributed circuit network, and in the multi-stage routing circuit network. When a collision occurs between two packets, one of the packets is routed at the unit switch where the collision occurred, and the buffer memory that inputs the other packet is notified of the collision and the packet is discarded. A packet communication method comprising means for retransmitting the packet from the buffer memory.