JPH0335286Y2 - - Google Patents
Info
- Publication number
- JPH0335286Y2 JPH0335286Y2 JP4798386U JP4798386U JPH0335286Y2 JP H0335286 Y2 JPH0335286 Y2 JP H0335286Y2 JP 4798386 U JP4798386 U JP 4798386U JP 4798386 U JP4798386 U JP 4798386U JP H0335286 Y2 JPH0335286 Y2 JP H0335286Y2
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- reference potential
- capacitor
- switch
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000003990 capacitor Substances 0.000 claims description 24
- 230000000903 blocking effect Effects 0.000 claims description 2
- 238000007599 discharging Methods 0.000 description 13
- 238000010586 diagram Methods 0.000 description 10
- 230000000694 effects Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 1
Landscapes
- Feedback Control In General (AREA)
- Control Of Voltage And Current In General (AREA)
- Filters And Equalizers (AREA)
Description
【考案の詳細な説明】
〔産業上の利用分野〕
本考案は、生体信号測定装置の入力回路などに
用いて好適の基線復帰回路に関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a baseline return circuit suitable for use in an input circuit of a biological signal measuring device.
本考案は、入出力端間にコンデンサが接続され
出力端に基準電位が接続された信号回路におい
て、基準電位と信号回路電圧の大小関係に応じて
コンデンサの出力側電極に正又は負の電位源を接
続することにより、コンデンサの充（放）電時間
を短縮したものである。
In a signal circuit in which a capacitor is connected between input and output terminals and a reference potential is connected to the output terminal, this invention applies a positive or negative potential source to the output side electrode of the capacitor depending on the magnitude relationship between the reference potential and the signal circuit voltage. By connecting , the charging (discharging) time of the capacitor is shortened.
第５図は従来例を示す回路図で、同図Ａに示す
ように、入力と出力側がコンデンサＣによつて直
流的に遮断され、出力端に基準電位を設定するた
めの抵抗Ｒが並列に接続された信号回路は、種々
の分野で使用されているが、いま、入力にノイズ
によつて例えば第２図○イに示すような正極性の直
流電圧が現われたとすると、出力端には第２図○ロ
のような電圧となつて現われる。すなわち、基線
の動揺が発生する。これが測定回路において妨害
（誤差）となることは、いうまでもない。
Figure 5 is a circuit diagram showing a conventional example. As shown in Figure A, the input and output sides are DC-blocked by a capacitor C, and a resistor R is connected in parallel to set a reference potential at the output end. Connected signal circuits are used in various fields, but if a positive DC voltage as shown in Figure 2 (○) appears due to noise at the input, a signal will appear at the output terminal. It appears as a voltage as shown in Figure 2. In other words, baseline fluctuation occurs. Needless to say, this causes interference (error) in the measurement circuit.
この対策として、従来は、第５図Ｂに示すよう
に抵抗Ｒと並列に充放電用スイツチSW１を接続
し、負又は正の妨害電圧が発生したときにこのス
イツチSW１を閉じコンデンサＣを充又は放電さ
せていた。なお、γはスイツチSWIがオン時の内
部抵抗を示す。 As a countermeasure against this, conventionally, a charging/discharging switch SW1 is connected in parallel with the resistor R as shown in FIG. It was being discharged. Note that γ indicates the internal resistance when the switch SWI is on.
上述の従来技術では、妨害電圧を基準電位に対
して充放電するので、第２図○ハに示すように基線
の復帰が遅い欠点がある。
In the above-mentioned conventional technology, since the disturbance voltage is charged and discharged with respect to the reference potential, there is a drawback that the return to the baseline is slow, as shown in FIG.
したがつて、本考案は、妨害電圧が現われたと
きの基線復帰を急速に行なわせようとするもので
ある。 Therefore, the present invention attempts to quickly return to the baseline when a disturbance voltage appears.
本考案は、基準電位と信号回路電圧（コンデン
サＣの出力側電圧）を比較し、両電圧の大小関係
に応じて正又は負の電位を供給すると共にスイツ
チ手段を制御する比較制御手段を設けた。このス
イツチ手段は、信号回路電圧が基準電位より高い
場合は負電位に、逆の場合は正電位にコンデンサ
Ｃの出力側電極を接続するように構成した。
The present invention is provided with a comparison control means that compares the reference potential and the signal circuit voltage (the output side voltage of the capacitor C), supplies a positive or negative potential depending on the magnitude relationship between the two voltages, and controls the switch means. . This switch means is configured to connect the output side electrode of the capacitor C to a negative potential when the signal circuit voltage is higher than the reference potential, and to a positive potential when the signal circuit voltage is higher than the reference potential.
上記の構成により、妨害電圧発生時コンデンサ
Ｃの充放電が急速に行われる。
With the above configuration, the capacitor C is rapidly charged and discharged when a disturbance voltage occurs.
第１図は、本考案の基本的実施例を示す簡略回
路図である。同図において、第５図と対応する部
分には同一の符号を付した。破線で囲んだ部分は
充放電部、SW２は充放電電圧切換スイツチ、
COMは誤差比較部を示す。充放電部内には、従
来と同様な充放電スイツチSW１のほかに充放電
電圧切換スイツチSW２が含まれる。誤差比較部
COMの一方の入力はコンデンサＣの出力側電極
に、他方の入力は基準電位に接続する。コンデン
サＣは入出力間すなわち信号回路に挿入されてい
るので、コンデンサＣの出力側電圧を信号回路電
圧と呼ぶことにする。誤差比較部COMは、信号
回路電圧と基準電位を比較し、信号回路電圧が基
準電位より高いとき切換スイツチSW２を負電位
源−Ｖが接続されたａ側に、信号回路電圧が基準
電位より低いとき切換スイツチSW２を正電位源
＋Ｖが接続されたｂ側に切換える出力を発生す
る。スイツチSW１の動作は、別に発する充放電
開始信号によつて制御してもよく、誤差比較部
COMの出力によつて制御するようにしてもよい。
FIG. 1 is a simplified circuit diagram showing a basic embodiment of the present invention. In this figure, parts corresponding to those in FIG. 5 are given the same reference numerals. The part surrounded by the broken line is the charging/discharging part, SW2 is the charging/discharging voltage switch,
COM indicates the error comparison section. The charging/discharging section includes a charging/discharging voltage changeover switch SW2 in addition to the conventional charging/discharging switch SW1. Error comparison section
One input of COM is connected to the output side electrode of capacitor C, and the other input is connected to a reference potential. Since the capacitor C is inserted between the input and output, that is, in the signal circuit, the output side voltage of the capacitor C will be referred to as the signal circuit voltage. The error comparison unit COM compares the signal circuit voltage and the reference potential, and when the signal circuit voltage is higher than the reference potential, switches SW2 to the a side to which the negative potential source -V is connected, and sets the signal circuit voltage to the side a where the negative potential source -V is connected. At this time, an output is generated to switch the changeover switch SW2 to the b side to which the positive potential source +V is connected. The operation of switch SW1 may be controlled by a charge/discharge start signal issued separately, and the error comparison section
It may also be controlled by COM output.
本回路の動作は、次のとおりである。充放電用
スイツチSW１は常開スイツチで平常時は開放さ
れているので、信号回路においてはコンデンサＣ
の入力信号を微分した波形をそのまま出力するこ
とができる。いま、入力にノイズによつて例えば
第２図○イに示すような正極性の直流電圧が印加さ
れたとすると、図示しない検出器がこれを検出し
て発生する充放電開始信号により又は誤差比較部
COMの出力信号により、スイツチSW１をオン
にする。誤差比較部COMは、上記の直流電圧
（第２図○イ）を基準電位と比較し、この場合は前
者が後者より高いので、例えば常開スイツチであ
る充放電電圧切換スイツチSW２をａ側に切換え
る出力信号を発生する。その結果、コンデンサＣ
の出力側電極に逆電圧である負電圧が加えられる
ので、コンデンサＣに充電された電荷は第２図○ニ
のように急速に放電される。上記のノイズによる
直流電圧が基準電位より低い場合は、充放電電圧
切換スイツチSW２がｂ側に切換えられ、上述と
同様にして充電が急速に行われる。誤差比較部
COMには信号回路の電圧がフイードバツクされ
ているので、信号回路電圧と基準電位の電位差が
０になつた時点で切換スイツチSW２を開放する
ようにすれば、出力電圧は第２図○ホのようにな
り、短時間で基線が安定することになる。切換ス
イツチSW２をこのように構成することは容易で
あるので、詳細説明は省略する。 The operation of this circuit is as follows. The charge/discharge switch SW1 is a normally open switch and is open during normal times, so the capacitor C is used in the signal circuit.
The waveform obtained by differentiating the input signal can be output as is. Now, if a positive DC voltage as shown in Figure 2 ○A is applied to the input due to noise, a detector (not shown) detects this and generates a charging/discharging start signal or an error comparator.
Switch SW1 is turned on by the COM output signal. The error comparison unit COM compares the above DC voltage (○A in Figure 2) with the reference potential, and in this case, since the former is higher than the latter, for example, it changes the charging/discharging voltage changeover switch SW2, which is a normally open switch, to the a side. Generates an output signal to switch. As a result, capacitor C
Since a negative voltage, which is a reverse voltage, is applied to the output side electrode of the capacitor C, the charge stored in the capacitor C is rapidly discharged as shown in FIG. When the DC voltage due to the above noise is lower than the reference potential, the charge/discharge voltage changeover switch SW2 is switched to the b side, and charging is performed rapidly in the same manner as described above. Error comparison section
Since the voltage of the signal circuit is fed back to COM, if the changeover switch SW2 is opened when the potential difference between the signal circuit voltage and the reference potential becomes 0, the output voltage will be as shown in Figure 2 (○). , and the baseline becomes stable in a short time. Since it is easy to configure the changeover switch SW2 in this way, detailed explanation will be omitted.
第３図は、本考案の実際的な実施例を示す簡略
回路図である。本例は、第１図の誤差比較部
COMと充放電電圧切換スイツチSW２を１個の
演算増幅器（オペアンプ）Ａ１で置き換えたもの
である。一般に、オペアンプには正電位源と負電
位源が接続されており、その出力端には、開放時
２つの入力電圧の大小関係に応じてこの正又は負
の電源電圧が現われている。よつて、コンデンサ
Ｃ出力側の電圧（信号回路電圧）が基準電位より
大き（小さ）いとき出力端に負（正）の電源電圧
が現われるようにすれば、スイツチSW１のオン
時にコンデンサＣは負（正）の電位源に接続され
ることになる。本例では、誤差比較部と充放電電
圧切換スイツチとを１個のオペアンプICで済ま
せるので、安価で部品点数が少ない回路が得られ
る。 FIG. 3 is a simplified circuit diagram showing a practical embodiment of the invention. This example uses the error comparison section in Figure 1.
The COM and charging/discharging voltage switching switch SW2 are replaced with one operational amplifier (op-amp) A1. Generally, a positive potential source and a negative potential source are connected to an operational amplifier, and a positive or negative power supply voltage appears at the output terminal of the operational amplifier depending on the magnitude relationship between the two input voltages when the operational amplifier is open. Therefore, if a negative (positive) power supply voltage appears at the output terminal when the voltage on the output side of capacitor C (signal circuit voltage) is larger (smaller) than the reference potential, capacitor C becomes negative when switch SW1 is turned on. (positive) potential source. In this example, since the error comparator and the charge/discharge voltage changeover switch are completed with one operational amplifier IC, a circuit can be obtained at low cost and with a small number of parts.
第４図は第３図の変形例を示すもので、同図Ａ
は説明用、同図Ｂが構成を示す簡略回路図であ
る。第４図Ａに示すように、第３図の実施例の出
力側にもう１つのオペアンプＡ２を接続した場
合、オペアンプＡ２の入力にはオフセツト電流ｉ
が流れるので、コンデンサＣに入力信号が印加さ
れないときでも電圧が発生する。この電圧は、ス
イツチSW１がオフのとき v1＝iRであり、スイ
ツチSW１がオフのとき、
v2＝ｉ（Rγ／Ｒ＋γ）
である。したがつて、スイツチSW１の動作に伴
い、v1とv2の電圧差が出力されて出力が変動す
る。第４図Ｂは、この点を改良した構成を示すも
ので、上記スイツチSW１に対応するスイツチ
SW３を図示の位置に設けてある。平常時、スイ
ツチSW３はａ側に接続され、入力信号はそのま
ま出力される。充放電開始信号によりスイツチ
SW３をｂ側に切換えると、オペアンプＡ１によ
りコンデンサＣの充放電が行なわれるが、基準入
力電位がv1＝iRにしてあるからコンデンサＣの
出力側もv1と同じ電圧となる。したがつて、その
時点で、スイツチSW３をａ側に戻しても、オペ
アンプＡ２の入力電位とコンデンサＣの充電電位
とは同じなので出力変動は発生しない。第４図Ｂ
のものは、オペアンプの入力インピーダンスが高
いことを利用したものである。 Figure 4 shows a modification of Figure 3.
1 is a simplified circuit diagram for explanation, and FIG. 2B is a simplified circuit diagram showing the configuration. As shown in FIG. 4A, if another operational amplifier A2 is connected to the output side of the embodiment shown in FIG.
flows, so a voltage is generated even when no input signal is applied to capacitor C. This voltage is v 1 =iR when switch SW1 is off, and v 2 =i(Rγ/R+γ) when switch SW1 is off. Therefore, as the switch SW1 operates, the voltage difference between v1 and v2 is output, and the output fluctuates. Figure 4B shows a configuration that improves this point, and shows a switch corresponding to the above switch SW1.
SW3 is provided at the position shown. Under normal conditions, the switch SW3 is connected to the a side, and the input signal is output as is. Switched by charge/discharge start signal
When SW3 is switched to the b side, the operational amplifier A1 charges and discharges the capacitor C, but since the reference input potential is set to v 1 =iR, the output side of the capacitor C also has the same voltage as v 1 . Therefore, even if the switch SW3 is returned to the a side at that point, no output fluctuation occurs because the input potential of the operational amplifier A2 and the charging potential of the capacitor C are the same. Figure 4B
The first one takes advantage of the high input impedance of the operational amplifier.
以上本考案の好適な実施例について説明した
が、本考案は、上述の実施例に限らず、実用新案
登録請求の範囲内において種々の変形・変更をし
うるものである。 Although the preferred embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and can be modified and changed in various ways within the scope of the claims for utility model registration.
本考案によれば、次のような種々の顕著な効果
が得られる。
According to the present invention, the following various remarkable effects can be obtained.
(イ) コンデンサの充放電時間を極めて短くできる
ので、基線復帰を急速に行うことができる。(a) Since the charging and discharging time of the capacitor can be extremely shortened, a return to the baseline can be performed rapidly.
(ロ) 充放電時間を短くできるため、オン抵抗値の
高い安価なスイツチを使用できる。(b) Since the charging/discharging time can be shortened, an inexpensive switch with a high on-resistance value can be used.
(ハ) 信号回路電圧と基準電位との電圧差を０にで
きるので、充放電完了後の基線の動揺が小さく
なる。(c) Since the voltage difference between the signal circuit voltage and the reference potential can be made zero, fluctuations in the baseline after charging and discharging are completed are reduced.
第１図は本考案の基本的実施例を示す簡略回路
図、第２図は本考案の効果を示すための波形図、
第３図は本考案の実際的な実施例を示す簡略回路
図、第４図は第３図の変形例を示す簡略回路図、
第５図は従来例を示す回路図である。
Ｃ……直流阻止コンデンサ、Ｒ……基準電位設
定抵抗、COM，Ａ１……比較制御手段、SW１，
SW２，SW３……スイツチ手段。
Fig. 1 is a simplified circuit diagram showing a basic embodiment of the present invention, Fig. 2 is a waveform diagram showing the effects of the present invention,
FIG. 3 is a simplified circuit diagram showing a practical embodiment of the present invention, FIG. 4 is a simplified circuit diagram showing a modification of FIG. 3,
FIG. 5 is a circuit diagram showing a conventional example. C...DC blocking capacitor, R...Reference potential setting resistor, COM, A1...Comparison control means, SW1,
SW2, SW3... Switch means.
Claims (1)
出力端に基準電位設定抵抗を介して基準電位が接
続された信号回路において、 上記基準電位と上記信号回路電圧を比較し、こ
れら両電圧の大小関係に応じて正又は負の電位を
供給すると共にスイツチ手段を制御する比較制御
手段を具え、 上記スイツチ手段は、上記基準電位と上記信号
回路電圧に大小関係が発生したときに作動して上
記コンデンサの出力側電極を上記正又は負の電位
供給手段に接続し、上記両電圧が等しくなると復
旧することを特徴とする基線復帰回路。[Scope of claim for utility model registration] A DC blocking capacitor is connected between the input and output terminals,
In a signal circuit in which a reference potential is connected to the output terminal via a reference potential setting resistor, the reference potential and the signal circuit voltage are compared, and a positive or negative potential is supplied depending on the magnitude relationship between these two voltages. Comparison control means for controlling the switching means is provided, and the switching means is activated when a magnitude relationship occurs between the reference potential and the signal circuit voltage to connect the output side electrode of the capacitor to the positive or negative potential supply means. A baseline return circuit characterized in that the circuit is connected to the base line and recovers when the two voltages become equal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4798386U JPH0335286Y2 (en) | 1986-03-31 | 1986-03-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4798386U JPH0335286Y2 (en) | 1986-03-31 | 1986-03-31 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62157502U JPS62157502U (en) | 1987-10-06 |
| JPH0335286Y2 true JPH0335286Y2 (en) | 1991-07-26 |
Family
ID=30869093
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4798386U Expired JPH0335286Y2 (en) | 1986-03-31 | 1986-03-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0335286Y2 (en) |
-
1986
- 1986-03-31 JP JP4798386U patent/JPH0335286Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62157502U (en) | 1987-10-06 |
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