JPH0334855B2 - - Google Patents
Info
- Publication number
- JPH0334855B2 JPH0334855B2 JP59240201A JP24020184A JPH0334855B2 JP H0334855 B2 JPH0334855 B2 JP H0334855B2 JP 59240201 A JP59240201 A JP 59240201A JP 24020184 A JP24020184 A JP 24020184A JP H0334855 B2 JPH0334855 B2 JP H0334855B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- film
- forming
- insulating film
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 15
- 239000004065 semiconductor Substances 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 13
- 239000004020 conductor Substances 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 238000001947 vapour-phase growth Methods 0.000 claims description 7
- 230000008018 melting Effects 0.000 claims description 6
- 238000002844 melting Methods 0.000 claims description 6
- 238000007740 vapor deposition Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- 230000008569 process Effects 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 229910021332 silicide Inorganic materials 0.000 claims description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-M Chloride anion Chemical compound [Cl-] VEXZGXHMUGYJMC-UHFFFAOYSA-M 0.000 claims 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 claims 1
- 229910001510 metal chloride Inorganic materials 0.000 claims 1
- 229910001512 metal fluoride Inorganic materials 0.000 claims 1
- 230000002093 peripheral effect Effects 0.000 claims 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 16
- 239000007789 gas Substances 0.000 description 10
- 238000001020 plasma etching Methods 0.000 description 6
- 239000010410 layer Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 239000010955 niobium Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 150000007513 acids Chemical class 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 150000001805 chlorine compounds Chemical class 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 150000002222 fluorine compounds Chemical class 0.000 description 1
- 230000008570 general process Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 150000002736 metal compounds Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- -1 molybdenum (Mo) Chemical class 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- NXHILIPIEUBEPD-UHFFFAOYSA-H tungsten hexafluoride Chemical compound F[W](F)(F)(F)(F)F NXHILIPIEUBEPD-UHFFFAOYSA-H 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、半導体装置の製造方法に係わり、特
に多層配線を断線なく形成する方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming multilayer wiring without disconnection.
従来の二層配線構造の半導体装置の一例を第３
図に示す。３１は拡散層等の回路要素が形成され
たｐ型シリコン基板である。この基板３１上に酸
化シリコン膜３２を介して第１の配線３３が形成
されている。第１の配線３３が形成された基板表
面は再び、酸化シリコン膜３４により覆われる。
この酸化シリコン膜３４に接続孔３５を設けて、
この接続孔３５を介して第１の配線３３にコンタ
クトする第２の配線３６が形成されている。
An example of a semiconductor device with a conventional two-layer wiring structure is shown in Part 3.
As shown in the figure. 31 is a p-type silicon substrate on which circuit elements such as a diffusion layer are formed. A first wiring 33 is formed on this substrate 31 with a silicon oxide film 32 interposed therebetween. The substrate surface on which the first wiring 33 is formed is again covered with a silicon oxide film 34.
A connection hole 35 is provided in this silicon oxide film 34,
A second wiring 36 is formed which contacts the first wiring 33 through this connection hole 35.
従来の一般的なプロセスでは、層間絶縁膜であ
る酸化シリコン膜３４に接続孔３５を開ける選択
エツチングの工程で、マスク合せずれがあると接
続孔３５の位置が図示のように第１の配線３３上
からはずれる。そうすると、図に示したようにオ
ーバーエツチングによる細溝３７が第１の配線３
３の接続孔３５端部に形成され、この部分で第２
の配線３６は断線を生じ易いという問題がある。 In the conventional general process, in the selective etching process for opening the connection hole 35 in the silicon oxide film 34, which is an interlayer insulating film, if there is a misalignment of the mask, the position of the connection hole 35 is shifted to the first wiring 33 as shown in the figure. It comes off from the top. Then, as shown in the figure, a narrow groove 37 due to overetching is formed on the first wiring 3.
3 is formed at the end of the connection hole 35, and the second
There is a problem that the wiring 36 is easily broken.
このような配線の断線を防ぐために従来一般に
行われているのは、接続孔に対応したマスクパタ
ーンを形成する際のパターンの合せずれを考慮し
て、第１の配線を少なくとも接続孔の位置で接続
孔の寸法より大きくすることである。しかしこの
ようにすると、第１の配線を加工技術の限界によ
り決まる最小寸法の間隔をもつて配設することが
できない。このことは、集積回路の集積度を向上
させる上で障害となる。 In order to prevent such disconnection of the wiring, what has been generally done is to take into account misalignment of the patterns when forming a mask pattern corresponding to the connection hole, and to remove the first wiring at least at the position of the connection hole. The size should be larger than that of the connecting hole. However, in this case, it is not possible to arrange the first wirings with minimum distances determined by the limitations of processing technology. This poses an obstacle to increasing the degree of integration of integrated circuits.
本発明の目的は、素子の集積度を低下させるこ
となく、接続孔での配線の断線を確実に防止する
ことができ、素子信頼性の向上をはかり得る半導
体装置の製造方法を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that can reliably prevent disconnection of wiring at connection holes and improve device reliability without reducing the degree of integration of the device. be.
本発明の方法は、半導体基板上の絶縁膜に配線
パターンに対応した溝若しくは孔をを形成し、こ
の溝若しくは孔に、選択気相成長法によりその深
さより厚く且つ少なくとも前記溝若しくは孔の周
縁部を覆う広さの導電性物質膜を埋め込むことに
より第１の配線を形成する。この選択気相成長
は、溝若しくは孔の底部表面が活性化されている
場合に可能である。そして第１の配線が形成され
た基板に更に絶縁膜を形成し、この絶縁膜に接続
孔を形成して、この接続孔を介して第１の配線に
コンタクトする第２の配線を形成する。
In the method of the present invention, a groove or a hole corresponding to a wiring pattern is formed in an insulating film on a semiconductor substrate, and the groove or hole is thickened by a selective vapor deposition method, and is thicker than the depth of the groove or hole and at least at the periphery of the groove or hole. A first wiring is formed by embedding a conductive material film having a width that covers the area. This selective vapor phase growth is possible if the bottom surface of the groove or hole is activated. Then, an insulating film is further formed on the substrate on which the first wiring is formed, a connection hole is formed in this insulating film, and a second wiring is formed in contact with the first wiring through this connection hole.
本発明によれば、第２の配線を第１の配線に接
続するための接続孔のエツチングに際し、マスク
パターンのずれがあつても、接続孔端部に微細な
溝ができない。何故なら、選択気相成長法により
堆積される、第１の配線としての導電性物質膜を
溝の深さより厚くすることにより、この導電性物
質膜の上部が溝の幅より広い範囲までカバーする
状態となるからである。従つて本発明によれば、
第２の配線の断線を確実に防止でき、半導体装置
の信頼性の向上をはかり得る。また接続孔位置で
の配線幅を大きくする必要がないので、配線を加
工限界で決まる間隔まで詰めて配列することがで
きる。従つて本発明は、高集積化半導体装置の多
層配線形成にとつて極めて有効となる。
According to the present invention, when etching a connection hole for connecting a second wiring to a first wiring, even if a mask pattern is misaligned, a fine groove cannot be formed at the end of the connection hole. This is because by making the conductive material film as the first interconnect, which is deposited by selective vapor deposition, thicker than the depth of the trench, the upper part of this conductive material film covers a wider area than the width of the trench. This is because it becomes a state. According to the invention, therefore:
Disconnection of the second wiring can be reliably prevented, and reliability of the semiconductor device can be improved. Furthermore, since there is no need to increase the width of the wiring at the connection hole position, the wiring can be arranged close to the spacing determined by the processing limit. Therefore, the present invention is extremely effective for forming multilayer wiring in highly integrated semiconductor devices.
第１図ａからｆは本発明の一実施例を示す工程
断面図である。まず、ａに示す如く素子が形成さ
れたシリコン基板１１上に第１の絶縁膜として
SiO2膜１２を形成し、さらに第２の絶縁膜とし
て膜厚0.8μｍのSiO2膜１３を形成する。この後、
SiO2膜１３上に、周知のPEP工程により第１の
配線の形成予定領域に窓を有するレジストマスク
１４を形成する。
FIGS. 1a to 1f are process sectional views showing one embodiment of the present invention. First, as shown in a, a first insulating film is formed on a silicon substrate 11 on which elements are formed.
A SiO 2 film 12 is formed, and a SiO 2 film 13 having a thickness of 0.8 μm is further formed as a second insulating film. After this,
A resist mask 14 having a window in a region where the first wiring is to be formed is formed on the SiO 2 film 13 by a well-known PEP process.
次に、ｂに示したように例えばCF4とH2との混
合ガスを用いた反応性イオンエツチング（RIE）
法により、第２の絶縁膜であるSiO2膜１３をエ
ツチングして第１の配線形成予定領域に沿つて溝
若しくは孔１５（１５1，１５2）を形成する。 Next, as shown in b, for example, reactive ion etching (RIE) using a mixed gas of CF 4 and H 2 is performed.
By etching the SiO 2 film 13, which is the second insulating film, grooves or holes 15 (15 1 , 15 2 ) are formed along the region where the first wiring is to be formed.
次に、レジストマスク１４を除去した後、溝若
しくは孔１５内に、WF6（六弗化タングステン）
ガスとH2を用いた気相成長法によりＷ（タングス
テン）膜を約1μｍの厚さ埋め込んで第１の配線
１６（１６1，１６2）を形成する。これによりｃ
に示したように、第１の配線１６の上部は溝若し
くは孔１５の幅より広がつてSiO2膜１３をカバ
ーする状態となる。この時のＷ膜の被着条件とし
ては基板温度250℃〜500℃、反応炉内の圧力１×
10-3〜760Torr，WF6ガスの分圧１×10-4〜５×
10-2Torrの範囲が望ましい。また選択成長が起
こるのは、RIEによりエツチングしたことによ
り、SiO2膜の溝若しくは孔１５の底部表面が活
性化されることに起因していると推定される。 Next, after removing the resist mask 14, WF 6 (tungsten hexafluoride) is added into the groove or hole 15.
The first wiring 16 (16 1 , 16 2 ) is formed by filling a W (tungsten) film to a thickness of about 1 μm by a vapor phase growth method using gas and H 2 . This allows c
As shown in FIG. 2, the upper part of the first wiring 16 becomes wider than the width of the groove or hole 15 and covers the SiO 2 film 13. The conditions for depositing the W film at this time are a substrate temperature of 250°C to 500°C, and a pressure of 1× in the reactor.
10 -3 ~760Torr, Partial pressure of WF 6 gas 1×10 -4 ~5×
A range of 10 -2 Torr is preferred. It is also presumed that the selective growth occurs because the bottom surfaces of the grooves or holes 15 in the SiO 2 film are activated by etching by RIE.
なお、第１の配線１６を基板１１にコンタクト
させる場合にはその部分の断面は例えば第２図の
ようになつている。すなわちSiO2膜１２にSiO2
膜１３を重ねる前に、SiO2膜１２に接続孔２２
を形成し、この接続孔２２に、選択気相成長法に
より予めＷ膜２３を埋め込んでおく。これによ
り、第１の配線１６1は、Ｗ膜２３を介して基板
１１表面の拡散層２１に接続される。 In addition, when the first wiring 16 is brought into contact with the substrate 11, the cross section of that portion is as shown in FIG. 2, for example. That is, SiO 2 in the SiO 2 film 12
Before overlapping the membrane 13, connect holes 22 are formed in the SiO 2 membrane 12.
is formed, and a W film 23 is filled in advance in this connection hole 22 by selective vapor deposition. Thereby, the first wiring 16 1 is connected to the diffusion layer 21 on the surface of the substrate 11 via the W film 23.
次にｄに示すように第３の絶縁膜として、例え
ばSiH4とN2Oガスとを用いたプラズマ気相成長
法によるSiO2膜１７を約0.8μｍの厚さ形成した
後、このSiO2膜１７上に、PEPにより接続孔形
成用の窓を有するレジストマスク１８を形成す
る。レジストマスク１８の窓の幅は、第１の配線
１６の下部の幅、すなわち溝若しくは孔１５の幅
と同一寸法である。図では、パターンの合わせず
れのため、レジストマスク１８の窓が僅かにずれ
て形成された場合を示している。 Next, as shown in d, a SiO 2 film 17 with a thickness of about 0.8 μm is formed as a third insulating film by, for example, plasma vapor deposition using SiH 4 and N 2 O gas, and then this SiO 2 A resist mask 18 having a window for forming a contact hole is formed on the film 17 by PEP. The width of the window of the resist mask 18 is the same as the width of the lower part of the first wiring 16, that is, the width of the groove or hole 15. The figure shows a case where the windows of the resist mask 18 are formed with slight deviations due to misalignment of patterns.
次にｅに示したように例えばCF4とH2との混合
ガスを用いたRIE法によりSiO2膜１７を選択エツ
チングして、第１の配線１６に対する接続孔１９
を形成する。エツチング条件として例えば、CF4
流量を24c.c.／min、H2流量を10c.c.／min、圧力を
1.33pa、高周波電力を150Wとする。この場合、
SiO2膜１７のエツチング速度が〜400Å／minに
対して、Ｗ膜からなる第１の配線１６のエツチン
グ速度は〜10Å／minと遅い。従つてこの様な条
件でエツチングすれば、第１の配線１６の表面が
露出した後は、ほとんどエツチングは進まず、ｅ
に示したように、接続孔１９が形成される。 Next, as shown in e, the SiO 2 film 17 is selectively etched by RIE using, for example, a mixed gas of CF 4 and H 2 to form the connection hole 19 for the first wiring 16.
form. For example, CF 4 as an etching condition.
Flow rate is 24c.c./min, H2 flow rate is 10c.c./min, pressure is
1.33pa, high frequency power 150W. in this case,
While the etching rate of the SiO 2 film 17 is ~400 Å/min, the etching rate of the first wiring 16 made of the W film is slow at ~10 Å/min. Therefore, if etching is performed under these conditions, after the surface of the first wiring 16 is exposed, the etching will hardly proceed and e.g.
As shown in FIG. 2, a connection hole 19 is formed.
次いで、前記レジストマスク１８を除去した
後、ｆに示すように、接続孔１９を介して第１の
配線１６にコンタクトする第２の配線２０を形成
する。この第２の配線２０は例えば、マグネトロ
ンスパツタ法により厚さ約1μｍのアルミニウム
（Al）膜を被着した後、これを例えばCCl4とCl2
との混合ガスを用いたRIE法により、パターニン
グすることにより形成される。 Next, after removing the resist mask 18, as shown in f, a second wiring 20 is formed which contacts the first wiring 16 through the connection hole 19. For example, this second wiring 20 is made by depositing an aluminum (Al) film with a thickness of about 1 μm by magnetron sputtering method, and then coating it with, for example, CCl 4 and Cl 2 .
It is formed by patterning using the RIE method using a mixed gas with.
こうして形成された第２の配線２０は、ｆから
も判るように、第１の配線１６との接続のために
設けられた接続孔１９での被覆性は非常によい。
接続孔１９が合わせずれをもつて形成されている
にも拘らず、第１の配線１６がその上部で幅広く
なつているために、従来のようなオーバーエツチ
ングによる細溝が形成されないからである。従つ
て第２の配線２０の断線は確実に防止され、多層
配線構造の半導体装置の信頼性が向上する。 As can be seen from f, the thus formed second wiring 20 has very good coverage in the connection hole 19 provided for connection with the first wiring 16.
This is because although the connection holes 19 are formed with misalignment, the first wiring 16 is wider at its upper portion, so that a thin groove is not formed by over-etching as in the conventional method. Therefore, disconnection of the second wiring 20 is reliably prevented, and the reliability of the semiconductor device with the multilayer wiring structure is improved.
上記実施例では、第１の配線の形成に際し
WF6ガスによるＷ膜の気相成長を用いた場合に
ついて説明したが、WCl6ガスを用いてもよい。
またモリブデン（Mo）、ニオブ（Nb）、タンタル
（Ta）、チタン（Ti）など他の高融点金属の弗化
物や塩化物による気相成長膜を利用することもで
きる。またこれらの金属化合物ガスとSiH4，
SiH2l2等の混合ガスによる高融点金属硅化物の気
相成長膜を用いても同様の結果が得られる。 In the above embodiment, when forming the first wiring,
Although the case of using vapor phase growth of a W film using WF 6 gas has been described, WCl 6 gas may also be used.
It is also possible to use a vapor phase growth film using fluorides or chlorides of other high melting point metals such as molybdenum (Mo), niobium (Nb), tantalum (Ta), and titanium (Ti). In addition, these metal compound gases and SiH 4 ,
Similar results can be obtained by using a vapor phase growth film of a high melting point metal silicide using a mixed gas such as SiH 2 l 2 .
また上記実施例では、第１図ｂの溝若しくは孔
１５形成の工程でRIEを用いることにより、溝若
しくは孔１５の底部表面を同時に活性化した。次
の選択気相成長工程での必要のために溝若しくは
孔１５の底部表面を活性化することは、他のエツ
チング法、例えばスパツタエツチング、化学的ド
ライエツチング（CDE）、酸や塩基を用いた湿式
エツチングを用いた場合にも可能である。この溝
若しくは孔の底部表面の活性化処理は、エツチン
グ工程とは別に、電子線照射、レーザ照射などに
より行なうこともできる。 Further, in the above embodiment, by using RIE in the step of forming the groove or hole 15 shown in FIG. 1b, the bottom surface of the groove or hole 15 was activated at the same time. Activating the bottom surface of the grooves or holes 15 for the needs of the next selective vapor deposition step can be accomplished using other etching methods such as sputter etching, chemical dry etching (CDE), acids or bases. This is also possible when wet etching is used. The activation treatment of the bottom surface of the groove or hole can also be performed by electron beam irradiation, laser irradiation, etc., separately from the etching step.
また上記実施例では、第２の配線２０としてア
ルミニウム膜を用いたが、モリブデン、タングス
テン、プラチナ（Pt）あるいはそれらの硅化物
でもよく、さらにはこれらの積層膜を用いた場合
にも本発明は有効である。 Further, in the above embodiment, an aluminum film is used as the second wiring 20, but molybdenum, tungsten, platinum (Pt) or silicides thereof may be used, and the present invention also applies when a laminated film of these is used. It is valid.
さらに上記実施例では２層配線について述べた
が、本発明は３層以上の多層配線に適用しても同
様な効果が得られる。 Further, in the above embodiment, a two-layer wiring was described, but the same effect can be obtained even when the present invention is applied to a multilayer wiring having three or more layers.
第１図ａ〜ｆは本発明の一実施例を示す工程断
面図、第２図は第１の配線を基板にコンタクトさ
せる部分での第１図ｃに対応する断面図、第３図
は従来の製造方法により製造された半導体装置の
断面図である。
１１……シリコン基板、１２……SiO2膜（第
１の絶縁膜）、１３……SiO2膜（第２の絶縁膜）、
１４，１８……レジストマスク、１５（１５1，
１５2）……溝若しくは孔、１６（１６1，１６2）
……第１の配線、１７……SiO2膜（第３の絶縁
膜）、１９……接続孔、２０……第２の配線。
1A to 1F are process sectional views showing one embodiment of the present invention, FIG. 2 is a sectional view corresponding to FIG. 1 is a cross-sectional view of a semiconductor device manufactured by the manufacturing method of FIG. 11... Silicon substrate, 12... SiO 2 film (first insulating film), 13... SiO 2 film (second insulating film),
14, 18...Resist mask, 15 (15 1 ,
15 2 )...Groove or hole, 16 (16 1 , 16 2 )
...First wiring, 17...SiO 2 film (third insulating film), 19... Connection hole, 20... Second wiring.
Claims (1)
と、前記第１の絶縁膜が形成された基板上に第２
の絶縁膜を形成する工程と、前記第２の絶縁膜を
選択的にエツチングして第１の配線の形成予定領
域に溝若しくは孔を形成する工程と、選択気相成
長法により前記溝若しくは孔にその深さより厚く
且つ少なくとも前記溝若しくは孔の周縁部を覆う
広さの導電性物質膜を堆積することにより第１の
配線を形成する工程と、前記第１の配線が形成さ
れた基板上に第３の絶縁膜を形成する工程と、前
記第３の絶縁膜を選択エツチングして前記第１の
配線に対する接続孔を形成する工程と、前記接続
孔を介して前記第１の配線にコンタクトする第２
の配線を形成する工程とを備えたことを特徴とす
る半導体装置の製造方法。 ２ 前記第１の配線を形成する工程は、高融点金
属の弗化物または塩化物ガスを用いた気相成長法
により、前記導電性物質膜として高融点金属膜を
堆積するものである特許請求の範囲第１項記載の
半導体装置の製造方法。 ３ 前記第１の配線を形成する工程は、高融点金
属の弗化物または塩化物ガスとシリコンを含むガ
スを用いた気相成長法により、前記導電性物質膜
として高融点金属の硅化物膜を堆積するものであ
る特許請求の範囲第１項記載の半導体装置の製造
方法。 ４ 前記第１の配線を形成する工程に先だち、前
記溝の底部表面を活性化する処理を行なう特許請
求の範囲第１項記載の半導体装置の製造方法。[Claims] 1. A step of forming a first insulating film on a semiconductor substrate, and a step of forming a second insulating film on the substrate on which the first insulating film is formed.
forming an insulating film, selectively etching the second insulating film to form a groove or hole in a region where the first wiring is to be formed, and etching the groove or hole by selective vapor deposition. forming a first wiring by depositing a conductive material film thicker than the depth and having a width that covers at least the peripheral edge of the groove or hole, and depositing a conductive material film on the substrate on which the first wiring is formed. forming a third insulating film; selectively etching the third insulating film to form a connection hole for the first wiring; and contacting the first wiring through the connection hole. Second
1. A method of manufacturing a semiconductor device, comprising the step of forming a wiring. 2. The step of forming the first wiring is a step of depositing a high melting point metal film as the conductive material film by a vapor phase growth method using a high melting point metal fluoride or chloride gas. A method for manufacturing a semiconductor device according to scope 1. 3. In the step of forming the first wiring, a silicide film of a high melting point metal is formed as the conductive material film by a vapor phase growth method using a gas containing fluoride or chloride gas of a high melting point metal and silicon. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is deposited. 4. The method of manufacturing a semiconductor device according to claim 1, wherein prior to the step of forming the first wiring, a process is performed to activate the bottom surface of the trench.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24020184A JPS61119059A (en) | 1984-11-14 | 1984-11-14 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24020184A JPS61119059A (en) | 1984-11-14 | 1984-11-14 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61119059A JPS61119059A (en) | 1986-06-06 |
| JPH0334855B2 true JPH0334855B2 (en) | 1991-05-24 |
Family
ID=17055959
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24020184A Granted JPS61119059A (en) | 1984-11-14 | 1984-11-14 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61119059A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5998535A (en) * | 1982-11-29 | 1984-06-06 | Hitachi Ltd | Manufacture of semiconductor integrated circuits |
-
1984
- 1984-11-14 JP JP24020184A patent/JPS61119059A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5998535A (en) * | 1982-11-29 | 1984-06-06 | Hitachi Ltd | Manufacture of semiconductor integrated circuits |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61119059A (en) | 1986-06-06 |
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