JPH0334635A - Receiving phase monitoring method - Google Patents

Abstract

PURPOSE:To always monitor a phase error by inserting a bit monitor bit for showing the phase error corresponding to a slave station by using a clock synchronizing with a reference clock extracted from data which is being transmitted, receiving it in a base station, and displaying the phase error quantity in accordance with each station. CONSTITUTION:A frame signal FR is demarcated into two directions by a switching part 24, one of them is demarcated so as to fetch an acquisition burst wave ACQ, and the other is demarcated so as to fetch data (A, B...N). The respective demarcated signals are impressed to clock extracting parts 25, 26, and a clock CK2 synchronizing with CK1 is extracted. Subsequently, based on the clock CK2, a phase error to the reference clock CK1 is detected by an MB inserting part 27, and it is converted to a digital code and inserted into a monitor bit MB. Also, a base station 11 extracts the monitor bit MB being in a prescribed position from in the frame signal, and displays the phase error quantity by a meter 23. In such a way, a receiving phase is monitored.

Description

[Detailed Description of the Invention] [Summary] A series of data transmitted from a plurality of slave stations at timings assigned in advance to each without overlapping each other, and a series of data transmitted in advance according to the needs of any of the slave stations. The frame signal is connected to a transceiver that receives a frame signal constituting one frame by an acquisition burst wave transmitted with a clock synchronized with a reference clock at a predetermined timing, and the frame signal is further inserted with a monitor bit in the transceiver. The base station has a base station that receives the data and performs reception processing, and when receiving the data of each slave station in the phase of the reference clock in the base station, the reference clock and the reception clock synchronized with the reference clock are The purpose of the present invention is to propose a reception phase monitoring method that can constantly monitor the phase error, and when there is the acquisition burst wave, the reference extracted from the acquisition burst wave is A bit representing the phase error detected using a clock synchronized with the clock is inserted into the monitor bit, and when there is no acquisition burst wave, a clock synchronized with the reference clock extracted from the data during data transmission. [Industrial Application Field] The present invention provides a method for detecting a series of data transmitted from a plurality of slave stations at timings assigned to each slave station in advance without overlapping each other. The transmitter/receiver is connected to a transmitter/receiver that receives a frame signal constituting one frame by an acquisition burst wave transmitted with a certain transfer lock at a predetermined timing according to the needs of the slave station, and the transmitter/receiver a base station that receives the frame signal further inserted with a monitor bit and performs reception processing, and a clock (CK2 ), the base station monitors a phase error between the reference clock and a clock (CK2) synchronized with the reference clock.

For example, under the TDM Hatsuto method, from multiple slave stations,
Each piece of data is transmitted to one base station at pre-assigned timings without overlapping each other.

In this case, the base station has a single reference clock, and a clock (CK2) synchronized with the reference clock of each data is brought into phase agreement with the reference clock to perform reception processing within the base station.

A clock (CK
2) There is also a method of individually generating reference clocks whose phases match each other and performing reception processing, but for example,
If reference clocks were generated individually for up to 00 slave stations (channels), it would be economically disadvantageous.

The present invention monitors whether the phase error between the phase of the single reference clock and the phase (reception phase) of the clock synchronized with the reference clock of the received data from each slave station is within an allowable range. The method will be described.

[Conventional technology]

FIG. 6 is a diagram showing an example of a communication system to which the present invention is applied. In the figure, 1 is a base station, and data is exchanged between this and a plurality of slave stations (A, B, . . ., N) 12. In this case, data transmission and reception is performed by the base station 1.
This is done via a transceiver 13 provided in the building where the mobile station 1 is installed and a transceiver 14 provided in the building where each slave station 11 is installed.

FIG. 7 is a diagram showing an example of the data format of data received by the base station. A series of data transmitted from a plurality of slave stations 12 at timings assigned in advance to each without overlapping each other is indicated by A, B...N. In addition to these series of data, ACQ is also inserted.

ACQ is an acquisition burst wave, and is transmitted from any slave station 12 as necessary. It is necessary, for example, when a slave station 12 is newly installed or during periodic maintenance when the reception phase error at the base station 11 becomes large, and is used as a signal for synchronization adjustment of the black one. These A
CQ and A, B...N constitute one frame and form a frame signal FR. Note that ACQ is alternatively shared by all slave stations. A monitor bit MB is inserted into this frame signal FR by the transceiver 13 of the base station 11. The monitor bit MB generally includes a level monitor bit, which detects the level of received data corresponding to each slave station, displays the level amount on the MB, and sends it to the base station 11. If there is data whose level is below a predetermined value, the base station 11 instructs the slave station to increase the transmission level via the downlink.

A base station 11 and a transmitter/receiver 1 that mainly performs a modulation/demodulation function
3, each data A is clocked by its own reference clock CKI.
, B...N. On the other hand, each data A, B
...N is CK generated from the signal received by each slave station 12
It is transmitted by clock CK2 synchronized with I. C.K.
Naturally, I and CK2 are set to the same speed.

However, even if the speed is the same, the base station 11
If a phase error occurs between the phase of I and the reception phase of CK2, correct reception processing will not be possible.

Therefore, it is important to always maintain the phase error within an acceptable range for any slave station.

Therefore, conventionally, maintenance is performed periodically (for example, every other day or every week) to make the reception phase appropriate, using nighttime or other times when the amount of data traffic is low.

This is based on the fact that both the phase of the reference clock CK1 and the phase of the clock CK2 synchronized with CKI are extremely stable, and the probability that the phase error will deviate from the allowable range is extremely low.

[Problem to be solved by the invention]

The above conventional technology has two problems. First, regardless of whether the reception phase is appropriate or not, the slave station 12
Since the phase error is monitored using an acquisition burst wave after data transmission is stopped, if the reception phase is appropriate, the maintenance work ends up being wasted.

The second problem is more serious than the first problem, and is a case where, for example, some equipment failure occurs and the phase error increases rapidly until the next periodic maintenance. In such a case, the line will be disconnected, and the service provided to the user will deteriorate. Also, urgent maintenance work must be started to restore the reception phase to its original proper state using an acquisition burst wave.

SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to propose a reception phase monitoring method that can constantly monitor phase errors.

[Means to solve the problem]

FIG. 1 is a diagram for explaining the present invention in detail. In this figure, the transceiver 13 and base station 11 are as described above, and the base station (1) is newly provided with a display 21 for monitoring the reception phase. switch 22 for selecting
and a meter 23 for displaying the amount of phase error of the selected channel. When the scale of the meter 23 indicates 0, it is a proper phase, when it points to the + side, it is a leading phase, and when it points to the - side, it is a lagging phase.

Lines 2 and L1 each schematically represent a transmission line for transmitting necessary information to the other party to be connected.

[For production]

FIG. 1 schematically depicts only the portions related to the present invention. First, the frame signal FR is divided into two directions by the switching unit 24. One is acquisition burst wave A
One is to separate it to extract CQ, and the other is to extract data (
Cut into pieces to remove A, B...N). The divided signals are sent to clock extractors 25 and 26.
The clock CK2 applied to the CKI and synchronized with the CKI is extracted.

Acquisition burst wave ACQ originally exists for clock synchronization adjustment, and is transferred with high precision to lock C.
K2 can be extracted. This is done by the clock extraction section 25.
It is. However, since ACQ does not always exist, clock CK2 is also extracted from the data. This is the clock extraction section 26. Although the clock extracted from the data is less accurate than the clock extracted from the ACQ,
Clock CK at any time as long as data is being transmitted
The approximate phase of 2 can be grasped.

The presence of ACQ and data can be detected by adding an ACQ level determination circuit (36 in FIG. 2) to the conventional method. That is, the level of the received signal may be monitored at the timing at which ACQ should appear (which the base station 11 itself knows). If the level is high, ACQ exists. Similarly, the level of the received signal is monitored at the timing at which each data should appear (which the base station 11 itself knows).

If the level is high, data is being sent.

Based on the clock CK2 thus obtained, the MB insertion section 27
The phase error with respect to the reference tarlock CKI is detected, converted into a digital code, and inserted into the monitor bit MB. Note that this MB also includes the level monitor bit described above.

Monitor bit MB into which a bit representing phase error is inserted
is placed at a predetermined position within the frame signal FR.

The base station 11 extracts monitor bits MB at specified positions from the frame signal, and particularly selects a bit representing a phase error. This is the MB extraction section 28. The selected phase error amount is displayed on the meter 23 in analog or digital form.

Thus, rather than a level monitor for scheduled maintenance, ACQ
Alternatively, it is possible to monitor the reception phase at all times as long as data exists. Therefore, it is only necessary to instruct the slave station to adjust the clock CK2 only when the phase error approaches the limit of the allowable range, and the line will not be disconnected.

In addition, instructions for the adjustment can be made online via the downlink to the slave station. For example, the final phase adjustment can be performed using ACQ based on the timing when data transmission from the slave station is interrupted. do it.

〔Example〕

FIG. 2 is a diagram showing an example of a circuit for implementing the method of the present invention, and this reception phase monitor circuit 30 is provided within the transceiver 13. Note that this circuit has been devised so that it can not only monitor the reception phase but also monitor the level of the reception signal as before. The signals listed on the left side of the figure will be explained from the top of the figure. RD is received data and is a demodulated baseband signal. CK2 is a clock extracted from this received data RD (or from ACQ), and both are obtained within the transceiver 13. CKI is a reference clock supplied from base station 11, and TAc is also supplied from base station 1.
This data is supplied from 1 and indicates the timing of appearance of acquisition burst waves. RL is the received signal (AC
Q, data) is received level data representing the level of
Obtained within the transmission/reception 1413. T'o'r is data A
, B...N, and is notified from the base station 11. TpH is each frame signal FR
This is a frame timing signal indicating the beginning of the base station 1.
Specified from 1.

The extracted clock CK2 is first passed through a phase detector (Misaki)
31, and the difference (phase error) with respect to the reference clock CKl is detected. This phase error is temporarily held in a sample and hold (S/H) circuit 32, and then converted into digital phase error data in an analog/digital converter (A/D) 33.

The timing of the sample and hold described above must be switched depending on the target from which CK2 is extracted (ACQ, data A, data B, etc.). For this purpose, hold timing control is received from the logic switch (Sill) 37. That is, if the target is ACQ, the switch 37 receives the logic "1" decoded by the decoder 35, which is data indicating the appearance timing of ACQ. Conversely, if the target is data, the incoming timing data T is supplied in accordance with the incoming timing of data A, B...N.
l1l.

A logic “1” decoded by the decoder 41 is received.

The logic switch 37 further includes a flip-flop (FF) 3.
It also receives the output of 6. When the above target is ACQ, there is no point in holding it with the sample hold circuit unless ACQ actually exists.

This is because ACQ appears when necessary and does not always exist. Therefore, the FF 36 determines that the output of the decoder 35 is logic "L" and the received signal level RL
It outputs a logic "1" to the switch 37 after making sure that the voltage is at a sufficient level. That is, for ACQ, the sample and hold is performed only when the outputs of the encoder 35 and the FF 36 match at logic "1". In addition, 3
8 is an amplifier that amplifies the received signal level RL. The output of this amplifier 38 is sampled and held (
A portion of the signal is held in an S/H (S/H) circuit 39, and then converted into digital reception level data in an analog/digital converter (A/D) 40.

The above-mentioned baseband received data RD and A/D 3
Each output of 3 and 40 is multiplexed by a multiplexer (MIX) and output as a frame signal FR as a monitor bit MB.
and sent to the base station 11.

The timing of this multiplexing is determined by the frame timing signal ′
1, and each bit position within the frame signal 4FR is determined in response to a series of bit pulses from the timing counter 42.

FIG. 3 is a diagram showing the groove bottom of the monitor bit extraction section and the display, and shows frame 2.2 containing the monitor bin hMB. Signal F
R is a separator (DEMII) synchronized by the frame timing signal TFR and the reference clock CKI.
X) 51, and in particular, the monitor bit MB portion is extracted. This extraction is performed using registers (REG
) 52 and timing counter 55. The timing counter 55 outputs a level read pulse Pt when a series (for example, 8 bits) of received level data has been stored in the REG 52.

, and then outputs a series (e.g. 8
When the phase error data (bit) has been stored,
A phase error reading pulse Pp is output. In this example,
The meter 23 in the display 21 is used for phase error monitoring,
Since it is shared with the conventional level monitor,
The pulse (PL or PP) to be monitored is manually switched using the switch 56.

The data in the REG 52 is converted to analog by a digital/analog converter (D/A) 53 and displayed on the analog meter 23. If you use a digital meter,
D/A 53 is unnecessary.

FIG. 4 is a timing chart of the main parts of the signals shown in FIG. Column (1) in this figure is an 8-bit register (REG).
8 bits of received level data and 8 bits of phase error data are sequentially stored in 52, by which the monitor bit MB is disciplined. Every time 8 bits are accumulated in REG 52, the above-mentioned received level read pulse PL ((2nd) column) and phase error read pulse Pp ((3rd) column) are output.

Finally, a detailed example of the main parts of the transceiver 13 is shown for reference.

FIG. 5 is a diagram showing a detailed example of the main parts of the base station side transceiver. Where the parts related to the present invention described above are visible, corresponding reference numbers or symbols are given.

Some parts that are not directly visible are included in the logic processing section.

〔Effect of the invention〕

As described above, according to the present invention, a monitoring method that can constantly monitor the reception phase is realized.

[Brief explanation of drawings]

FIG. 1 is a diagram for explaining the present invention in detail, FIG. 2 is a diagram showing an example of a circuit for implementing the method of the present invention, and FIG. 3 is a diagram showing the side of the monitor bit extraction section and the display. Figure 4 is a timing chart of the main parts of the signals in Figure 3, Figure 5 is a diagram showing a detailed example of the main parts of the base station side transceiver, and Figure 6 is a diagram of the communication system to which the present invention is applied. FIG. 7 is a diagram showing an example of a data format of data received by a base station. In the figure, 11...Base station, 12...Slave station, 13...
14...Transmitter/receiver, 21...Display device.

Claims (1)

[Claims] 1. A series of data transmitted from a plurality of slave stations (12) at timings assigned in advance to each without overlapping each other, and according to the needs of any of the slave stations (12). a transceiver (13) that receives a frame signal (FR) constituting one frame using an acquisition burst wave (ACQ) transmitted with a clock (CK2') synchronized with the reference clock at a predetermined timing according to the timing;
and further inserts a monitor bit (MB) in the transceiver (13).
The base station (11) receives the data (FR) and performs reception processing, and the base station (11) has a base station (11) that receives a reference clock (CK1) in the base station (11) and uses the reference clock of the data of each slave station (12) in phase with the reference clock (CK1) in the base station (11). In the method of monitoring the phase error between the reference clock (CK1) and the clock (CK2) synchronized with the reference clock at the base station (11) when receiving the synchronized clocks (CK2) in unison. , when there is the acquisition burst wave (ACQ), a bit representing the phase error detected using the clock (CK2) extracted from the acquisition burst wave and synchronized with the reference clock is inserted into the monitor bit (MB). , When the acquisition burst wave (ACQ) is not present, the bit representing the phase error corresponding to the slave station detected using a clock (CK2) synchronized with the reference clock extracted from the data during data transmission is A reception phase monitoring method characterized by inserting the signal into a monitor bit (MB) and receiving it within the base station (11), and displaying the amount of phase error corresponding to each slave station on a display (21).