JPH033432B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for displaying line status in a data communication system.

(Prior art) In a data communication system consisting of a central processing unit (hereinafter referred to as CPU), a communication control unit (hereinafter referred to as CCE), etc., an attempt is made to visually display the status of messages flowing over the line and the status of communication. Conventionally, the following methods were used to display the transmission/reception status of messages notified to the CPU via CCE: 1. A method of displaying the line status by CPU command to the line display addition mechanism added in the CCE based on the judgment made by the program. ) Adding a circuit for displaying the line status to each line corresponding part of the line control unit of the CCE. The following methods were used:

Figure 6 is an example of the above item), and 3-1 to 3
Data from the line indicated by -n is sent and received under control of CCE2 and passed to CPU1 through bus 4.
Processing for displaying the line status is performed by the program of the CPU 1, and the line display device 5
An instruction is given to display the line status.

Figure 7 is an example of the above item), and 3-1 to 3
Data from the -n line is controlled by CCE2, passed to CPU1 via bus 4, processed to display the line status by the program, and the result is added to display the line status connected to CCE2 via CCE2. A display instruction is given to the mechanism 6.

Figure 8 is an example of the above-mentioned item), and as in the previous example, data from lines 3-1 to 3-n is
Through the line corresponding parts 7-1 to 7-n included in the
It is passed to CPU1 via bus 4 via CCE2. In addition, in order to display the status of the line 3, the line corresponding section 7 is equipped with hardware corresponding to each line, and the interface line 8-- is individually provided to the line status display section 6'.
The line status is displayed by transmitting the line status using 1 to 8-n.

(Problems to be solved by the invention) However, in the method shown in FIG.
Since the line display device 5 serves as an input/output device for the CPU 1, it requires a considerable amount of hardware, and since the line status display processing is performed by the program of the CPU 1, there is a drawback that the load on the program becomes large.

In addition, in the method shown in Figure 7, CCE2
to connect an additional mechanism for line display to
This leads to an increase in the amount of hardware for CCE2, and further
Since the CPU 1 program is responsible for line display processing, there is a drawback that the load on the program increases.

Furthermore, in the method shown in FIG. 8, dedicated hardware must be added to the line handling section 7, and a separate interface line 8 is used from the line handling section 7, so the number of lines is large. This had the disadvantage that the number of interface lines increased.

In addition, in an asynchronous line, the mark lights up when the polarity is space, and goes out when the polarity is the same, so line disconnections may occur, and if the space polarity remains, the light remains on; If the flag code is continuous on the line due to a time filler between frames, etc., it will remain lit, and in any case, the line status display device will show that the data is not being sent or received, even though no data is actually being sent or received. It had the disadvantage that it displayed as if it were transmitting and receiving data.

Therefore, an object of the present invention is to accurately display the transmission and reception status of a line with a simple configuration without imposing a program load on the CPU, without increasing the amount of hardware in the CCE, and without increasing the number of interface lines. The objective is to provide a line status display method that makes it possible to

(Means for Solving the Problems) The present invention provides a communication control device that includes a microprocessor and controls the transmission and reception of data between a central processing unit and a line. A register for holding the line number of the line and a display means for displaying the line under transmission and the line under reception are provided. The line status display method is characterized in that a corresponding line is displayed based on a receiving display command and a line number read from the register.

(Operation) The microprocessor determines whether the line to be displayed is a transmission request or a reception request, and sends a transmission display command or a reception display command to the display means. Further, the line number of the line is stored in a register, and this line number is sent to the display means. The display means displays the corresponding line based on this information.

(Example) The present invention will be described below based on an example with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of the present invention, and shows the internal details of a communication control device (CCE).
The channel interface unit 10 is a CPU (not shown)
This is the part that controls the interface with the microprocessor 11, and is connected to the microprocessor 11. A microprocessor 11 includes a program memory, a data memory, a sequencer instruction holding register, an interrupt control circuit, etc. (not shown), and is a part that controls transmission and reception of the CCE. The line 3 is connected to a line correspondence section 15 corresponding to each line, and the line correspondence section 15 performs serial-to-parallel or serial-to-parallel conversion of transmitted and received data, and sends each character data to the microprocessor 11 through an interrupt circuit (not shown). interrupt. The microprocessor 11 sets the line number that generated the interrupt in the line number register (LNR) 13, and the switching circuit 14 selects the LNR from each line corresponding section 15-1 to 15-n.
The line corresponding section with the line number set to 13 is connected to the microprocessor 11 through the data line 12. As a result, the microprocessor 11 communicates with the line corresponding section that generated the interrupt, determines the content of the interrupt request, and performs processing as necessary depending on the content.

FIG. 2 shows the details of the processing. When an interrupt from the line is notified to the microprocessor 11, the microprogram of the microprocessor 11 determines whether it is a transmission request, a reception request, or something else.
If it is a transmission request interrupt, the next data to be transmitted is prepared, it is determined whether the data is valid for display as a line status display, and if it is valid, a transmitting display command is issued at the same time as the character transmission command. If invalid, only a character transmission command is issued. Also, if it is a reception request,
First, a character reception command is issued, and then it is determined whether or not the received characters are valid for display as a line status display.If valid, a reception display command is issued.

When a transmitting display command or a receiving display command is issued by the microprocessor 11, the contents of the command are held in a command holding register (not shown) in the microprocessor 11, and the contents are transmitted to the command bus signal 1.
6 is sent to the command decoder 17.

Figure 3 shows the contents of the instruction holding register, including an arithmetic control field that controls arithmetic operations of the microprocessor, a memory address control field that controls memory address specification, etc., a transmit/receive display command control field that controls transmit/receive display commands, and a line. It consists of a transmission/reception command control field and the like for controlling commands for communicating with the corresponding section.

When the command decoder 17 decodes the transmitting display command, it outputs it to the signal line 18-1, and when it decodes the receiving display command, it outputs it to the signal line 18-2. At this time LNR
13 holds the number of the line that issued the transmitting display command or the receiving display command, and the signal line 19
is input into the buffer 20 by. Also, the buffer 20 has the aforementioned signal lines 18-1 and 18-
2 is also input, and the output of the buffer 20 is sent to the line status display device 22 and the signal lines 21-1, 21-2,
21-3.

FIG. 4 shows the details of the signal line 21 when displaying the line status of 32 lines.
3 corresponds to 5 bits of line number 0 to 4,
Signal 21-1 is the transmitting display command, signal 21-2 is
corresponds to the receiving display command.

FIG. 5 shows the details of the line status display device 22, in which the signal line buffer 23 is an interface circuit with the signal line 21 between the buffer 20 in the CCE, and the signal line 24-3 is the signal line 21. -3 and means the line number, signal line 24-
1 corresponds to the signal line 21-1 and means a display command during transmission, and the signal line 24-2 corresponds to the signal line 21-2 and means a display command during reception.

When a transmitting display command is issued from the CCE microprocessor 11, a signal 24-1 is output, and the line number 24-3 is decoded by the decoder 25, and the transmitting display latch 27 displays the transmitting display corresponding to the line number. The light is set in the latch and displayed by the light emitting diode 28. Similarly, when a receiving display command is issued from the microprocessor 11, a signal 24-2 is output, and the line number 24-3 is decoded by the decoder 26 and the receiving display latch 29 is output.
Among them, the reception status indicator latch corresponding to the line number is set and displayed by the light emitting diode 30.

(Effects of the Invention) As explained above, in the present invention, the line status display control command is controlled by a microprogram in the communication control equipment (CCE).
This has the advantage that the load on the CPU program is reduced, and since the microprogram in the CCE also normally judges transmission control characters, line status display control can be performed at the same time, and the load on the CCE does not increase. In addition, the amount of hardware for the CCE only needs to be increased by adding one command field and a decoder for that command, and the only interface lines are one each for sending and receiving display commands and a line number. In addition, the line status display device requires only a line number decoder, a display latch for each line, and a light emitting diode for display, so it has the advantage of being able to realize an economical line display device. be.

A description of the CCE microprocessor of the present invention is as follows:
Although an example of a horizontal microprocessor has been shown, it goes without saying that it can be easily implemented using a general-purpose microprocessor.

Furthermore, by using the start-stop synchronization, character synchronization, and frame synchronization synchronization methods and various transmission control procedures, the message is By performing fine-grained control such as displaying only transmission and reception by making minor changes to the CCE microprogram, it is possible to construct a flexible data communication system.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
2 is an operation flowchart of the microprocessor shown in FIG. 1, FIG. 3 is a diagram showing the contents of the instruction holding register in the microprocessor shown in FIG. 1, and FIG. Detailed diagram, Figure 5 is the first
A detailed block diagram of the line status display device 22 shown in FIG.
FIGS. 6 to 8 are block diagrams of conventional line display systems, respectively. 1...Central processing unit (CPU), 2...Communication control device (CCE), 3-1 to 3-n...Line, 4...Bus line, 5...Line display device, 6...Line status display addition mechanism, 6'... Line status display section, 7-1 to 7-n... line correspondence section, 8-1 to 8-n... interface line,
10... Channel interface unit, 11... Microprocessor, 12... Data line, 13... Line number register (LNR), 14... Switching circuit, 15-1
~15-3...Line correspondence section, 16...Command bus signal,
17...Command decoder, 18-1, 18-2, 19,
21-1 to 21-3...signal line, 20...buffer,
22...Line status display device, 23...Signal line buffer, 24-1...Signal corresponding to transmitting display command,
24-2...Signal corresponding to the receiving display command, 24
-3... Line number, 25, 26... Decoder, 27-
1, 27-2...Sending display latch, 28-1, 2
8-2...Light emitting diode, 29-1, 29-2...
Receiving display latch, 30-1, 30-2...Light emitting diode.

Claims (1)

[Claims] 1. In a communication control device that has a microprocessor and controls the transmission and reception of data between the central processing unit and a line, there is a register that holds the line number of the line when transmitting or receiving, and a register that holds the line number of the line when transmitting or receiving. and display means for displaying the line and the line being received, and the display means displays the transmitting display command or the receiving display command in the microprogram sent from the microprocessor, and the line read from the register. A line status display method characterized by displaying a corresponding line based on a number.