JPH0334158B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a bipolar transistor random access memory (RAM) having a redundant configuration.
Particularly regarding its address input section.

[Conventional technology]

Normally, large-capacity MOSRAMs have a redundant configuration, so that when a defective memory cell occurs, a spare row or column is selected when selecting the row or column that contains the defective memory cell. and improve yield. Recently, there has been a movement to apply such a redundant configuration to bipolar transistor RAM.

FIG. 2 shows a recently proposed bipolar transistor static RAM. In FIG. 2, 1 is a 64K static type memory cell array, and 2 is a redundant array. Note that although the redundant array may be an array of two or more rows or columns, in order to simplify the explanation, it is assumed to be a one-row array here. One row of memory cell array 1 is selected by row address buffer 3, word decoder 4, and word driver 5. In other words, external row address signals A ₀ , A ₁ , ..., A ₇ are converted into internal row address signals A ₀ , A 1 , A ₇ by row address buffer 3 .
…, A ₇ and their inverted signals ₀ , ₁ , …,
₇ and these signals A ₀ , A ₁ ,…, A ₇ ,
Upon receiving ₀ , ₁ ,..., ₇ , the word decoder 4
One of the 256 word drivers 5, that is, one of the word lines WL ₀ , WL ₁ , . . . , WL ₂₅₅ is driven. One column of memory cell array 1 is also selected by a similar column selection means (not shown).

If all the cells in the memory cell array 1 are normal, there will be no problem and the circuit in FIG. 2 will function as a normal device. However, if a defective cell is found in the memory cell array 1 in FIG. The row address of the row containing the cell (hereinafter referred to as a defective row address) is written into the address storage circuit 6. The row address signals A ₀ , A ₁ , ..., A ₇ are constantly compared with the defective row address signals A _0R , A _1R , ..., A _7R written in the address storage circuit 6 by the address comparison circuit 7. . As a result, the row address signal
A ₀ , A ₁ , …, A ₇ and defective row address signal A _0R ,
When A _1R , ..., A _7R match, the address comparison circuit 7 drives the driver 8 to select the redundant array 2, and conversely disables the word driver 5 and does not select the memory cell array 1. That's what I do.

FIG. 3 is a detailed block circuit diagram showing an example of the address storage circuit 6 of FIG. 2. As shown in FIG. 3, 1-bit address storage circuits 6-0, 6-corresponding to each row address signal A ₀ , A ₁ , . . . , A ₇
1,..., 6-7 are provided. In other words, row address signals A ₀ , A ₁ , ..., A ₇ are applied, a high voltage such as +5V is applied to the write terminal V _p as a write voltage, and a low voltage such as -5V is applied to one terminal _Vo . and row address signal
A ₀ , A ₁ , ..., A ₇ are written to the 1-bit address storage circuits 6-0, 6-1, ..., 6-7, respectively,
It becomes possible to read out the defective address signals A _0R , A _1R , ..., A _7R .

FIG. 4 is a circuit diagram showing an example of the 1-bit address storage circuit of FIG. 3. In Figure 4, V _cc
is, for example, GND level, V _EE is, for example, -5V,
In other cases, V _o is −5V or less, V _EE is assumed, and V _p
is set to _Vcc only when writing to +5V and at other times. PC is a junction breakdown type PROM cell and has diode characteristics after writing. That is, during writing, a voltage greater than the _CE withstand voltage of the transistor cell is applied between its emitter and collector, shorting the emitter and base.

In Figure 4, the forward voltage of the diode is
If it is 0.8V, the potential of node N ₁ is equal to that of the diode.
-0.8×3=-2.4V due to D ₁ , D ₂ , D ₃ , and the potential of node N ₂ when PROM cell PC is not destroyed (when not written) is due to diodes D ₁ , D ₂ ,
-0.8 x 4 = -3.2V due to D ₃ and D ₄ , and the potential of node N ₂ when PROM cell PC is destroyed (during writing) is -0.8 x due to diode D ₅ and one stage of diode of cell PC. 2=-1.6V. A node for one stage of such a diode
The logic amplitudes of N ₁ and N ₂ are supplied to transistors Q ₂ and Q ₃ that constitute a current switch, and as a result,
The defective address A _iR will be read out via the transistor Q ₄ as an emitter follower.

When performing the write operation shown in Figure 4, the write voltage
V _p is externally raised to +5V, and one voltage V _o is also held at -5V. At this time, if the address signal A _i is high level, the transistor
_Q1 is turned on. As a result, a voltage of _7V or more (for example, approximately 10V in this case) is applied to the PROM cell PC, and as shown in the figure, a current _IW flows and the emitter-base is short-circuited. .

[Problem that the invention seeks to solve]

However, when writing in Figure 4,
A very large write current _Iw is required, and as a result, the write transistor _Q1 becomes large and its load becomes large. As a result, as shown in FIG. 2, address signals A ₀ , A ₁ ,..., with large logic amplitudes are generated.
When A ₇ is directly supplied to the address storage circuit 6 together with the address buffer 3, a large load of the writing transistor Q ₁ is applied to the address signals A ₀ , A ₁ , ..., A ₇ even during non-writing. The problem is that the normal address access time is slow.

[Means for solving problems]

An object of the present invention is to shorten the address access time during normal operations other than when writing, and the means for this purpose is to reduce the logic amplitude of the address signal by using an emitter follower or diode level shift down means, and then input the address signal to the address storage circuit. It is to supply.

[Operation] According to the above-mentioned means, even if the capacity of the write transistor is large, the address amplitude applied to the write transistor other than during writing is small, so that the large load of the write transistor is effectively transferred to the address signal line. will not participate in

〔Example〕

FIG. 1 is a schematic diagram of a metal body showing an embodiment of a semiconductor memory device according to the present invention. In Figure 1,
For FIG. 2, each address signal A ₀ , A ₂ , ..., A ₇
is supplied to the address storage circuit 6 via emitter followers Q ₁₁ , _{Q 12} as level shift down means, diodes D ₁₁ , D ₁₂ , D ₁₃ , and resistors R ₁ , R ₂ . For example, if the high level and low level of the address signal are −0.8V and −1.8V, the address amplitude is 1.0V (=1.8−0.8), and therefore, on the input side of the address buffer 3, Its high and low levels are −1.6V, respectively.
(=-0.8-0.8), -2.6V (=-1.8-0.8),
The address amplitude is still 1.0V (=2.6-1.6).
On the other hand, each node on the input side of the address storage circuit 6
In _N3 , the high level -0.8V of the address signals _A0 , _A1 ,..., _A7 is converted to -0.8-0.8×5 by two stages of emitter followers and three stages of diodes _D11 , _D12 , _D13 . = -4.8V, and the low level -1.8V can become -1.8 - 0.8 x 5 = -5.8V due to the two-stage emitter follower and three-stage diode, but in this case, the minimum power supply voltage is -5V.
Therefore, the low level of each node _N3 is -5V. Therefore, the address amplitude at each node _N3 is
The voltage is reduced to 0.2V (=5.0-4.8), and the address amplitude of the gate of the write transistor _Q1 is further reduced by the resistors _R1 and _R2 . For example, if the address amplitude of the gate of write transistor _Q1 is
If it is 0.1V, the address amplitude is given by the two-stage emitter follower, three-stage diode, and resistor.
This means that 0.1/1 = 1/10.

In this way, except when writing, the address amplitude input to the address storage circuit 6 is made smaller than the address amplitude input to the address buffer 3, so the address storage circuit 6
It is possible to substantially prevent a large load of the write transistor Q ₁ from being applied to the address signal to the address buffer 3. In other words, even if the gate capacitance C _G of the transistor Q ₁ is large, if the voltage amplitude ΔV is small, the charge fluctuation C _G ΔV becomes small, so the load on the write transistor can be ignored.

At the time of writing, the potential V _p is changed from 0V to 5V, so the address amplitude to the write transistor Q ₁ becomes large, and in this case, the address amplitude to the address buffer 3 also becomes even larger. The address amplitude has no effect on the address buffer 3.

In FIG. 1, a two-stage emitter follower, a three-stage diode, etc. are used as the level shift down means, but the number of stages can be changed as appropriate or according to the power supply voltage. For example, all five stages may be diodes, and
If the write voltage is high, the number of stages can be increased to 6 or more, and if the minimum power supply voltage is higher than -5V, the number of stages can be reduced to 4 or less.

〔Effect of the invention〕

As explained above, according to the present invention, since the address amplitude applied to the write transistors is reduced except during writing, the large load of these transistors is no longer applied to the address signal, and as a result, the address access time is shortened. be done.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a semiconductor memory device according to the present invention, FIG. 2 is an overall configuration diagram of a recently proposed RAM using bipolar transistors with a redundant configuration, and FIG. 3 is an address memory shown in FIG. FIG. 4 is a detailed block circuit diagram of circuit 6, which is a circuit diagram showing an example of the 1-bit address storage circuit of FIG. 1: Regular memory cell array, 2: Redundant memory cell array, 3, 4, 5: Regular memory cell selection means, 6: Defective address storage means, 7: Comparison means, Q ₁₁ , Q ₁₂ , D ₁₁ , D ₁₂ , _D13 , _R11 , _R12 : Level shift down means.

Claims (1)

[Scope of Claims] 1. Address input means, regular memory cell selection means for selecting a regular memory cell according to the address received by the address input means, defective address storage for storing a defective address of the regular memory cell. means for comparing the defective address of the defective address storage means with the address received by the address input means, and selecting a redundant memory array when the two match, and disabling the normal memory cell selection means; , provided between the address input means and the defective address storage means, the address input is transmitted to the defective address storage means when writing a defective address, and the address input is transmitted to the defective address storage means during normal memory operation. What is claimed is: 1. A semiconductor storage device comprising: switching means for preventing 2. The semiconductor memory device according to claim 1, wherein the switching means comprises level shift down means, and the address amplitude supplied to the defective address storage means is smaller than the output address amplitude of the address input means. 3. The semiconductor memory device according to claim 2, wherein the level shift down means is obtained by combining an emitter follower, a diode, a resistor, or the like in one stage or in a plurality of stages.