JPH0332223A - Output circuit - Google Patents

Output circuit

Info

Publication number
JPH0332223A
JPH0332223A JP1167603A JP16760389A JPH0332223A JP H0332223 A JPH0332223 A JP H0332223A JP 1167603 A JP1167603 A JP 1167603A JP 16760389 A JP16760389 A JP 16760389A JP H0332223 A JPH0332223 A JP H0332223A
Authority
JP
Japan
Prior art keywords
transistor
output
current
voltage
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1167603A
Other languages
Japanese (ja)
Inventor
Yoshinori Sago
佐合 良教
Yuji Kihara
雄治 木原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP1167603A priority Critical patent/JPH0332223A/en
Publication of JPH0332223A publication Critical patent/JPH0332223A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To reduce output noise by providing a TR in series with an output driver TR, and suppressing an excess current by the said TR. CONSTITUTION:With an L input from an output control signal terminal 2, TRs 4, 5 are turned on and when an H signal is inputted from an input signal terminal 1, the TR 4 is turned on. A voltage of a power potential-(2Xthreshold voltage) is applied to the gate of a TR 13 from a constant voltage generating circuit 1, the TR 13 reaches a saturation current lower than that of the TR 4 to suppress the current supplied from the power terminal to the TR 4. Even when an L signal is inputted from the input signal terminal 1, the TR 5 is turned on and a voltage of a GND level + (2X threshold voltage) is supplied to the gate of the TR 14 from the constant voltage generating circuit 16 to suppress the current. Thus, excess current is suppressed and a cause of noise is eliminated.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は半導体装置の出力回路に関するものである。[Detailed description of the invention] [Industrial application field] The present invention relates to an output circuit for a semiconductor device.

〔従来の技術〕[Conventional technology]

第8図は従来の半導体装置の出力回路の回路図で、図に
釦いて、[11は入力信号端子、(2)は出力側副端子
、131は出力信号端子、14)はゝゝH”IIM動用
P型トラトランジスタ51は1ゝp //駆動用N型ト
ランジスタ、+611−1電源端子、(7)ぽGND端
子、(81けトランジスタ(4)全制御する回路、(9
)はトランジスタj5)を制御する回路、 tlolは
反転回路である。
FIG. 8 is a circuit diagram of an output circuit of a conventional semiconductor device. IIM dynamic P-type transistor 51 is 1p // drive N-type transistor, +611-1 power supply terminal, (7) po GND terminal, (81 transistors (4) complete control circuit, (9
) is a circuit that controls transistor j5), and tlol is an inverting circuit.

次に動作について説明する。出力別副信号(2)よりゝ
′H“ 入力の時、トランジスタ+41 +51はOF
F状態となる。出力制御信号(2)よりゝゝL“入力の
時トランジスタ+41 f5)はON状態となることが
可能となり、入力信号端子illより信号が人力される
と、トランジスタ141 、151に伝達される。 H
//大入力時はP型トランジスタ(4)がON状態とな
り、出力は亀源電位金供給する。又、” L’大入力時
N型トランジスタj51がON状態となり、出力はGN
D電位金供給する。
Next, the operation will be explained. When ``H'' is input from the output-specific sub-signal (2), transistors +41 and +51 are OFF.
It becomes F state. From the output control signal (2), when the input is "L", the transistor +41 f5) can be turned on, and when a signal is input from the input signal terminal ill, it is transmitted to the transistors 141 and 151.H
//When the input is large, the P-type transistor (4) is turned on, and the output is supplied with the source potential gold. In addition, when "L' is a large input, the N-type transistor j51 is in the ON state, and the output is GN.
D-potential gold is supplied.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来の出力回路は以上のように構成されていたので、出
力信号が反転する時、トランジスタVC貫通電流により
瞬時に過大な電流が流れ、電源ラインや出力端子のL−
01i分によって出力電圧に変動が生じる。この電圧変
動がノイズとなり誤動作上越こすという問題点があった
Conventional output circuits are configured as described above, so when the output signal is inverted, an excessive current flows instantaneously due to the through current of the transistor VC, causing the L- of the power supply line and output terminal to flow.
The output voltage varies depending on the amount of 01i. There is a problem in that this voltage fluctuation becomes noise and causes malfunctions.

この発明は上記のような問題魚倉解決するためになされ
たもので、過大な電流を抑制し、ノイズの原因分取り除
いた出力回路を得ることを目的とする。
This invention was made to solve the above-mentioned problems, and its purpose is to obtain an output circuit that suppresses excessive current and eliminates the cause of noise.

〔課題上解決するための手段〕[Means for solving problems]

この発明に係る出力回路は、出力ドライバートランジス
タと直列にトランジスタ分設け、ノイズの原因となる過
大な電流をこのトランジスタ03より抑制するようにし
たものである。
In the output circuit according to the present invention, a transistor is provided in series with the output driver transistor, and excessive current that causes noise is suppressed by the transistor 03.

〔作用〕[Effect]

この発明における出力回路は、出力ドライバートランジ
スタと直列に設けたトランジスタのゲートニ、出力ドラ
イバートランジスタの飽和電流よりも低い飽和電流にな
る電圧金側えることにより、電流が抑制され誤動作を防
止する。
In the output circuit according to the present invention, the current is suppressed and malfunctions are prevented by applying a voltage to the gate of the transistor provided in series with the output driver transistor so that the saturation current is lower than that of the output driver transistor.

〔実施的〕 以下、この発明の一実i [4J (r図について説明
する。
[Practice] Hereinafter, the embodiment of this invention i [4J (r diagram) will be explained.

第1図に釦いて、符号111〜(10)は前記従来のも
のと1−一である。図に釦いて、(+3)は電流制御用
P型トランジスタ、041は電流制御用1N型トランジ
スタ、00はトランジスタ03)’?制御する定電圧発
生回路、(IfIlはトランジスタα4)を制御する定
電圧発生1川路である。
In FIG. 1, the numbers 111 to (10) are 1-1 with the conventional ones. In the diagram, (+3) is a P-type transistor for current control, 041 is a 1N-type transistor for current control, and 00 is a transistor 03)'? This is a constant voltage generation circuit that controls a constant voltage generation circuit (IfIl is a transistor α4).

次に動作について説明する。前記従来の出力回路で説明
した様に、出力!1i−INfflJ信号端子12)よ
り11L I!大入力時、トランジスタ031151は
ON状態となることが可能となり、入力信号端子[11
よりゝゝH″の信号が入力されると、トランジスタ14
)がON状態となる。この時、トランジスタ(13)の
ゲートには定電圧発生回路u[ilより、電源電位−(
2×しきめ値電圧)の電圧が供給されて釦シ、トランジ
スタ03)はトランジスタ(41の飽和電流値よりも低
い飽和電流値になって、電源端子からトランジスタ+4
1VC供給する電流を抑制する。このことにより、出力
端子がゝゝL“からゝゝHI/に立ち上がる時、瞬間的
に過大な電流が流れるのを抑制し、出力信号の立ち上が
りの勾配を緩くする。
Next, the operation will be explained. As explained in the conventional output circuit above, the output! 11L I! from 1i-INfflJ signal terminal 12) At the time of large input, the transistor 031151 can be turned on, and the input signal terminal [11
When a “H” signal is input, the transistor 14
) becomes ON state. At this time, the gate of the transistor (13) is supplied with a power supply potential -(
When a voltage of 2 x threshold voltage) is supplied to the button, transistor 03) has a saturation current value lower than the saturation current value of transistor (41), and transistor +4 is supplied from the power supply terminal.
Suppress the current supplied by 1VC. As a result, when the output terminal rises from "L" to "HI/," an excessive current is prevented from flowing momentarily, and the slope of the rise of the output signal is made gentle.

筐た、入力信号端子fi+よりlゝL //の信号が入
力する時も同様でトランジスタ(5)がON状態となり
この時はトランジスタ圓のゲートに、GND電位十(2
Xしきい値電圧)の電圧が定電圧発生量WIf+6)よ
り供給されて電流の抑制を行い、出力信号の立ち下がり
の勾配金繰くする。
Similarly, when a signal of 1L// is input from the input signal terminal fi+ of the housing, the transistor (5) is turned on, and at this time, the gate of the transistor circle is connected to the GND potential (2).
A voltage of X threshold voltage) is supplied from the constant voltage generation amount WIf+6) to suppress the current and adjust the falling slope of the output signal.

〔発明の効果〕〔Effect of the invention〕

以上のようにこの発明によれば、出力信号の反転時に過
大な電流が瞬間的に流れるのを抑制するので、出力ノイ
ズ4減らすことができ、出力特性音改善する効果が得ら
れる。
As described above, according to the present invention, it is possible to suppress the instantaneous flow of an excessive current when the output signal is inverted, so that the output noise can be reduced by 4, and the effect of improving the output characteristic sound can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の一実施例金示す出力回路の回路図、
第2図は第1図の入力信号と出力信号の波形図、第3図
は従来の出力回路の回路図第4図は第8図の各部の波形
図金側す。図に釦いて、+11は入力信号端子、(21
は出力別画信号端子、+31は出力信号端子、(4)は
′l H//駆駆動用型型トランジスタ+51Viゝ+
 L ///動用N型トトランジスタ+61 Lri電
源端子、 +71i G ’N D端子、(8)はトラ
ンジスタ14)音制御する回路、+91i)ランジスタ
5)音制御する回路、(!0)は反転回路、瞥は電流制
御用P型トランジスタ、0(1)は電流制御用N型トラ
ンジスタ、051はトランジスタt+a+’を制御する
定這圧発生1(−1IJ路、(161はトランジスタ1
41を制御する定電圧発生回路金石す。 なか、図中、同一符号は同一、又は相当部分を示す。
FIG. 1 is a circuit diagram of an output circuit showing an embodiment of the present invention.
2 is a waveform diagram of the input signal and output signal of FIG. 1, FIG. 3 is a circuit diagram of a conventional output circuit, and FIG. 4 is a waveform diagram of each part of FIG. 8. In the figure, +11 is the input signal terminal, (21
is the output separate picture signal terminal, +31 is the output signal terminal, (4) is the 'lH//drive type transistor +51Viゝ+
L ///Active N-type transistor +61 Lri power supply terminal, +71i G'N D terminal, (8) is transistor 14) Sound control circuit, +91i) Transistor 5) Sound control circuit, (!0) is inverting circuit , 0(1) is a P-type transistor for current control, 0(1) is an N-type transistor for current control, 051 is a constant pressure generation 1 (-1IJ path that controls transistor t+a+', (161 is transistor 1)
The constant voltage generation circuit that controls the In the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】[Claims] 半導体装置の出力ドライバートランジスタにおいて、電
源−出力間にN型トランジスタとP型トランジスタを使
用する時、このトランジスタと直列に電流制御用トラン
ジスタを設け電流を制御することを特徴とする出力回路
In an output driver transistor of a semiconductor device, when an N-type transistor and a P-type transistor are used between a power supply and an output, a current control transistor is provided in series with the transistor to control the current.
JP1167603A 1989-06-29 1989-06-29 Output circuit Pending JPH0332223A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1167603A JPH0332223A (en) 1989-06-29 1989-06-29 Output circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1167603A JPH0332223A (en) 1989-06-29 1989-06-29 Output circuit

Publications (1)

Publication Number Publication Date
JPH0332223A true JPH0332223A (en) 1991-02-12

Family

ID=15852836

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1167603A Pending JPH0332223A (en) 1989-06-29 1989-06-29 Output circuit

Country Status (1)

Country Link
JP (1) JPH0332223A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04310020A (en) * 1991-04-08 1992-11-02 Toshiba Corp D/a converter
JP2007538475A (en) * 2004-05-19 2007-12-27 インターナショナル レクティファイアー コーポレイション Gate driver output stage with bias circuit for high and wide operating voltage range
JP2014027401A (en) * 2012-07-25 2014-02-06 Lapis Semiconductor Co Ltd Output buffer and semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04310020A (en) * 1991-04-08 1992-11-02 Toshiba Corp D/a converter
JP2007538475A (en) * 2004-05-19 2007-12-27 インターナショナル レクティファイアー コーポレイション Gate driver output stage with bias circuit for high and wide operating voltage range
JP2014027401A (en) * 2012-07-25 2014-02-06 Lapis Semiconductor Co Ltd Output buffer and semiconductor device

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