JPH03296389A - Digital video signal monitor circuit - Google Patents

Abstract

PURPOSE:To monitor a video signal in an optional area of a pattern by providing a limit range accumulation arithmetic circuit accumulating only video signals of area set optionally so as to discriminate whether or not a current scanning position on the pattern is within the set area. CONSTITUTION:A timing signal is inputted from a timing signal input terminal 18 and a horizontal and a vertical clock signal are counted respectively by a horizontal position counter 13 and a vertical position counter 14. Position information of a video signal inputted at present to a video signal input terminal 15 is sent to a control circuit 12 by the counters. When the video signal in a monitor range 1 shown in the Figure is inputted, an affirmative signal is sent from the control circuit 12 and an accumulation circuit 11 accumulates video signals at that time. When the monitor range is revised into a monitor range 2, coordinate information has only to be inputted via a range setting terminal 17. Thus, a monitor signal of an optional range at an optional position is obtained.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a video signal monitor circuit, and in particular to a television,
The present invention relates to a digital video signal monitor circuit that obtains a monitor signal by accumulating signals in a certain area within a screen regarding digital video signals of a VTR, VTR camera, etc.

[Prior Art] A conventional video signal monitor circuit, as shown in FIG.
Integrating circuit 91, comparing circuit 92, counter control circuit 93,
It was composed of a counter 94.

A video signal for one screen inputted from an input terminal 95 is integrated by an integrating circuit 91 . The output of the integrating circuit 91 and the reference signal input to the reference signal input terminal 96 are connected to the comparator circuit 92.
are input and compared. The output terminal and control terminal 97 of comparison circuit 92 are connected to counter control circuit 93. In the 6-count mode, the counter control circuit 93 causes the counter 94 to perform a counting operation, a hold operation, or resets the counter 94 based on a control signal input to the control terminal 97.
If the output is smaller than the reference signal at the reference signal input terminal 96, a control signal for up-counting the counter 94 is output, and if it is larger, a control signal for down-counting the counter 94 is output. The count value of counter 94 is output from output terminal 98. After that, the integrating circuit 91
It is reset in preparation for the next video signal. Output terminal 98
The signal outputted from is used, for example, as an automatic control signal for a white balance circuit.

[Problems to be Solved by the Invention] The conventional video signal monitor circuit described above integrates the signal of the entire screen, so it is difficult to measure the light of only the center part or the background part (photometering of the upper part of the screen). It was impossible to monitor such a portion of the screen. As a result, accurate judgments may not be made when forming control signals for white balance, auto iris, etc.

Therefore, an object of the present invention is, firstly, to be able to monitor video signals in any area of the screen, and secondly, to monitor multiple monitors in different partial areas from the video signal of the same screen. The purpose is to be able to obtain signals.

[Means for Solving the Problems] The digital video signal monitor circuit of the present invention includes a limited range accumulation value calculation circuit that accumulates only the video signals of an arbitrarily set area. The limited range cumulative value calculation circuit, for example, determines whether the current scanning position on the screen is within a set area, and if so, adds the video signal to the cumulative value, and if not, adds the video signal to the cumulative value; In some cases, this can be achieved by not adding.

Another digital video signal monitor circuit of the present invention includes a first circuit that accumulates video signals of a constant number of continuous pixels for each horizontal signal, in order to obtain monitor signals of different areas from video signals of the same screen. and a second arithmetic circuit that accumulates a predetermined number of consecutive outputs of the first arithmetic circuit within a predetermined range for each horizontal signal.

[Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1(a) is a block diagram showing a first embodiment of the present invention. In the figure, 13.14 is based on the timing signal input from the timing signal input terminal 18,
A horizontal position counter and a vertical position counter 12 that output current position signals receive output signals from the horizontal position counter 13 and vertical position counter 14, and determine whether the current position is within the area set by the range setting terminal 17. A control circuit 11 determines whether or not the area is within the area and generates an affirmative signal if it is within the area; 11 is a video signal inputted from the video signal input terminal 15 every time the control circuit 12 issues an affirmative signal; This is an accumulation circuit that accumulates the accumulated value and outputs the accumulated value to the monitor output terminal 16.

FIG. 1(b) is a block diagram showing the configuration of the control circuit 12 of FIG. 1(a). In Figure 1(b), 12
1.122 are first and second coincidences for determining whether or not the position information input to the horizontal position input terminal 124 and the vertical position input terminal 125 is within the range set by the range setting terminal 17, respectively. The circuit 123 is an AND gate that outputs an affirmative signal to the M decoder circuit output terminal 126 when a match signal is input from both the first and second match circuits 121 and 122.

Next, the operation of the monitor circuit shown in FIG. 1 will be explained.

The area to be monitored is determined by the range setting terminal 17.
Monitor range 1 [(X+, Yl) to (X
2, Ya)]. A timing signal including a horizontal clock signal, a vertical clock signal, etc. is input from the timing signal input terminal 18, and the horizontal clock signal is input to the horizontal position counter 13.
Further, the vertical position counter counts the vertical clock signal, and these counters transmit the digit 1 information of the video signal currently input to the video signal input terminal 15 to the control circuit 12. Now, assuming that the video signal of monitor range 1 in FIG. 2 is being input, the control circuit 12
An affirmative signal is issued from , and the accumulating circuit 11 adds up the video signals at that time. When the scanning to the point (X2, Ya) is completed, the accumulation of the video signals within the monitor range 1 is completed. The cumulative value of the cumulative circuit 11 is sent to the microcomputer via the monitor output terminal 16, where it is used to form various control signals such as white balance control, auto iris, and auto focus.

The horizontal position counter 13 is reset within the horizontal blanking period, and the accumulation circuit 11 and the vertical position counter are reset within the vertical blanking period.

When changing the monitor range to, for example, monitor range 2 [(Xs, Ys) to (X4.Ya)] shown in FIG. 2B, this coordinate information may be input via the range setting terminal 17. That is, in this embodiment, by changing the setting information from this setting terminal, a monitor signal in an arbitrary range at an arbitrary position can be obtained.

FIG. 3 is a block diagram showing a second embodiment of the invention. This embodiment is an example in which a plurality of monitor circuits of the first embodiment are incorporated into the same device.

In this embodiment, the range setting terminal group 17A connects the control circuits 12a, 12b, and 12c to A, B, and B in FIG. 2, respectively.
Set the monitor range 1.2.3 shown in C. When the settings are made in this way, the accumulation circuits 11a, llb, llc
from monitor output terminals 16a, 16b, 1, respectively.
Monitor information of the areas shown in each monitor range in FIG. 2 can be obtained through 6c.

According to this embodiment, a plurality of different monitor ranges can be simultaneously monitored from the video signal of the same screen.

FIG. 4(a) is a block diagram showing a third embodiment of the present invention. In the same figure, 42a indicates a signal input from the video signal input terminal 45 and a range setting terminal group 47. A first variable delay circuit 42b delays the input signal by a number of horizontal clocks, and a second adjustment delay circuit delays the input signal by a set number of vertical clocks from the range setting terminal group 47, and 43a and 43b each delay a horizontal clock. a latch signal generation circuit that emits a latch pulse when the number of vertical clocks reaches a set number, 41a, 41
b are first and second arithmetic circuits each having the configuration shown in FIG. 4(b).

In FIG. 4(b), 412 is an arithmetic circuit input terminal 41
413 is a subtracter that subtracts the signal input to the delay signal input terminal 416 from the added value of the adder 412; 414 receives the output of the subtracter and holds the value until the latch pulse is input from the latch signal input terminal 417, and when the latch pulse is input, the value held at that time is input. This is a data latch.

Next, the operation of the circuit shown in FIG. 4 will be explained.

Now, if we obtain a signal within the area shown in monitor range 1 in Fig. 2, then X2-X+ +1=n, , Ya -Y
As l +1 = m, the first and second variable delay circuits 4
The range setting terminal group 47 sets n and m to 2a and 42b, respectively, and X2 and Ya to latch signal generation circuits 43a and 43b, respectively. When the video signal of the first horizontal line is input from the video signal input terminal 45, the signals of each pixel are sequentially added in the first arithmetic circuit 41a, but when the number of clocks reaches n, the video signal of n clocks ago is Subtracted from the cumulative value. From then on, the horizontal line 020
The sum of the video signals with a width of 77 minutes is sent from the first arithmetic circuit 41a [
The data is output from the data latch 4] in FIG. 4(b). When the number of clocks reaches X2, a latch pulse is generated from the latch signal generation circuit 43a, and the sum of the video signals (X1, 1) to (X2, 1) is latched in the data latch. During the horizontal blanking period, this value is taken into the second arithmetic circuit 41b, and the first arithmetic circuit 41a and the first variable delay circuit 4.2a are reset. Similarly, for the video signal of the second horizontal line, (XI, 2) ~
The sum of the video signals (X2.2) is latched, and this is the second
They are added in the arithmetic circuit. Similarly, the sum of video signals of width n is accumulated one after another in the second arithmetic circuit.
After the m horizontal signals have been added, the output values of the second variable delay circuit 42b are sequentially subtracted. When the input of the video signal of the second horizontal line is completed, the second
The sum of the video signals of monitor range 1 in FIG. 2 is held in the arithmetic circuit 41b. Here, a latch pulse is emitted from the latch signal generation circuit 43b and the second arithmetic circuit 41
b is latched with the previous sum held, and this sum is sent to the microcomputer as a monitor signal. In the next vertical blanking period, the second arithmetic circuit 41b and the second variable delay 42b are reset.

FIG. 5(a) is a block diagram showing a fourth embodiment of the present invention. In the figure, 5]a and 51b are first and second arithmetic circuits each having the configuration shown in FIG. 5(b);
52a and 52b are the first and second parts of FIG. 4<a), respectively.
The first and second variable delay circuits 255 having the same functions as the variable delay circuits 42a and 42b have video signal input terminals, 56 a monitor output terminal, 57 a group of range setting terminals, 5
8 is a timing signal input terminal.

In FIG. 5(b), 512 is an adder that adds the signal input to the arithmetic circuit input terminal 511 to the output signal output to the arithmetic output terminal 515, and 513 is the adder 51.
A subtracter 514 that subtracts the signal input to the delay signal input terminal 516 from the output of the subtracter 513 is a data hold circuit that holds the output of the subtracter 513 and is reset during the horizontal blanking period or the vertical blanking period.

Next, the operation of the circuit of this embodiment shown in FIG. 5 will be explained. Now, when the range to be monitored is monitor range 1 shown in D in FIG. 6, the first variable delay circuit 5
2a has a delay value n corresponding to the number of clocks included in the horizontal width of monitor range 1 (1≦n≦horizontal clock number of one screen); A delay value m (1≦m≦number of lines in one screen) is set for the number of lines included in the vertical height. In addition, the operation timing of the second variable delay circuit 52b and the second arithmetic circuit 51b (timing for accepting the output of the first arithmetic circuit 51a) is also set.
1a is a video signal input terminal 55 (arithmetic circuit input terminal 51
An adder 512 accumulates the digital video signal from 1), and a subtracter 513 subtracts the data n clocks ago, which is the output of the first variable delay circuit 52a, and stores it in a data hold circuit 514. In this way, the first arithmetic circuit 5
1a always outputs the sum of data with a width of 02077 minutes from the current scanning position on the screen. The second arithmetic circuit 51b is
The first arithmetic circuit 51 input to the arithmetic circuit input terminal 511
The output signal of a is added to the adder 51 according to the set timing.
2, subtracts the sum of 82072 lines in the horizontal direction before m lines, and stores the result in the data hold circuit 514. In this way, the second arithmetic circuit 51b accumulates the sum of 82,072 pieces of data in the horizontal direction, which is the output of the first arithmetic circuit 51a, and outputs the sum of m942 pieces of data in the vertical direction from the current position. As a result, the monitor range 1 in FIG. 6 moves vertically from top to bottom on the screen as shown by the arrow. The accumulated values obtained in this way are sequentially sent to the microcontroller,
Appropriate portions are used as monitor information.

In this embodiment, by advancing the operation timing of the second arithmetic circuit 51b by a certain amount of lock compared to the previous line, the monitor range 2 shown at E in FIG. 6 is moved diagonally downward as shown by the arrow in FIG. It can be moved.

According to this embodiment, multiple monitor information can be obtained from the same screen using one monitor circuit without providing multiple monitor circuits in parallel as in the case shown in the second embodiment (Fig. 3). be able to.

FIG. 7 is a block diagram showing a fifth embodiment of the present invention. In this figure, parts that are equivalent to those in FIG. 5 are given the same reference numerals, so redundant explanation will be omitted.

In FIG. 7, 54a and 54b are a horizontal position counter and a vertical position counter, respectively, which output a current position signal based on a timing signal input from a timing signal input terminal 58, and 53 is a monitor candidate area whose current position is This is a control circuit that determines whether or not it is within the monitor candidate area set by the setting terminal group 59, and outputs various timing signals when it is within the area.

Now, set the range shown in F in FIG. 8 as a monitor candidate area via the monitor candidate area setting terminal group 59,
Furthermore, by specifying the range shown in G in the figure as the monitor range, it is possible to obtain monitor information that moves vertically within the monitor candidate area.

[Effects of the Invention] As explained above in 1-1, the present invention is capable of obtaining a monitor signal of any area of any size on one screen. Information at a desired position on the screen can be monitored, and white balance, auto iris, auto focus, etc. can be controlled accurately.

[Brief explanation of the drawing]

1(a>, (b) are block diagrams showing a first embodiment of the present invention, FIG. 3 is a block diagram showing a second embodiment of the present invention, FIG. 4(a), (b> is a block diagram showing the third embodiment of the present invention, FIG. 2 is an explanatory diagram of the operation of the first to third embodiments, and FIGS. 5(a) and 5(b) are block diagrams showing the third embodiment of the present invention. FIG. 6 is a block diagram showing the fourth embodiment of the present invention, FIG. 6 is an explanatory diagram of the operation of the fourth embodiment, FIG. 7 is a block diagram showing the fifth embodiment of the present invention, and FIG. 9 is a block diagram of a conventional example. 11.11a to llc...accumulation circuit, 12.12
a to 12c... Control circuit, 121... First coincidence circuit, 122... Second coincidence circuit, 123
...And gate, 124...Horizontal position input terminal, 125...Vertical position input terminal, 126.
...Control circuit output terminal, 13...Horizontal position counter, 14...Vertical position counter, 15...
Video signal input terminal, 16...Monitor output terminal, 1
7... Range setting terminal 18... Timing signal input terminal, 41a, 51a... First arithmetic circuit, 41
b, 5 l b--Second arithmetic circuit, 42a, 52
a...First variable delay circuit, 42b, 52b.
...Second variable delay circuit, 43a, 43b...
Latch signal generation circuit, 53... control circuit, 54a
...Horizontal position counter, 54b...Vertical position counter, 45.55...Video signal input terminal, 46
．． 56...Monitor output terminal, 47.57...
Range setting terminal group, 48.58... Timing signal input terminal, 59... Monitor candidate area setting terminal group.

Claims (4)

[Claims] (1) A digital video signal monitor circuit equipped with a limited range cumulative value calculation circuit that receives a digital video signal and outputs a cumulative value only for the digital video signal in a predetermined area. (2) The limited range cumulative value calculation circuit includes a horizontal position counter that outputs the current horizontal position of the video screen, a vertical position counter that outputs the current vertical position of the video screen, and a count value of the horizontal position counter. and a control circuit that generates a coincidence signal when the count value of the vertical position counter is within a predetermined range, and a control circuit that accumulates digital video signals only when the coincidence signal is generated from the control circuit. 2. The digital video signal monitor circuit according to claim 1, further comprising an accumulation circuit. (3) The limited range cumulative value calculation circuit includes a first calculation circuit that accumulates digital video signals in a range set for each horizontal line, and an output of the first calculation circuit within the specified range. 2. The digital video signal monitor circuit according to claim 1, further comprising a second arithmetic circuit that performs accumulation for the included horizontal lines. (4) A first arithmetic circuit that receives a digital video signal and accumulates the video signal of a constant number of continuous pixels for each horizontal line, and an output of the first arithmetic circuit within a predetermined range for each horizontal line. A digital video signal monitor circuit comprising: a second arithmetic circuit for accumulating a predetermined number of continuous signals.