JPH03296257A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent the mixing of FM modulation noise into oscillation output by removing the vibration of the charge at a p-type silicon substrate, in the IC comprising an oscillating circuit, a frequency divider circuit, and an dividing ratio changeover signal interface circuit to interface with an external circuit. CONSTITUTION:The input stage circuit 54 of a dividing ratio changeover interface circuit 52 is constituted by providing an NPN transistor 58, and the collector is connected to the input terminal of an inner circuit 55, and is also connected to a high voltage power source line 61 through a resistance 60, and the base is connected to a bias voltage input terminal 62, and is grounded through an emitter resistance 63. Since the dividing ratio changeover signal Sn is supplied to the emitter of the NPN transistor 58, the dividing ration changeover signal Sn never affects the charge of a p-type silicon substrate 64 through an n<+> buried layer 68. That is, it never vibrates the charge of the p-type silicon substrate 64. Therefore, the values of the parasitic capacitance 88 of a voltage control oscillating circuit 50 and the parasitic capacitance 89 of the pad 57 for oscillation output do not change, and the mixing of FM modulation noise into the oscillation output of the voltage control oscillating circuit 50 can be avoided.

Description

[Detailed Description of the Invention] [Summary] An n-type epitaxial layer is formed on a p-type semiconductor substrate, and an oscillation circuit and an oscillation output of the oscillation circuit are separated using the n-type epitaxial layer as an element formation region. A frequency division ratio switching signal interface circuit is provided for interfacing between a frequency division circuit that rotates the frequency and an external circuit that is a source of a frequency division ratio switching signal supplied for switching the frequency division ratio of the frequency division circuit. With respect to the semiconductor integrated circuit device, for the purpose of preventing FM modulation noise from being included in the oscillation output of the oscillation circuit, the input stage circuit of the frequency division ratio switching signal interface circuit is configured using an NPN transistor, Its collector is connected to one power supply voltage source through a first resistor, its base is connected to a bias voltage input terminal, and its emitter is connected to a frequency division ratio switching signal input terminal through a second resistor. At the same time, it is connected to the other power supply voltage source having a lower potential than the one power supply voltage source via a third resistor, so that an output signal is obtained at its collector.

[Industrial Field of Application] The present invention relates to an IC that constitutes a part of a local oscillation circuit that constitutes a frequency conversion circuit of a receiving section of a wireless device, for example, among semiconductor integrated circuit devices (hereinafter referred to as IC).

[Prior Art] A receiving section of a wireless device is configured as shown in FIG. 10, for example.

In the figure, 1 is an antenna, 2 is a high frequency amplification circuit, 3 is a mixing circuit, 4 is a local oscillation circuit, 5 is an intermediate frequency amplification circuit, and 6 is an F
M detection circuit, 7 is a low frequency amplifier circuit, 8 is a speaker, and the local oscillation circuit 4 is constituted by a so-called PLL circuit. That is, the voltage controlled oscillation circuit 9, the frequency dividing circuit 10.11, and the frequency division ratio switching signal interface circuit 12.
, a phase comparison circuit 13 , a crystal oscillation circuit 14 , a frequency division circuit 15 , and a low-pass filter 16 . Note that the frequency division ratio of the frequency dividing circuit 10 is switched and controlled by a frequency division ratio switching signal Sn made of a low frequency signal supplied from the frequency dividing circuit 11 via the frequency division ratio switching signal interface circuit 12. The frequency division ratio switching signal interface circuit 12 is provided so that the frequency division circuit 10 or the ECL (pseudo-ECL) circuit may be used, and the frequency division circuit 11 may be formed from a CMO3 circuit or a TTL circuit.

Conventionally, as shown in FIG. 11, an IC has been proposed in which a voltage controlled oscillation circuit 9, a frequency dividing circuit 10, and a frequency dividing ratio switching signal interface circuit 12 are integrated into one chip.
17 is a pad for inputting a frequency division ratio switching signal, 18 is an input stage circuit of the frequency division ratio switching signal interface circuit 12, one is also an internal circuit, 20 is a pad for frequency division output, and 21 is a pad for oscillation output. It is. Note that the pad 17 is connected to the base of a PNP transistor 22 constituting the input stage circuit 18 and is grounded via a resistor 23. Further, the PNP transistor 22 has its emitter connected to an input terminal of one of the internal circuits and is connected to a high voltage V via a resistor 24. C1 is connected to a high voltage power supply line 25 to which, for example, 5 [V] is supplied, and its collector is grounded.

The conventional IC shown in FIG. 11 has an n-type epitaxial layer 2 on a p-type silicon substrate 26, as shown in FIG.
7 is formed, and this n-type epitaxial layer 27 is used as an element formation region.

However, in FIG. 12, regarding the transistors, the PNP transistor 22 forming the input stage circuit of the frequency division ratio switching signal interface circuit 12 and the voltage controlled oscillation circuit 9 are shown.
Only the NPN transistor 28 constituting the circuit is illustrated, and illustration of other transistors is omitted.

Note that two are the base electrode of the PNP transistor 22, and three are the base electrodes of the PNP transistor 22.
0 is an n+ buried layer, 31 is an n layer connecting the base electrode 29 and the n+ buried layer 30, 32 is an emitter electrode, 33 is an emitter region made of a p layer, 34 is a collector electrode, 35
is a collector region made of a p layer. Also, 36 is NP
A collector electrode of the N transistor 28, 37 an n+ buried layer, 38 an n layer connecting the collector electrode 36 and the n+ buried layer 37, 39 a base electrode, 40 a base region made of a p layer, 41 an emitter electrode, 42 is an emitter region made of an n layer. Further, 43 to 46 are element isolation regions made of p-layer layers, and 47 is an insulating layer made of a 5i02 film.

[Problems to be Solved by the Invention] In the conventional IC shown in FIG. 11 (FIG. 12),
When FM modulation noise mixes into the oscillation output obtained from the pad 21 and is outputted from the speaker 8 as low frequency noise via the intermediate frequency amplifier circuit 5, FM detection circuit 6, and low frequency amplifier circuit 7. There was a problem that there was.

As a result of experiments and research by the present inventor, this is because the frequency division ratio switching signal Sn is supplied to the n+ buried layer 3o via the pad 17, the base electrode 29, and the n+ layer 31. The charges existing in the region on the type epitaxial layer 27 side oscillate under the influence of the frequency division ratio switching signal Sn,
Among these, especially the lower part of the n+ buried layer 37 and the pad 21
The oscillation of charge in the p-type silicon substrate below the NPN
This is because the values of the parasitic capacitance 48 of the transistor 28 and the parasitic capacitance 49 of the pad 21 fluctuate, which affects the resonant circuit of the voltage controlled oscillation circuit 9 and mixes FM modulation noise into the oscillation output. It has been found.

Moreover, in this way, the oscillation output of the voltage controlled oscillation circuit 9 is F
The problem that M modulation noise is included is that an IC that does not include the voltage controlled oscillation circuit 9 but is provided with the frequency divider circuit 10 and the frequency division ratio switching signal interface circuit 12, and an IC that does not include the voltage controlled oscillation circuit 9 but have the voltage controlled oscillation port Fl This problem also occurred when used in connection with an IC equipped with @9. The reason for this is that the value of the parasitic capacitance of the pad for inputting the oscillation output supplied from the voltage controlled oscillation circuit 9 changes, or it affects the resonance circuit of the voltage controlled oscillation circuit 9, and this causes FM modulation noise in the oscillation output. This is thought to be due to contamination.

In view of this point, the present invention provides: ■ an n-type semiconductor substrate on a p-type semiconductor substrate;
A type epitaxial layer is formed, and this n-type epitaxial layer is used as an element formation region to provide an oscillation circuit, a frequency divider circuit that divides the oscillation output of this oscillation circuit, and a frequency division ratio of this frequency divider circuit. Regarding an IC equipped with a frequency division ratio switching signal interface circuit that interfaces with an external circuit that is the source of the frequency division ratio switching signal supplied to and ■ forming an n-type epitaxial layer on a p-type semiconductor substrate, and using this n-type epitaxial layer as an element formation region, the oscillation output supplied from an oscillation circuit configured in an external device is A frequency division ratio switching signal interface circuit is provided for interfacing a frequency division circuit that divides the frequency with an external circuit that is a source of a frequency division ratio switching signal that is supplied to switch the frequency division ratio of this frequency division circuit. The purpose of this invention is to prevent FM modulation noise from being included in the oscillation output of an oscillation circuit with respect to an IC.

[Means for Solving the Problems] FIG. 1 is a principle circuit diagram of an IC according to a first aspect of the present invention, and FIG. 2 is a sectional view of the same principle.

Here, as shown in FIG. 1, the IC according to the first invention includes an oscillation circuit, for example, a voltage controlled oscillation circuit 50, and a frequency dividing circuit 51 that divides the frequency of the oscillation output of the voltage controlled oscillation circuit 5o.
and a frequency division ratio switching signal interface circuit 52 that interfaces with an external circuit that is the source of the frequency division ratio switching signal Sn supplied to switch the frequency division ratio of the frequency dividing circuit 51. It is something. In FIG. 1, 53 is a pad for inputting a frequency division ratio switching signal, and 54 is a pad for inputting a frequency division ratio switching signal.
is an input stage circuit of the frequency division ratio switching signal interface circuit 52, 55 is also an internal circuit, 56 is a pad for frequency division output,
57 is a pad for oscillation output.

Further, in this first invention, the input stage circuit 54 of the frequency division ratio switching signal interface circuit 52 is configured with an NPN transistor 58, and the pad 53 for inputting the frequency division ratio switching signal has a resistor 59. It is connected to the emitter of this NPN transistor 58 via the NPN transistor 58. Also, this N
PN) The run transistor 58 connects its collector to the internal circuit 55.
A bias voltage input terminal 62 is connected to a high voltage power supply line 61 to which a high voltage VCC1, for example, 5 [V] is supplied via a resistor 60, and its base is connected to a bias voltage input terminal 62 to which a bias voltage VBB is supplied. , and its emitter is grounded via a resistor 63. Here, the bias voltage VBB is set to a value that prevents saturation of the NPN transistor 58 and produces an appropriate voltage effect on the resistor 60 when the voltage of the frequency division ratio switching signal Sn reaches its lowest value. , resistors 59, 60, 63 are frequency division ratio switching signals S
The NPN transistor 58 is set to a value that does not saturate or break down within the input voltage range of n.

Further, as shown in FIG. 2, the IC according to the first invention includes a p-type semiconductor substrate, for example, a p-type silicon substrate 64.
An n-type epitaxial layer 65 is formed thereon, and this n-type epitaxial layer 65 is used as an element formation region. However, in FIG. 2, regarding the transistors 1 to 1, the NPN transistor 58 that constitutes the input stage circuit 54 of the frequency division ratio switching signal interface circuit 52, and the NPN transistor 6 that constitutes the voltage controlled oscillation circuit 50. Only one transistor is shown in the figure, and illustration of other transistors is omitted.

In addition, in this FIG. 2, 67 is a collector electrode of the NPN transistor 58, 68 is an n+ buried layer, 69 is an n layer connecting the collector electrode 67 and the n+ buried layer 68,
70 is a base electrode, 71 is a base region made of a p layer, 7
2 is an emitter electrode, and 73 is an emitter region made of an n-layer. Further, 74 is a collector electrode of the NPN transistor 6, 75 is an n+ buried layer, 76 is an n layer connecting the collector electrode 74 and the n+ buried layer 75, 77 is a base electrode, 78 is a base region made of a p layer, 7 is an emitter electrode, and 80 is an emitter region made of an n-layer. Also, 8
1 to 84 are element isolation regions made of p-layer layers, and 85 is an insulating layer.

Further, FIG. 3 is a principle circuit diagram of an IC according to a second aspect of the present invention, and FIG. 4 is a sectional view of the same principle.

Here, as shown in FIG. 3, the IC according to the second invention includes an oscillation circuit configured on another chip 86, for example, a frequency division circuit 51 that divides the oscillation output of the voltage controlled oscillation circuit 50, A frequency division ratio switching signal interface circuit 5 that interfaces with an external circuit that is the source of the frequency division ratio switching signal Sn supplied to switch the frequency division ratio of the frequency dividing circuit 51.
2 and 2 into one chip, and for the rest,
The configuration is similar to the first invention. Therefore, in FIG. 4, parts corresponding to those in FIG. 2 are designated by the same reference numerals, and redundant explanation thereof will be omitted. Note that 87 is a pad for inputting the oscillation output supplied from the voltage controlled oscillation circuit 50.

[Operation] In the first invention, since the frequency division ratio switching signal Sn is supplied to the emitter of the NPN transistor 58, the frequency division ratio switching signal Sn is transferred to the charge of the p-type silicon substrate 64 via the n+ buried layer 68. It has no effect. That is, the charge on the p-type silicon substrate 64 is not oscillated. Therefore, the values of the parasitic capacitance 88 of the voltage controlled oscillation circuit 50 and the eight parasitic capacitances of the pad 57 for oscillation output do not change, and FM modulation noise is prevented from being mixed into the oscillation output of the voltage controlled oscillation circuit 50.

Also, in the second invention, the frequency division ratio switching signal Sn is N
Since it is supplied to the emitter of the PN transistor 58, n
+ The charge of the p-type silicon substrate 64 is not affected through the buried layer 68.

That is, the charge on the p-type silicon substrate 64 is not oscillated. Therefore, pad 8 for inputting the oscillation output
The value of the parasitic capacitance 90 of 7 does not change, and the voltage controlled oscillation circuit 5
Mixing of FM modulation noise into the zero oscillation output is avoided.

[Examples] Hereinafter, first to fifth embodiments of the present invention will be described with reference to FIGS. 5 to 9. In addition, these examples are as follows.
FIG. 11 (FIG. 12) Similar to the conventional example, a voltage controlled oscillation circuit, a frequency dividing circuit 10, a frequency dividing ratio switching signal interface circuit 12, and a frequency dividing circuit 10 constituting the local oscillation circuit 4 of the wireless device in the example shown in FIG. Is it a case where the present invention is applied to an IC formed by integrating into a single chip?
(FIG. 12) The difference from the conventional example is the configuration of the input stage circuit 18 of the frequency division ratio switching signal interface circuit 12.

1st male side (Fig. 5) Fig. 5 shows the main part of the first embodiment of the present invention.
In the embodiment, pad 17 is connected to NP via resistor 91.
It is connected to the emitter of N transistor 92. This NPN transistor 92 has its collector connected to the base of an NPN transistor 93 and to the high voltage power supply line 25 via a resistor 94, and its base connected to a bias voltage input terminal 95 to which a bias voltage BB is supplied. It is connected to the base of an NPN transistor 96, and its emitter is grounded via a resistor 97.

Further, the NPN transistor 96 has its collector in an NP state.
connected to the base of the N transistor 98 and the resistor 9
9 is connected to the high voltage power supply line 25, and its emitter is connected to the reference voltage (2) through a resistor 100. The reference voltage input terminal 101 is connected to a reference voltage input terminal 101, which is supplied to the reference voltage input terminal 101, and is grounded via a resistor 102.

Further, the NPN transistor 93 has its collector connected to the high voltage power supply line 25 via a resistor 103, and its emitter connected to the emitter of the NPN transistor 98 and to one end of a constant current source 104. The other end of the current source 104 is grounded. Also, NPN
The transistor 98 has its collector connected to an input terminal of one of the internal circuits and is also connected to the high voltage power supply line 25 via a resistor 105.

The rest of the structure is the same as that of the conventional example shown in FIG. 11 (FIG. 12).

In the first embodiment, the reference voltage VREP determines the input characteristic of the input stage circuit 18 and the threshold voltage Vt.
h) can be determined.

Second Male Side (FIG. 6) FIG. 6 is a circuit diagram showing a main part of a second embodiment of the present invention.

In this second embodiment, the base of an NPN transistor 92 is connected to the collector and base of an NPN transistor 96, and the bias voltage input terminal 95 provided in the first embodiment is omitted, thereby simplifying the circuit. and
The rest of the structure is the same as that of the first embodiment.

Third Embodiment (FIG. 7) FIG. 7 is a circuit diagram showing a main part of a third embodiment of the present invention.

In the third embodiment, the resistor 100 and reference voltage input terminal 101 connected to the emitter of the NPN transistor 96 in the first embodiment are omitted to simplify the circuit. , is configured similarly to the first embodiment.

Note that in this case, the emitter voltage of the NPN transistor 96 becomes the threshold voltage Vth.

Fourth Embodiment (FIG. 8) FIG. 8 is a circuit diagram showing a main part of a fourth embodiment of the present invention.

In the fourth embodiment, the base of an NPN transistor 92 is connected to the collector and base of an NPN transistor 96, and the bias voltage input terminal 95 provided in the first embodiment is omitted.
Resistor 1 connected to the emitter of N transistor 96
00 and the reference voltage input terminal 101 are omitted to simplify the circuit, and the other components are configured similarly to the first embodiment. In addition, in this case as well, NPN
The emitter voltage of transistor 96 becomes threshold voltage Vth.

Fifth Male Side (FIG. 9) FIG. 9 is a circuit diagram showing essential parts of a fifth embodiment of the present invention.

In this fifth embodiment, a resistor 1 is connected between the midpoint of connection between resistor 91 and resistor 97 and the emitter of NPN transistor 92.
06, and a resistor 107 is provided between the connection midpoint of the resistor 100 and the resistor 102 and the emitter of the NPN transistor 96, and the E of the NPN transistors 92 and 96 is
This embodiment is designed to improve the SD breakdown voltage (electrostatic breakdown voltage), and is otherwise configured in the same manner as the first embodiment.

[Effects of the Invention] According to the first aspect of the present invention, an n-type epitaxial layer is formed on a p-type semiconductor substrate, and this n-type epitaxial layer is used as an element formation region to form an oscillation circuit and this A frequency division ratio switching device that interfaces between a frequency division circuit that divides the oscillation output of the oscillation circuit and an external circuit that is the source of the frequency division ratio switching signal that is supplied to switch the frequency division ratio of this frequency division circuit. For ICs equipped with a signal interface circuit,
It is possible to prevent FM modulation noise from being included in the oscillation output of the oscillation circuit.

According to the second invention, an n-type epitaxial layer is formed on a p-type semiconductor substrate, and an oscillation device configured in an external device (another chip) is formed using this n-type epitaxial layer as an element formation region. A frequency divider that interfaces between a frequency divider circuit that divides the oscillation output supplied from the circuit and an external circuit that is the source of the frequency division ratio switching signal that is supplied to switch the frequency division ratio of this frequency divider circuit. For ICs equipped with a ratio switching signal interface circuit, FM is used for the oscillation output of the oscillation circuit.
Modulation noise can be prevented from being included.

[Brief Description of the Drawings] Figures 1 and 2 are a principle circuit diagram and a principle sectional view of an IC according to the first invention, respectively. Figures 3 and 4 are principle circuit diagrams of an IC according to the second invention, respectively. 5 is a circuit diagram showing the main parts of the first embodiment of the IC according to the present invention, FIG. 6 is a circuit diagram showing the main parts of the second embodiment of the IC according to the present invention, and FIG. is a circuit diagram showing the main part of the third embodiment of the IC according to the present invention, FIG. 8 is a circuit diagram showing the main part of the fourth embodiment of the IC according to the present invention, and FIG. FIG. 10 is a circuit diagram showing the main part of the embodiment. FIG. 10 is a circuit diagram showing the receiving section of the wireless device. FIG. 11 and FIG. FIG. 2 is a circuit diagram and a cross-sectional view showing essential parts of an example of a conventional IC that constitutes a conventional IC. (In FIGS. 1 to 4) 50... Voltage controlled oscillation circuit 51... Frequency dividing circuit 52... Frequency division ratio switching signal interface circuit 53.5
6.57.87... Pad 54... Input stage circuit 58.66... NPN transistor RO 4... P-type silicon substrate 65... N-type epitaxial layer 88.89.90... Parasitic capacity

Claims (1)

[Claims] 1. An n-type epitaxial layer (65) is formed on a p-type semiconductor substrate (64), and the n-type epitaxial layer (65) is formed on a p-type semiconductor substrate (64).
5) as an element formation region, an oscillation circuit (50), and a frequency division circuit (51) that divides the frequency of the oscillation output of the oscillation circuit (50).
and a frequency division ratio switching signal interface circuit (52) that interfaces with an external circuit that is the source of the frequency division ratio switching signal (Sn) supplied to switch the frequency division ratio of the frequency dividing circuit (51). In a semiconductor integrated circuit device comprising: an input stage circuit (54) of the frequency division ratio switching signal interface circuit (52), an NPN transistor (
58), the collector of which is connected to the first resistor (6
0) to one power supply voltage source (61), its base is connected to the bias voltage input terminal (62), and its emitter is connected to the division ratio switching signal input via the second resistor (59). Connected to the terminal (53) and the third resistor (63)
A semiconductor integrated circuit device, characterized in that the semiconductor integrated circuit device is connected to the other power source voltage source having a lower potential than the one power source voltage source (61) through the power source voltage source (61), and is configured to obtain an output signal at its collector. 2. Form an n-type epitaxial layer (65) on a p-type semiconductor substrate (64), and form an n-type epitaxial layer (65) on a p-type semiconductor substrate (64).
5) as an element formation area, a frequency dividing circuit (51) that divides the frequency of the oscillation output supplied from the oscillation circuit (50) configured in the external device (86), and a frequency dividing circuit (51) for dividing the frequency of the oscillation output supplied from the oscillation circuit (50) configured in the external device (86). A semiconductor integrated circuit device comprising a frequency division ratio switching signal interface circuit (52) for interfacing with an external circuit that is a source of a frequency division ratio switching signal (Sn) supplied for switching the ratio. The input stage circuit (54) of the frequency division ratio switching signal interface circuit (52) is connected to an NPN transistor (
58), the collector of which is connected to the first resistor (6
0) to one power supply voltage source (61), its base is connected to the bias voltage input terminal (62), and its emitter is connected to the division ratio switching signal input via the second resistor (59). Connected to the terminal (53) and the third resistor (63)
A semiconductor integrated circuit device, characterized in that the semiconductor integrated circuit device is connected to the other power source voltage source having a lower potential than the one power source voltage source (61) through the power source voltage source (61), and is configured to obtain an output signal at its collector.