JPH03295268A - Semiconductor device - Google Patents

Abstract

PURPOSE:To protect a semiconductor device against the effect of potential fluctuation by a method wherein a dedicated voltage wire is provided for a well separately from a voltage wire used for supplying a prescribed voltage to a transistor. CONSTITUTION:An N-type well region 22 is formed on the surface of a P-type silicon substrate 21 (or a P-type well region). For instance, a part of the flip- flops in a serial access memory is formed in the N-type well region 22. An N<+>-type diffusion region 23 is formed on the surface of the N-type well region 22. The N<+>-type diffusion region 23 serves as a region which comes into contact with a power wire 24 to supply an electric power to the well region 22, and the power wire 24 dedicated to a well is connected to the N<+>-type diffusion region 23. One or more of the N<+>-type diffusion region 23 are provided to the surface of the well region 22 depending on the size of a well. The well-dedicated power wire 24 is not used for supplying another power voltage Vcc. A normal power wire 25 is also provided in parallel with it separately from the well- dedicated power wire 24.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device having a structure in which a transistor is provided in a well.

[Summary of the invention]

In a semiconductor device having a transistor in an n-well or a p-well, the present invention prevents latch-up etc. by making the power supply line or ground line connected to the well independent of the one connected to the transistor. This is to prevent this from occurring.

[Conventional technology]

A memory device for storing image information such as a video memory is a DRA in which memory cells are arranged in a matrix.
A norial access memory (SAM) for data input/output is provided adjacent to the M core section. This norial access memory has, for example, a circuit configuration in which about 50 to 100 D flip-flops are arranged in a row in terms of layout, and each D flip-flop is connected to a common power supply line.

The D flip-flops that make up these serial access memories are usually formed inside a well formed on the surface of a semiconductor substrate, and a predetermined clock signal is applied to the clock input terminal of each D flip-flop. .

[Problem to be solved by the invention]

By the way, the area where this serial access memory is provided is a long and narrow area M along the periphery of the DRAM core, and therefore the power supply line is also formed into a long and thin pattern along the shape of the serial access memory.

However, if a power line is provided in a long and thin pattern that spans the length of several towers, the resistance value of the power line becomes high.

The plurality of D flip-flops constituting the serial access memory operate simultaneously in synchronization with the clock signal. Therefore, when the clock signal rises, as shown by the broken line in Figure 5, current is required in all the D flip-flops at the same time, and as a result, the potential of the power supply line temporarily drops, as shown by the solid line in the figure. become.

When such voltage fluctuations occur in the power supply line, problems such as latch-up occur.For example, as shown in FIG. A power supply voltage Vcc is applied to the well region 102 from a power supply line 104 via an n-type diffusion region 103.
is supplied, the voltage of the power line 104 fluctuates due to the operation of the D flip-flop 105 as described above. Then, the fluctuation becomes a fluctuation in the well potential,
If there is a diffusion region 106 connected to the bit line in the same well and the diffusion region 106 is at a high potential, the junction will be forward biased and current will flow into the well. As a result, latch-up and the like will occur.

SUMMARY OF THE INVENTION In view of the above-mentioned technical problems, the present invention aims to provide a semiconductor device that prevents the harmful effects of latch amplifiers and the like.

[Means for Solving the Problems] In order to achieve the above object, the semiconductor device of the present invention has n
A semiconductor device in which a transistor is provided in a well or p-well, which has a power line or a ground line for supplying a power supply voltage or ground voltage to the transistor, and a power line that is independent of the power line or ground line. Alternatively, a ground line is connected to the well.

[Effect]

Voltage lines such as power supply lines and ground lines for supplying a predetermined voltage to the transistors described above can have their potentials fluctuated during operation of the transistors. , the influence of the potential fluctuation becomes smaller.

〔Example〕

Preferred embodiments of the present invention will be described with reference to the drawings.

This embodiment is an example of a video memory that stores image information, and has a serial access memory composed of a plurality of D flip-flops, and has a voltage line dedicated to a well.

First, the circuit configuration will be briefly explained with reference to FIG.
The DRAM has a core section 1, and data is stored in each memory cell of the DRAM core section 1. From this DRAM core section 1, a plurality of bit lines BLw, BLX-3, B
LX,! , ”' are taken out, and each focus line B
L,, B L,,,, B L,, □2...,
The pMOS transistor 3 and the nMO transistor 5) are connected to a transfer gate consisting of a transistor 4. Each of these transfer gates has a common output line 5 at the other end of the bit line.
connected to.

The gates of the pMO3) transistor 3 and the nMO3 transistor 4 are controlled by Dfree, Buflo, and P2, respectively. A plurality of D flip-flops 2 are connected in series, and the Q terminal of the D flip-flop 2 is connected to the D terminal of the next stage D flip-flop. A common clock signal CK is input to each D flip-flop. Therefore, in the video memory of this embodiment having such a circuit configuration, the transfer gates are sequentially opened and closed to perform parallel-to-serial conversion at the timing of the rising edge of the clock signal CK. Sometimes, current is required for each D flip-flop to operate in unison, which can result in voltage fluctuations on voltage lines such as power lines and ground lines. However, in the video memory of this embodiment, the voltage line for supplying power to each well is D
Since it is separate from the voltage line supplied to the row of flip-flops 2, fluctuations in the well voltage are prevented.

FIG. 2 is a device cross-sectional view showing an example of an n-type well, in which an n-type well region 22 is formed on the surface of a p-type silicon substrate 21 (or a p-type well region). This n
For example, a portion of a plurality of flip-flops in a serial access memory is formed in the well region 22 of the mold. This n
On the surface of the type well region 22, an n type diffusion region 23 is formed.
is formed. This n-type diffusion region 23 is a region for contacting a power supply line 24 for supplying power to the well region 22, and is connected to a power supply line 24 dedicated to the well. One or more n-type diffusion regions 23 are formed on the surface of the well region 22 depending on the size of the well. The power supply line 24 dedicated to the well is, for example, made of a conductive layer such as a metal layer wired over the plurality of diffusion regions 23, and is not used for supplying other power supply voltages Vcc. A normal power supply line 25 is also formed in parallel and independently. This power supply line 25 has a power supply voltage Vcc
This is a voltage line for supplying voltage, and is connected to the p' type diffusion region 26 of the MOS transistor constituting the D flip-flop.

The power line 24 for supplying power to the well region 22 in this way
By making the power supply line 25 for feeding power to the MOS transistor formed in the well region 22 a separate and independent voltage line, even if the potential of the power supply line 25 fluctuates greatly due to a clock signal etc. 24 will not be affected by this. Therefore, since the potential of the well region 22 is stabilized, latch-up and the like can be prevented.

FIG. 3 is a cross-sectional view of an example device having a p-type well region. In this example, an n-type silicon substrate 31 (or n
A p-type well region 32 is formed in the p-type well region (type well region),
A p type diffusion region 3 is formed on the surface of the p type well region 32.
3 is formed. In the well region 32, for example, some elements of a D flip-flop constituting a serial access memory are formed, and in the P' type diffusion region 33, a ground line 34 is formed.
For connection, one or more are formed on the surface of the substrate as necessary. The ground line 34 is a dedicated line particularly for supplying power to the well region 32, and supplies the ground voltage GND from an external terminal to the well region 32. A normal ground line 35 is formed separately from this ground line 34. This ground line 35 is a voltage line for supplying the ground voltage GND, and is a MOS that constitutes the
It is connected to the n-type diffusion region 36 of the transistor.

The ground line 34 for supplying power to the well region 32 in this way
By making the ground line 35 for feeding power to the MOS transistor formed in the well region 32 an independent voltage line, even if the potential of the ground line 35 fluctuates greatly,
Ground wire 34 has a stable ground potential. Therefore, the potential of the well region 32 is stabilized, and latch-up and the like are prevented.

FIG. 4 is a schematic plan view of the main part of the video memory of this embodiment, in which a long rectangular pattern is formed on the surface of a p-type silicon substrate 41 to form an n-type well region of the opposite conductivity type to the silicon substrate 41. 42 is formed.

A p-channel MOS transistor 43 is formed in this well region 42, and a voltage line 45 for supplying a voltage Vcc to the source of this p-type MOS transistor 43 is formed. This power supply line 45 has a pattern whose longitudinal direction is the X direction in the figure, following the shape of the elongated serial access memory. And this power line 4
Na wires 44 dedicated to the well are provided in a pattern parallel to 5.

This well-dedicated power supply line 44 is connected to the well region 42 through contact holes 46 provided at a plurality of locations on the surface of the well region 42 . As shown in FIG. 4, in the video memory of this embodiment, the power supply line 44 dedicated to the well is formed separately and independently from the original power supply 145, so that the potential of the power supply line 45 increases as the element is driven. Even if the voltage varies, the potential of the well-dedicated power supply line 44 remains stable. Therefore, rough lumps and the like are effectively prevented. Furthermore, by supplying power at multiple locations in this manner, the well potential can be further stabilized.

〔Effect of the invention〕

In the semiconductor device of the present invention, the voltage of the well is supplied by a power supply line and a grounding line that are independent of the normal power supply line and grounding line connected to the transistor, so even if the voltage of the normal power supply line and grounding line fluctuates, Even in such a case, the voltage of the well can be stabilized and, therefore, latch-up and the like can be prevented from occurring.

2 is a schematic sectional view of the main part of one example, FIG. 3 is a schematic sectional view of another main part of the above-mentioned example, and FIG. 4 is a schematic plan view of the main part of the above-mentioned example. , FIG. 5 is a waveform diagram for explaining problems of a conventional video memory, and FIG. 6 is a schematic cross-sectional view of an example of a conventional semiconductor device.

1...DRAM core section 2...D flip-flop 3...PMO3) transistor 4...nMO3) transistor 21...p-type silicon substrate 22...n-type well region 24.25, 44.45...Power line 31...n-type silicon substrate 32...p-type well region 34.35...Grounding wire

[Brief explanation of drawings]

Claims (2)

[Claims] (1) A semiconductor device having a transistor in an n-well, characterized in that a power supply line independent of a power supply line for supplying power supply voltage to the transistor is connected to the n-well. (2) A semiconductor device having a transistor in a p-well, characterized in that a ground line independent of a ground line for supplying a ground voltage to the transistor is connected to the p-well.