JPH03294949A - High speed communication bus window controller - Google Patents

Abstract

PURPOSE:To shorten the processing time until a communication by mapping a specific area of a second memory map to a specific area of a first memory map, executing directly read and write to the mapped area and delivering an address pointer for showing the head of data. CONSTITUTION:The controller consists of a main CPU (central processor equipment) board 1B having a memory map M1 being a first memory map, and a communication board 2B having a memory map M2 being a second memory map. In such a state, a bus window circuit 17 executes mapping of a buffer area 16 of the memory map M2 to a communication data area 13 being a specific area of the memory map M1, and the main CPU board 1B executes directly read and write to the mapped buffer area 16 and delivers an address pointer for showing the head of data. In such a way, the execution transmission efficiency of the data quantity sent out actually to a transmission line can be improved, and the processing time until a communication can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high-speed communication bus window control device that utilizes a network to which processing devices are connected.

[Prior Art] Currently, processing devices (nodes) such as computers, image terminals, word processors, workstations, print servers, disk servers, etc., connected via communication paths such as local area networks (LANs) are organically connected. A system is being built to do so.

Further, standardization of each layer is progressing in LAN, and the standardization concept for file transfer, job transfer operations, etc. is also becoming solidified.

A common layered model is the International Organization for Standardization's (ISO) open system interconnection or open system interconnection, as shown in Table 1.
A reference model called O8I (hereinafter referred to as O8I reference model) is known.

This O8I reference model consists of seven layers ranging from communication line control to business-dependent communication functions, in order from the upper layers: application layer (level 7), presentation layer (level 6), session layer (level 5), Transport layer (level 4), network layer (level 3)
), link layer (level 3), physical or physical layer (
It is layered into each protocol of level 1).

FIG. 14 shows a communication procedure between a transmitting station and a receiving station using such a conventional layered protocol.

At the transmitting station, data 59 to be transmitted is first created using the application layer and presentation layer protocols.

Thereafter, a session level header 60a is added to the data 59 by the session layer protocol to create session layer data 60, and a transport level header 61a is added to the data 60 by the transport layer protocol to transport the data. Layer data 61 is created.

Furthermore, a network level header 62a is added to the data 61 by the network layer protocol to create network layer data 62.

Finally, a data link level header 63a is added to the data 62 according to the data link layer protocol to create data link layer data 63.

This data 63 is transmitted to the receiving station via an interface device and transmission media defined in the physical layer.

At the receiving station, the data link level header 63a1 added at the transmitting station and the network level header 6
2a1 transport level header 61a1 session level header 60a are sequentially removed at each layer, and data 59 is reproduced according to the protocols of the application layer and presentation layer.

Further, each header 60a to 63a is used as control information at the receiving station. Note that the headers 6Qa to 63a enable connection with many network systems and provide future interoperability.

In this case, each station is configured so that a plurality of modular protocol software are linked, and data is actually copied and transferred between each layer.

[Problems to be Solved by the Invention] However, in the above-mentioned conventional method, the same data is copied at each layer, which increases the data storage area and makes the copying time longer than the protocol processing time, reducing the execution speed. There is a problem in that the value decreases. Furthermore, the number of headers increases as the header progresses from upper layers to lower layers, compressing the original data to be transferred within the packet.

Also, when it comes to protocols, if standard alternatives for each layer are completely covered, in order to implement all the protocols of multiple classes, software is not created for each class, and the common parts use the same software. As the number of classes increases, class selection processing flows occur more frequently, causing overhead.

Therefore, in the above conventional method, the header 60a of each layer
.about.63a is large, the actual transmission efficiency of the amount of data actually sent to the transmission path decreases, and since there are many layers, there is a problem that the processing time until communication is long.

In view of the above-mentioned conventional problems, an object of the present invention is to provide a high-speed communication bus that can improve the actual transmission efficiency of the amount of data actually sent to the transmission path and shorten the processing time until communication. The purpose of the present invention is to provide a window control device.

[Means for Solving the Problems] According to the present invention, the object is to provide a high-speed communication bus window control device for creating protocols for each layer of a layered network architecture, which comprises a plurality of areas. a first memory map which is configured to sequentially write each specific address from the first address group into each area; and a first memory map which is made up of a plurality of areas and which can sequentially write each specific address from the second address group to each area. and a bus window circuit that maps a specific area of the second memory map to a specific area of the first memory map and transfers an address pointer indicating the beginning of data. This is achieved by a high-speed communication bus window controller.

[Operation] The first memory map sequentially writes each specific address from the first address group to each area of the first memory map, and the second memory map sequentially writes each specific address from the second address group to each area of the second memory map. , the bus window circuit maps a specific area of the second memory map to a specific area of the first memory map, directly reads and writes to the mapped area, and passes an address pointer indicating the beginning of data.

[Example code] Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is an explanatory diagram showing the concept of a high-speed communication bus window control device in an embodiment of the present invention, in which a main CPU having a memory map M1 as a first memory map
(Central Processing Unit) Board IB.

and a communication board 2B having a memory map M2 as a second memory map.

First, the memory map M1 of the main CPU board IB is
It consists of an operating system area 11, an application area 12 of the O8I reference model, and a communication data area 13 (hereinafter, the areas will be referred to as areas). In each of the above areas, the operating system area 11 and application area 12 are sequentially written from address 0000 in the first address group, and the communication data area 13 is written from address A to address A+L in the first address group. written.

Next, the memory map M2 of the communication board 2B is composed of a control software area 14, a header information area 15, and a buffer area 16 for each packet data.

In each of the above areas, control software area 1
4 and header information area 15 are sequentially written from address 0000 in the second address group, and buffer area 16 is written sequentially from address B to B+L in the second address group.
The data is written to B+4L via B+2L, B+3L, and B+4L.

Here, the communication data area 13 of the memory map M1 of the main CPU board IB is connected to the bus window circuit 17 (second
(see figure) transparently shows the buffer area 16 as a specific area of the memory map M2 of the communication board 2B.

That is, the bus window circuit 17 maps the buffer area 16 of the memory map M2 to the communication data area 13 as a specific area of the memory map M1, and
Board IB directly reads and writes to the mapped buffer area 16 and passes an address pointer indicating the beginning of data.

The main CPU (not shown) of the main CPU board IB can refer to the packet data in the memory map M2 by simply setting the packet data pointer in the bus window circuit 17.

Next, FIG. 2 shows the configuration of the communication board 2B in FIG. 1.

The communication board 2B controls the entire communication board 2B.
A RAM/R having a read-only memory (hereinafter referred to as ROM) for storing programs, etc. of P U18 and CPU U18, and a random access memory (hereinafter referred to as RAM) including the above areas 14, 15 and 16.
OMl9, communication LS that communicates via network
Equipped with I20.

Furthermore, the communication board 2B has a CPU 18 and a main CPU.
Bus window circuit 17 that performs address control between the address bus/control bus 21 of the host bus of board IB
, a control circuit 23 that performs data control between the CPU 18 and the data bus 22 of the host bus of the main CPU board IB;
Address bus/control bus 24 and data bus 2
It is equipped with 5.

Next, the configuration of the bus window circuit 17 in FIG. 2 is shown in FIG. 3.

The bus window circuit 17 is connected to the host bus address bus/
Control on the control bus 21 (registers 26 to 29 that store addresses by K numbers WO to W3, respectively, and a register control circuit 34 that controls the registers 26 to 29 and buffers 30 to 33. The bar above each symbol indicates that these control signals are negative logic (the same applies to each control signal hereinafter).

The buffers 30 to 33 each have a register control circuit 34.
The address is outputted to the data bus 25 by control signals 5ELO- and 5EL3 from the data bus 25.

In the example shown in FIG. 3, 512 kilobytes (KB) (
address r80000HJ~IF FF FFHJ)
A memory window of 128 KB is provided in the memory area of , and an arbitrary buffer address within the communication board 2B is indicated through this memory window.

The main CPU of the main CPU board IB writes the buffer start address to registers 26 to 29 assigned to the input/output (hereinafter referred to as Ilo) map, and an area of 512 KB to 1 megabyte (MB) is accessed. At times, the latch data of the registers 26 to 29 is output as an address to the address bus/control bus 24 of the communication board 2B. Note that the register control circuit 34 is provided with a bus window inhibition register for when the high speed communication bus window control device is not used.

The conditions under which each control signal in the bus window circuit 17 becomes active will be explained below.

The control signal WO-W3 has an I10 write access from the address bus/control bus 21 of the host bus,
They become active when addresses correspond to registers 26-29, respectively.

Control signal 5ELO becomes active when there is an I10 read access from the host bus and addresses correspond to registers 26-29, respectively. Then, data is selected from the corresponding register and output to the data bus 25 in conjunction with the control signal 5ELL (this allows the address written in the register to be read). Further, when 512 KB or more is accessed by normal memory access, the addresses in the registers 26 to 29 are output to the address bus/control bus 24 of the communication board 2B in conjunction with the control signal 5EL2.

Control signal 5ELI becomes active when there is a ■/○ read request to any address of registers 26 to 29 by I10 access from the host bus.

The control signal 5EL2 is 512KB to IM from the host bus.
It becomes active when there is a memory access of B and the register in the register control circuit 34 is not in the bus window inhibited state.

The control signal 5EL3 becomes active when the register in the register control circuit 34 is not in the bus window inhibited state and there is a memory access of 512 KB to IMB from the host bus.

Next, FIG. 4 shows the exchange of data between layers by the high-speed communication bus window control device in this embodiment.

In FIG. 4, where n is a positive integer, data 41 of the n-th layer is added with a header 42 of the (n-1)th layer and (n
-1) The data is passed to the layer 43, and a header 44 of the (n-2)th layer is added to the passed data (
n-2) is delivered to the layer 45.

5(a) shows the physical structure of the high-speed communication bus window control method of FIG. 4, and FIG. 5(b) shows the physical structure of the high-speed communication bus window control method of FIG.
A management disk as a table means included in the physical structure of a) and having a pointer 46 for the next upper layer, a data storage pointer 47 for each layer, and an area 48 as an area for storing data (header) length. Ributa table DT
shows.

Next, the physical structure first includes nth layer data 49 of length DLn written from address An. Hereinafter, in order from the upper layer, the header 50 of the (n-1)th layer of length DLn-1 written from address A n-1, the header 50 of the (n-1)th layer of length DL n-2 written from address A n-2, It is composed of a header 51 and the like of the n-2) layer.

Furthermore, the physical structure includes a pointer DT n+1 of the next (n+1) layer written from the address DTn, a data storage pointer An of the n-th layer, and a data length DLn of the n-th layer, and is sequentially written from the upper layer. , address DTn-1
The pointer DTn of the next nth layer written from DTn, the pointer (
n-1) layer data storage pointer An-1, data length D
Ln-1, pointer DTn-1 of the next (n-1) layer written from address DTn-2, data storage pointer An-2 of the (n-2) layer, data length DL n-2
It is equipped with a management disc libter table DT configured by the following.

FIG. 6 shows the configuration of each layer from the data link layer to the application layer.

In the data link layer header 52 shown in FIG. 6(a), a pointer NP to the next network layer header 53 is specified.
(New Po1nter), the data storage pointer DP of the data link layer header 52, and the data length DL are created. In the network layer header 53 shown in FIG. 6(b), a pointer NP to the next transport layer header 54, a data storage pointer DP of the network layer header 53, and a data length DL are created.

The transport layer header 54 shown in FIG. 6(C) contains a pointer NP to the next session layer header 55 and a data storage pointer D of the transport layer header 54.
P and data length DL are created. The session layer header 55 shown in FIG. 6(d) includes a pointer NP to the next presentation layer header 56, a data storage pointer DP of the session layer header 55, and a data length D.
L is created.

In the presentation layer header 56 shown in FIG. 6(e), a pointer NP to the next application layer data 57, a data storage pointer DP of the presentation layer header 56, and a data length DL are created. In addition, the application layer data 5 shown in FIG. 6(f)
7, the last pointer FFFFH of the data storage area, data storage pointers DPI to DP3 of the application layer data 57, and data lengths DL1 to DL3 are created for each packet.

FIG. 7 shows a pointer in the presentation layer header 56 shown in FIG. 6(e) to the application layer data 57 shown in FIG. 6(f), which is managed by the data pointer of each packet or the data pointer management table 58. ing.

Therefore, according to the embodiments of this publication, an actual packet is created by simply rewriting the pointer NP of the upper layer for each layer, and the connection state and actual state of the data and header of each layer are determined by the management disk list table. Can be managed individually.

FIG. 8(a) and FIG. 8(b) show the creation process of the management disc libter table DT at the time of transmission. Figure 8 (
In a), first, the start pointer of the data storage area is obtained from the application (step S1), the data storage pointer DP is obtained for each packet and the management disc libter table DT is created (step S2), and the data storage pointer DP is used to create the data storage pointer table DT. A management table 58 is created (step S3).

The subsequent processing of each layer (step S4) differs depending on the protocol, but as shown in FIG. 8(b), if the header and processing are basically the same, no header is intentionally created. Simply write the pointer NP of the next upper layer of the data storage pointer DP in the management disk libter table DT to proceed to the next lower layer (steps S41, S41.
545).

When transmitting large-capacity divided packets, the above-described processing is performed to divide only the application layer data.

On the other hand, if the header is not the same or the process is not the same, the protocol processing and header creation processing are performed (step 543), and the header information is stored in the management disk printer table D.
Enter T (step 544) and proceed to the next lower layer (step 545).

When the processing of each layer (step S4) is completed, the fifth
Returning to figure (a), the preparation of the packet for transmission is completed,
Since all data is transmitted (steps 85 to S7), processing can be performed faster than conventional processing for each layer.

FIG. 9 shows the procedure for transmitting the above-mentioned transmission packet to the transmission medium. When a transmission request is generated from the communication LSI or hardware, the packet transmission is performed by chaining the areas of each layer of the management disk printer table DT (step S
8), the next packet is data pointer management table 5
8, step 511), and only rewrites the pointer NP in the upper layer of the management disclibrator table DT (step 512).

FIG. 10(a) and FIG. 10(b) show the process of creating a discriminator table at the time of reception.

As shown in FIG. 10(a), as in the case of transmission, first the start pointer of the data storage area is acquired from the application (step 513), the data pointer management table 58 is prepared (step 514), and then the packet is When received (step 515), the process moves to each layer (step S16, step 8 in FIG. 10(b)).
161-5165).

The processing of each layer is basically the same header and processing as in the case of reception, so if the processing is the same, no header is intentionally created.
Simply pointer NP to the next layer of data storage pointer DP
Proceed to the next upper layer by simply entering the
5).

If the header is not the same or the process is not the same, the protocol processing and header creation are performed (step 5163), the header information is entered in the management disk printer table DT (step 5164), and the next upper layer is Proceed (step 5165).

When the processing of each layer (step 816) is completed, the process returns to FIG.
).

FIG. 11 shows a procedure for receiving a packet from a transmission medium. When a reception interrupt occurs from the communication LSI or hardware, the header section is cut out from the packet data and stored in the header storage area of each layer (step 519).
Store the data part in the data storage area and create a management disc libter table DT (step 520), check for the occurrence of a communication error (step 521), and if no communication error has occurred, select the data pointer management table DT.
8 (step 522). If a communication error occurs, error processing is performed (step 523) and the process returns.

According to this embodiment, it is possible to reduce unnecessary data copying between layers and perform communication processing at high speed, and the network protocol up to a predetermined layer shown in FIG. 12 is processed by a separate processor. The intelligent board system and the communication LSI shown in FIG. 13 support up to the data link layer, and processing can be performed even in a non-intelligent board system in which the main CPU processes the upper layer.

In the intelligent board system shown in Figure 12,
The application layer, presentation layer, and session layer among the upper protocol layers are divided into parts of the intelligent board system, including Simple Main Transfer Protocol (SMTP), File Transfer Protocol (FTP), and ChillNet. The network layer and data link layer are Transmission Control Protocol (TCP), Internet Protocol (IP), User Datagram Protocol (
UDP), Address Resolution Protocol (ARP
) and the Internet Control Message Protocol (ICMP). In addition, in the non-intelligent board system shown in Fig. 13, each layer from the application layer to the network layer in the upper protocol layer is the host/network layer of the non-intelligent board system.
The support area is divided, and the data link layer is divided by the LAN board of the non-intelligent board system.

[Effects of the Invention] A high-speed communication bus window control device that creates protocols for each layer of a layered network architecture, which is composed of a plurality of areas and assigns each specific address from the first address group to each area. a first memory map in which data can be sequentially written; a second memory map that is composed of a plurality of areas and in which specific addresses from a second address group can be sequentially written in each area;
Since it is equipped with a bus window circuit that maps a specific area of the memory map to a specific area of the first memory map and transfers an address pointer indicating the beginning of data, the effective transmission efficiency of the amount of data sent to the transmission path is reduced. can be improved, and the processing time until communication can be shortened.

Table 1

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of a memory map of a main CPU board and a memory map of a communication board in a high-speed communication bus window control method according to an embodiment of the present invention, and FIG. 2 is a block diagram showing the communication board of FIG. 1. Figure 3 is
2 is a block diagram showing the bus window circuit, FIG. 4 is an explanatory diagram showing data exchange between layers in the high speed communication bus window control device of this embodiment, and FIG. FIG. 5(b) is an explanatory diagram showing the actual physical structure of the high-speed communication bus window control device of FIG. 5(a).
) is an explanatory diagram showing the management disc libta table included in the physical structure of An explanatory diagram showing a pointer to the next application layer header in the header; FIGS. 8 and 9 are flowcharts showing operations at the time of transmission; FIGS. Figures 12 and 13
The figures are explanatory diagrams showing hardware to which the high-speed communication bus window control device of the present invention is applied, and FIG.
It is an explanatory diagram showing operation of a conventional transmitting station and a receiving station. 1B...Main CPU board, 2B...Communication board, ML M2...Memory map, 11...Operating system area, Engineering 2...Application area, 13...Communication data area, 14... Control software area, 15...Header information area, 1
6... Buffer area, 17... Bus wind circuit. Patent attorney Funayama to Daikei (b) Figure 10 408- Figure 9 Figure 11

Claims (1)

[Claims] A high-speed communication bus window control device that creates protocols for each layer of a layered network architecture, and is composed of multiple areas and can sequentially write each specific address from the first address group to each area. a first memory map; a second memory map that is composed of a plurality of areas and can sequentially write each specific address from the second address group into each area;
A high-speed communication bus window control device comprising: a bus window circuit that maps a specific area of a memory map to a specific area of the first memory map and delivers an address pointer indicating the beginning of data.