JPH03292697A - Non-volatile semiconductor storage device - Google Patents

Abstract

PURPOSE:To properly erase data in a short time by providing an erase pulse generating means which generates an erase pulse to erase stored data of a non-volatile semiconductor storage means and a pulse waveform setting means which arbitrarily sets the waveform of the erase pulse. CONSTITUTION:An erase pulse generator 19 is provided with an erase time setting circuit 50 which outputs an erase time set pulse Terase having the same pulse width as the erase pulse, a high voltage switch circuit 53 to which a high voltage Vp from the external is given and which outputs a high voltage erase pulse Vp having the erase pulse width set by the erase time setting circuit 50, and a voltage trimming circuit 55 to which the high voltage erase pulse Vp is given and which outputs an erase pulse intVpp set to a voltage most sutable for chip erasing. The waveform of the erase pulse like the voltage value or the pulse width is set from the outside. Thus, data is properly erased in a short time.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a nonvolatile semiconductor memory device, and in particular to a method for erasing data in a bulk erase type electrically erasable nonvolatile semiconductor memory device. be.

[Prior art] FIG. 9 shows a 15SCC (International Single
5olid-8tate C1rcuits C
1 is a block diagram of a nonvolatile semiconductor memory device described in Digest of Technical Papers (1990) pp. 60-61. Referring to FIG. 9, a nonvolatile semiconductor memory device includes a memory array 1 in which a plurality of nonvolatile memory cells are arranged in a plurality of rows and a plurality of columns, and a memory array provided from the outside. an address buffer 6 for buffering address signals AO to AK of 1; a row decoder 4 connected to the address buffer 6 for decoding the address signal to select one of the rows; a Y gate 2 connected to the column decoder 5 and the memory array l for selecting one of the bit lines of the memory array 1 according to the decoded and selected column; A source line switch 3 connected to the array 1 for switching the voltage applied to the source line of the memory array 1, a write circuit 7 connected to the memory array 1 via the Y gate 2, and a write circuit 7 connected to the memory array 1 via the Y gate 2. a sense amplifier 8 connected to the memory array 1; a human output buffer 9 connected to the write circuit 7 and the sense amplifier 8 for buffering external input/output signals; , PGM, and is connected to a mode control circuit 10 for controlling the operation mode of this device, a mode control circuit 10, an address buffer 76, a row decoder 4, a source line switch 3, a sense amplifier 8, and a memory array 1. and an erase control circuit 11 for controlling the operation of the device when erasing the stored contents of the device.

The address buffer 6 receives an address signal AO-A from the outside.
k is given. The input/output buffer 9 is connected to the input/output signal line 11
0 O to I107 exchange input/output signals with the outside.

FIG. 10 is a block diagram of memory array 1 and its peripheral circuits. Referring to FIG. 10, a memory array 1 is connected to a row decoder 4, connected to a plurality of word lines WLI to WL3 arranged in parallel to each other, and connected to a Y gate 2, which intersects with the word lines WLI to WL3. A plurality of bit lines BLI to BL3 arranged parallel to each other in the direction, memory cells such as memory cells MCI provided at each intersection of each word line and each bit line, and each memory cell and source line switch 3. Source line SL1~ for connecting with
Includes SL3.28.

In FIG. 10, three word lines and three bit lines are drawn. However, this is just for convenience of explanation, and in reality, the number of these is larger.

The Y gate 2 is connected to the I10 line 27 to which the write circuit 7 and sense amplifier 8 are connected, and each bit line BL1 to BL3 and I
10 line 27 and transistors 26a to 26c for bit line selection. Each transistor 2
The gates 6a to 26c are respectively connected to the column decoder 5.
are connected to outputs Y1 to Y3 of.

FIG. 11 is a schematic cross-sectional structural diagram of the memory cell MCI of FIG. 10. Referring to FIG. 11, memory cell MCI
is provided on the semiconductor substrate 24. memory cell MC
I is formed on the main surface of the semiconductor substrate 24 between the source region 23 and the drain region 22, which are impurity regions formed at a predetermined interval, and between the source region 23 and the drain region 22. In addition, there is a thin oxide film with a film thickness of about 100A, a floating gate 21 for information storage formed on this thin oxide film, an oxide film formed on the floating gate 21, and a further layer on the oxide film. and a control gate 20 provided therein. Source region 23 is connected to source line SL1. drain region 2
2 is connected to bit line BL1. Control gate 20 is connected to word line WL1. Floating gate 21 is electrically insulated from others.

FIG. 12 is a more detailed block diagram of the erase control circuit 11. Referring to FIG. 12, erase control circuit 11 includes command signal latch 12 connected to mode control circuit 10 and for latching a command signal given from mode control circuit 10, mode control circuit 10 and command signal latch 12, and mode control circuit 10 and command signal latch 12. 12, a sequence control circuit 13 for controlling the source line switch 3, row decoder 4, address buffer 76, and sense amplifier 8, a verify voltage generator 14 for generating a specified voltage, and a sequence control circuit. 13 and the verify voltage generator 14, and is connected to the voltage switch 1 for switching the power supply voltage applied to the row decoder 4 and the sense amplifier 8 according to the operation mode.
5. The voltage switch 15 switches the power supply voltage applied to the row decoder 4 between 5V, 13V, and 3.4V. The voltage switch 15 also switches the power supply voltage applied to the sense amplifier 8 between 5V and 3.4V.

The sequence control circuit 13 is connected to the command signal latch 12, and includes an address counter 16 and a command signal latch for sequentially generating addresses of the target memory and providing them to the address buffer 6 when erasing the stored contents of the memory array 1. 12, is connected to the address counter 16 and sense amplifier 8, and is used to confirm erasing and erasing status (hereinafter referred to as "
(referred to as "erase verify") sequence control circuit 13
and an erase/erase verify control circuit 17 for controlling the operation of the source line switch. 3, an erase pulse generator 19 for supplying the erase pulse to the mode control circuit 10 and the erase/
and a decoder control circuit 10 connected to an erase verify control circuit 17 .

The following describes the operation of nonvolatile semiconductor memory devices.
The explanation will be given in the order of successive addition and deletion.

(1) Write operation When data is written to the memory cell MCI shown in FIGS. 10 and 11, the nonvolatile semiconductor memory device operates as follows. The write circuit 7 is activated,
High voltage vpp is applied to I10 line 27. Column decoder 5 connects bit line B to which memory cell MCI is connected.
To select LI, transistor 26a is turned on. Column decoder 5 therefore boosts its output Yl to high voltage Vp1). Output Y2 of column decoder 5,
Y3 is kept at L level. Row decoder 4 selects word line WL1 connected to memory cell MCI, and boosts the level of word line WL1 to high voltage VppWL. The source line switch 3 grounds the source line 28. As a result, the drain 22 of the memory cell MCI has a high voltage Vpp.
A high voltage VppWL is applied to BL and the control gate 20, and the source 23 is grounded.

As a result, a current flows between the drain 22 and the source 23. By setting the channel structure so that a high electric field is generated near the drain 22, hot electrons are generated near the drain 22 due to an avalanche phenomenon. Most of the generated hot electrons flow to the drain 22. However, some hot electrons are absorbed by the high voltage Vp applied to the control gate 20.
Due to pWL, the energy gap between floating gate 21 and silicon substrate 24 is exceeded and stored in floating gate 21. As a result, the threshold value of the memory transistor of this memory cell MCI is shifted higher. It is assumed that information "0" is written in this state.

(2) Read operation When reading out the memory cell MC1 shown in FIGS. 10 and 11, the device operates as follows. Column decoder 5 selects bit line BLI to which memory cell MCI is connected. For this purpose, column decoder 5 sets its output Y1 to "H" level, and transistor 26
Turn on a. Both outputs Y2 and Y3 of the column decoder 5 are kept at "L" level.

Similarly, row decoder 4 selects word line WLI to which memory cell MCI is connected, and sets its level to "H" level. The row decoder 4 is connected to other word lines WL2 and WL.
3 is kept at "L" level.

The source line switch 3 grounds the source line 28. Therefore, source lines SL1 to SL3 are also at ground potential.

It is assumed that information "0" is written in memory cell MCI in advance. In this case, the threshold value of the memory transistor of memory cell MCI is high. “H” to the control gate 20
``The memory transistor does not conduct even if a level is applied. No current flows from the bit line BLI to the source line SLI.

It is assumed that memory cell MCI is in an erased state.

Memory transistors have low thresholds. Therefore, when an "H" level voltage is applied from word line WL1 to control gate 20, the memory transistor becomes conductive.

A current flows from the bit line BLI to the source line SL1 via the memory transistor. Therefore, word line WL1
When an "H" level voltage is applied to the control gate 20, the sense amplifier 8 detects whether or not a current flows through this memory cell, so that the information stored in the memory cell MC1 becomes "0". It is determined whether the value is "1" or "1".

(3) Erasing operation During the erasing operation, high voltage Vpp5L is applied to the sources 23 of all memory cells by the source line switch 3. All control gates 20 are grounded. The drains 22 of all memory cells are kept floating. That is, all of the outputs of column decoder 5 and column decoder 4 are set to "L".

A strong electric field is induced in the oxide film between floating gate 21 and source 23. Due to the tunneling phenomenon caused by this strong electric field, electrons are extracted from the floating gate 21 to the source 23. As a result, the threshold voltage of the memory transistor of the memory cell becomes lower.

Source line SLI of all memory cells of memory array 1
~SL3 are connected to a common source line 28. Therefore, data is erased in all memory cells of memory array 1 at once.

In the following description, the ``H'' level refers to the power supply voltage (5V) or so, and the ``L'' level refers to the ground potential.

By the way, due to the manufacturing process of semiconductor memory devices, variations occur in the characteristics of the devices. This variation may cause some memory cells to be easily erased and some memory cells to be less likely to be erased. If the erase pulse is set according to memory cells that are easily erased, those that are difficult to erase will remain unerased.

On the other hand, if the erase pulse is set according to what is difficult to erase, there is a risk that electrons will be extracted excessively from the floating gate of a memory cell that is easy to erase, and this memory cell will become depressed.

When an unselected memory cell is in a depletion state during successive selection, a current flows not only in the selected memory cell but also in the depleted unselected memory cell. A malfunction occurs in the fruiting device. Furthermore, even during so-called programming, in which data is written to each memory cell of the memory array 1, current flows to unselected cells that are in a depleted state. As a result, programming becomes impossible. In order to avoid such troubles, the following steps are taken when erasing memory cells.

In the erase mode, all memory cells are first written, and the threshold values of the memory transistors of all memory cells are raised. Address counter 16 sequentially generates address signals and supplies them to address buffer 6 in order to write to all memory cells of memory array 1 . The row decoder 4, column decoder 5, and write circuit 7 are erase/
It is controlled by erase verify control circuit 17 and writes to all memory cells of memory array 1.

After writing to all memory cells is completed, an erase/erase verify operation is started. First, a high voltage is applied to the sources of all memory cells by the source line switch 3. All word lines WL1-WL3 are grounded. As a result, all memory cells of memory array 1 are erased. Application of high voltage to the source by the source line switch 3 is carried out for a fixed period of time, for example, 10 m5. The source line 2 is set by the source line switch 3.
This potential change applied to 8 is called an erase pulse.

Thereafter, an erase verify operation is performed on memory array 1. Erase verify operation refers to memory array 1
The task is to check whether data has been erased from all memory cells. Address counter 16 sequentially generates address signals to select all memory cells and supplies them to address buffer 76 . Each memory cell of memory array 1 is sequentially selected by row decoder 4 and column decoder 5. The sense amplifier 8 amplifies the a power from this memory cell and supplies it to the erase/erase verify control circuit 17. Erase/erase verify control circuit 17
When it finds a memory cell with a high threshold, it stops the verify operation and repeats the erase operation. When it is determined that the threshold values of all memory cells have become low, the erase/erase verify control circuit 17 ends the erase/erase verify operation. When this erase operation is completed, the status signal output from the command signal latch 12 becomes "H" level.

By repeating the above erase/erase verify operation, the threshold values of the memory transistors of all memory cells are shifted to around Ov. Electrons are extracted from the floating gate of each memory cell in small amounts. Therefore, each memory cell never becomes depressed.

[Problems to be Solved by the Invention] In the conventional nonvolatile semiconductor memory device, the erase/erase verify operation is performed as described above. Therefore, there were the following problems. Depending on the manufacturing process of a nonvolatile semiconductor memory device, variations within each chip may be small, but variations between chips may become large.

At this time, it is difficult to uniquely determine the optimal values of the pulse width and pulse voltage of the erase pulse so that data can be efficiently erased for all chips. Further, if the erase pulse width is reduced, depletion of the memory cell becomes less likely to occur, but the number of erase confirmations after the erase pulse increases. As a result, there were problems such as an increase in the time required to complete erasing.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a nonvolatile semiconductor memory device that can erase data in a short time and appropriately.

[Means for Solving the Problems] A nonvolatile semiconductor storage device according to the present invention includes a nonvolatile semiconductor storage means including a storage area in which data can be electrically rewritten, and a method for erasing data stored in the nonvolatile semiconductor storage means. The erase pulse generating means includes an erase pulse generating means for generating an erase pulse for erasing, and a pulse waveform setting means for arbitrarily setting the waveform of the erase pulse.

[Operation] In the nonvolatile semiconductor memory device according to the present invention, the waveform of the erase pulse such as the voltage value and pulse width of the erase pulse for erasing data stored in the memory cells can be set externally. Therefore, if the variation in ease of erasing of each memory cell within a chip is small, data can be appropriately erased in a short time by setting the waveform of the erase pulse optimally. In addition, since the erase pulse width can be set for each chip, if there are large variations between chips, an appropriate erase pulse waveform can be set for each chip, and data can be erased appropriately for all chips in a short time. be able to.

[Example code] An embodiment of the present invention will be described below with reference to the drawings.

The overall structure of the nonvolatile semiconductor memory device according to the present invention is similar to the conventional one shown in FIGS. 9 to 12. However, as shown in FIG. 1, the erase pulse generator 19 used in the erase control circuit 11 of the nonvolatile semiconductor memory device according to the present invention has the same pulse width as the erase pulse, An erase time setting circuit 50 for outputting an erase time setting pulse Terase having a voltage of a fixed voltage and a fixed voltage, and an external high voltage Vp from the outside.
is given, and in response to the erase time setting pulse Terase, the erase time setting circuit 50 is set at the same voltage as the external Vp.
a high-voltage switch circuit 53 for outputting a high-voltage erase pulse Vp having an erase pulse width set by a high-voltage erase pulse Vp; and an erase pulse whose voltage is set to the optimum voltage for chip erasing when the high-voltage erase pulse Vp is applied. and a voltage trimming circuit 55 for outputting 1ntVpp.

Referring to FIG. 2, erasure time setting circuit 50 includes an oscillator 70 for oscillating a pulse having a constant frequency, a plurality of frequency dividers 71a connected in series to the output of oscillator 70,
71b, -..., 71c, the oscillator 70, and each frequency divider 71
NOR gate 74 whose input is connected to the outputs of a to 71c
and a fuse 72 for cutting each signal line, which is provided for each of the input lines 75a to 75d of the NOR gate 74.
a to 72d, and pull-down resistors 73a to 73d for connecting each signal line 75a to 75d between the fuses 72a to 72d and the NOR gate 74 to the ground potential.

The oscillator 70 and frequency dividers 71a to 71c constitute a binary counter.

Referring to FIG. 3, the high voltage switch circuit 53 has a source connected to the output of the erase time setting circuit 50 and a gate connected to the power supply voltage V.
cc, a p-channel transistor 61 whose source was connected to a high voltage external Vp, whose drain was connected to a node 66 at the contact point with the drain of the transistor 63, and whose gate was commonly connected to the node 66. p
Channel transistor 64 and n-channel transistor 6
5. The source of p-channel transistor 64 is connected to external Vp. The drain of N-channel transistor 65 is connected to ground potential. The drain of p-channel transistor 64 and the drain of n-channel transistor 65 are connected and serve as an output of high voltage switch circuit 53. The output of high voltage switch circuit 53 is connected to the gate of p-channel transistor 61.

A circuit consisting of a p-channel transistor 6L64 and an n-channel transistor 65 is a high voltage switch circuit 53.
In response to the erase time setting pulse Terase input to
). The transistor 63 is
This is for isolating the erase time setting circuit 50 from the high voltage external Vp. Power supply voltage Vcc is applied to the gate of transistor 63. The potential of the drain of the transistor 63 rises only to "gate voltage - threshold voltage". Therefore, external Vp is cut by transistor 63.

Referring to FIG. 4, voltage trimming circuit 55 includes fuse 31 provided between input terminal 35 and output terminal 36.
a, three resistors 30a connected in series in this order between the contact between the input terminal 35 and the fuse 31a, and the ground potential.
, 30b, 30c, a fuse 31b provided between the contacts of the resistors 30a, 30b, and the output terminal 36, and the resistor 3
It includes a fuse 31c provided between the contacts 0b and 30c and the output terminal 36.

The voltage trimming circuit 55 shown in FIG.
By leaving any one of the fuses 31a, 31b, and 31c and cutting the other fuses, the resistor 30a
, 30b, 30c, a suitable voltage is obtained. As a result, the voltage of the erase pulse 1ntVpp output from the voltage trimming circuit 55 can be adjusted to an appropriate level after the chip is fabricated.

The operation of the erase pulse generator 19 of a nonvolatile semiconductor memory device according to an embodiment of the present invention will be explained with reference to FIGS. 1 to 6. Referring to FIGS. 2 and 5(a), an oscillator 70 oscillates a clock having a constant frequency. Fifth
Referring to FIG. 7B, frequency divider 71a divides the frequency of the clock oscillated by oscillator 70 and provides a signal with half the number of pulses to NOR gate 74. Referring to FIG. 5(C),
The divider 71b further divides the frequency of the output of the divider 71a and supplies the NOR gate 74 with a signal having one-fourth the number of pulses of the clock oscillated by the oscillator 70. Furthermore, the fifth
Referring to FIG. 7D, frequency divider 71C divides the output of frequency divider 71b and provides NOR gate 74 with a signal having one-eighth the number of pulses of the clock oscillated by oscillator 70.

By leaving one of the fuses 72a to 72d and cutting the other fuses, the pulse output by the NOR gate 74 is the same as the pulse input through the remaining fuse.

For example, referring to FIG. 6, it is assumed that only fuse 72c is left and the other fuses 72a, 72b, and 72d are cut. Referring to FIGS. 6(a), (b) and (d), NOR from the oscillator 70, frequency divider 71a1 and frequency divider 71c
There is no pulse input to the gate 74, and the input cuffs 5a, 75b, 75d of the NOR gate 74 are always at the "L" level.

On the other hand, the input from frequency divider 71b is applied to NOR gate 74 as shown in FIG. 6(C).

Therefore, the output of the NOR gate 74 is an inverted version of the output waveform of the divider 71b, as shown in FIG. 6(e).

Referring to FIG. 3, the high voltage switch circuit 53 receives an erase time setting pulse Ter which is the output of the erase time setting circuit 50.
ase is input. Erase time setting pulse Terase
is at “H” level, N-channel transistor 6
5 starts to turn on. Therefore, the high voltage switch circuit 53
The potential of the high voltage erasing pulse Vp outputted by starts to become "L".

However, the erase time setting pulse Terase has a normal amplitude. Therefore, the p-channel transistor 64 whose source is connected to the high voltage 11Vp cannot be turned on completely. A through current flows between the external Vp and the ground potential. Therefore, p-channel transistor 64 and n
The potential of the contact point with the channel transistor 65 is also completely “L”.
In this case, the output of the high voltage switch circuit 53 becomes unstable, which is not desirable.

Therefore, the output of the high voltage switch circuit 53 is applied to the gate of the p-channel transistor 61. When the output of the high voltage switch circuit 53 drops to a certain extent, the node 66 becomes the external Vp potential through the p-channel transistor 61. The potential of the gate of the p-channel transistor 64 is
p, so the p-channel transistor 64 is completely turned off.

Therefore, the potential of the high voltage erase pulse Vp output from the high voltage switch circuit 53 becomes completely "L" level.

On the other hand, when the erase time setting pulse Terese inputted to the transistor 63 is at "L" level, the p-channel transistor 64 is turned on and the n-channel transistor 65 is turned off. Therefore, the potential of the high voltage erase pulse Vp output from the high voltage switch circuit 53 becomes the potential of the external Vp.

In this way, by controlling the high voltage switch circuit 53 using the erase time setting pulse Terase, the high voltage switch circuit 53 outputs a pulse having a pulse width specified by the erase time setting circuit 50 and specified by the external Vp. A high voltage erase pulse Vp having an amplitude is output.

Referring to FIG. 4, voltage trimming circuit 55 adjusts the voltage of high voltage erase pulse Vp applied to input terminal 35 to the voltage set by fuses 31a to 31c. As a result, the voltage of the erase pulse 1ntVpp outputted from the voltage trimming circuit 55 becomes a signal having the optimal pulse width and voltage for erasing data in the nonvolatile semiconductor memory device.

As described above, after manufacturing the nonvolatile semiconductor memory device, the pulse width of the erase pulse can be adjusted by the erase time setting circuit 50. Further, the voltage of the erase pulse can be adjusted by the voltage trimming circuit 55. Therefore, the pulse width and voltage of the erase pulse can be set for each chip so that data can be erased appropriately in a short time.

FIG. 7 is a circuit diagram showing another example of the voltage trimming circuit 55. Referring to FIG. 7, this voltage trimming circuit 55 includes three resistors 30a% 30b% 30c connected in series between the input terminal 35 and the output terminal 36,
A connecting wire is provided in parallel with each of the resistors 30a, 3b, and 30c to short-circuit both ends of each resistor, and three fuses 31a, 3lb, and 31 are provided on each of the connecting wires.
c.

In this voltage trimming circuit 55, the fuse 31
Every time one of the fuses a, 31b, and 31c is cut, the voltage of the erase pulse 1ntvpp that is output becomes lower due to the voltage drop due to the resistance provided in parallel with the cut fuse. Therefore, until the erase pulse voltage becomes appropriate, the fuses 31a, 3lb, 31c
By cutting off the voltage, a pulse voltage that can appropriately erase data from the nonvolatile semiconductor memory device can be obtained.

FIG. 8 is a block diagram of another example of the erase pulse generation circuit 19 used in the nonvolatile semiconductor memory device according to the present invention. Referring to FIG. 8, the circuit 19 includes an erase time setting circuit 50 for generating an erase time setting pulse Terase having the same pulse width as the erase pulse and an amplitude of the normal voltage, and a high voltage A voltage trimming circuit 55 receives an external Vp and adjusts the voltage of the external Vp to a voltage appropriate for erasing data, and a voltage trimming circuit 55 adjusts the appropriate voltage set by the voltage trimming circuit 55 in response to an erase time setting pulse Terase. Erasing pulse 1ntVp with
and a high voltage switch circuit 53 for outputting p.

The erase time setting circuit 50, high voltage switch circuit 53, and voltage trimming circuit 55 are shown in FIGS. 2, 3, and 4, respectively.
It has the same configuration as the erase time setting circuit 50, high voltage switch circuit 53, and voltage trimming circuit 55 shown in the figure.

By using an erase pulse generator 19 as shown in FIG. 8, it is also possible to obtain an erase pulse for appropriately erasing data in a nonvolatile semiconductor memory device.

That is, according to the present invention, even after manufacturing a nonvolatile semiconductor memory device, an appropriate erase pulse width can be set for each chip by the erase time setting circuit 50,
Furthermore, the erase pulse voltage can be adjusted for each chip by the voltage trimming circuit 55. Therefore, it is possible to obtain an erase pulse that can erase data most appropriately and in a short time for each chip.

The present invention has been described above based on the above-mentioned embodiments.

However, this invention is not limited to the above-mentioned embodiments,
It is also possible to implement various other modifications.

[Effects of the Invention] As described above, according to the present invention, the voltage value, pulse width, and other waveforms of the erase pulse for erasing the contents stored in the memory cells of a nonvolatile semiconductor memory device can be controlled from the outside after the chip is fabricated. Can be set.

Therefore, even if the waveform of the erasing pulse most suitable for erasing data varies greatly between chips, the most suitable erasing pulse can be selected for each chip. There is no need to erase data with an unreasonably low erase pulse voltage or an unreasonably short pulse width to deal with chip-to-chip variations as in the past, and the time it takes to erase data is much shorter, while reducing depletion. There is no fear that a memory cell will occur.

That is, it is possible to provide a nonvolatile semiconductor memory device that can appropriately erase data on a chip-by-chip basis in a short period of time.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an erase pulse generator for a nonvolatile semiconductor memory device according to the present invention, and FIG. 2 is a circuit block diagram of an erase time setting circuit for a nonvolatile semiconductor memory device according to the present invention. 3 is a circuit diagram of the high voltage switch circuit, FIG. 4 is a circuit diagram of the voltage trimming circuit, FIG. 5 is a waveform diagram showing the operation of the erase time setting circuit 50, and FIG. 6 is a circuit diagram of the voltage trimming circuit. 8 is a waveform diagram showing the pulse width setting by the erase time setting circuit; FIG. 7 is a circuit diagram of a voltage trimming circuit used in a nonvolatile semiconductor memory device according to another embodiment of the present invention; FIG. is a block diagram of an erase pulse generation circuit of another embodiment of the nonvolatile semiconductor memory device according to the present invention, FIG. 9 is a block diagram of the nonvolatile semiconductor memory device, and FIG. 10 is a block diagram of the nonvolatile semiconductor memory device. FIG. 11 is a schematic cross-sectional structure diagram of a memory cell, and FIG. 12 is a block diagram of an erase control circuit. In the figure, 1 is a memory array, 11 is an erase control circuit, 13 is a sequence control circuit, 16 is an address counter, 17 is an erase/erase verify control circuit, 19 is an erase pulse generator, 50 is an erase time setting circuit, and 53 is a A high voltage switch circuit, 55 indicates a voltage trimming circuit. Note that the same reference numerals in the figures indicate the same or equivalent parts.萬19 Figure 2/s. Figure 5 (e) Figure 3 Channel 4 Figure 9 Figure 11 Figure 8/Revised Figure 9 Figure 11 Figure 22 Nidrein@be

Claims (1)

[Claims] (1) A nonvolatile semiconductor memory device in which data can be electrically rewritten, comprising a nonvolatile semiconductor storage means including a storage area in which data can be electrically rewritten, and data stored in the nonvolatile semiconductor storage means. A nonvolatile semiconductor memory device comprising: an erase pulse generating means for generating an erase pulse for erasing the erase pulse; and a pulse waveform setting means for arbitrarily setting the waveform of the erase pulse.