JPH03291693A - Dot matrix type display device - Google Patents

Abstract

PURPOSE:To automatize the switching of a display mode by analyzing a synchronous signal, identifying the display mode of a video signal, and generating the synchronizing signal and a dot clock according to the identified display mode. CONSTITUTION:A display mode selecting means 5 identifies the type of the video signal based on the output of a synchronous signal analyzing circuit 4, and the synchronous signal having a period corresponding to the display mode selected based on an instruction from the display mode selecting means 5, and similarly, a dot clock generating circuit 7 generates a dot clock DCK having a period corresponding to the display mode. Therefore, the display mode can be switched corresponding to a signal inputted into a display device. Thus, the display mode can be automatically switched.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a dot matrix type display device that displays video signals output from a personal computer, etc., and particularly relates to a dot matrix type display device that displays video signals output from a personal computer, etc. The present invention relates to a dot matrix display device that can automatically switch display modes by determining

(Prior Art) Display devices are known that are equipped with a display mode selection switch and the like and can display various video signals by manually setting the display mode.

(Problem to be Solved by the Invention) However, in a display device connected to a personal computer that can switch between multiple display modes using software, the mode must be manually switched each time the display mode is switched. However, this operation is extremely troublesome.

The present invention has been made to solve the above problems, and its purpose is to provide a display device that can identify the type of video signal and automatically switch the display mode.

(Means for Solving the Problems) In order to solve the above problems, a dot matrix type display device according to the present invention provides a synchronization system that measures and outputs the period and polarity of a synchronization signal and the number of horizontal synchronization signals within a vertical synchronization period. a signal analysis means; a display mode selection means for selecting a corresponding display mode from among a plurality of preset display modes based on the output of the synchronization signal analysis means; The present invention is characterized by comprising a synchronizing signal generating means for generating a synchronizing signal and a dot clock generating means for generating a dot clock corresponding to a selected display mode.

(Operation) The display mode selection means identifies the type of video signal based on the output of the synchronization signal analysis means. The synchronization signal generation means is
A synchronizing signal having a period corresponding to the display mode selected based on the command from the display mode selection means is generated, and similarly, the dot clock generating means generates a dot clock having a period corresponding to the display mode. Therefore, the display mode can be automatically switched in accordance with a signal input manually to this display device.

(Example) Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a block diagram of a dot matrix type display device according to the present invention.

A dot matrix type display device (hereinafter referred to as a display device) 1 includes an input terminal 2 for a video signal and input terminals 3a and 3b for horizontal and vertical synchronizing signals. Horizontal synchronization signal HI and vertical synchronization signal V manually input from horizontal synchronization signal input terminal 2a and vertical synchronization signal input terminal 2b
I is input to the synchronization signal analysis circuit 4.

This synchronizing signal analysis circuit 4 is configured to measure the period and polarity of the horizontal synchronizing signal HI and vertical synchronizing signal VI, and the number of horizontal synchronizing signals included between one vertical interval signal. The results measured by the synchronization signal analysis circuit 4 are sent to the display mode selection means 5 via the signal line 4a.

The display mode selection means 5 includes a CPU 5a and a storage means 5b.
It consists of The CPU 5a refers to a plurality of display mode determination tables stored in advance in the storage means, determines the type of video signal currently being input, and determines the display mode.

FIG. 2 is a flowchart showing the procedure for determining the display mode.

This flowchart shows a case where the number of determination tables is five. The CPU 5a checks the period of the horizontal synchronizing signal, the number of horizontal synchronizing signals, the polarity of the horizontal synchronizing signal, and the polarity of the vertical synchronizing signal, and determines the display mode.

Then, the CPU 5a sends control information VC to the vertical synchronization generation circuit 6 to generate a vertical synchronization signal corresponding to the determined display mode. At the same time, the CPU 5a determines the frequency of the dot clock necessary to perform the display corresponding to the determined display mode, and sends control information DC to the dot clock generation circuit 7.

The dot clock generation circuit 7 sends a corresponding dot clock DCK to the display unit control circuit 8 based on the control information DC.

Further, the CPU 5a sends control information MC to the display unit control circuit 8 to cause it to perform an operation corresponding to the determined display mode. Based on the determined display mode, the display unit control circuit 8 outputs the video signal S input from the video signal input terminal 1, the horizontal synchronization signal HM output from the synchronization signal analysis means 4, and the vertical synchronization generation circuit 6.
The display unit 9 is driven by the vertical synchronizing signal VM generated by the vertical synchronizing signal VM to display video signal information.

In addition, the CPU 5a constantly monitors the information of the synchronization signal analysis circuit 4, and the horizontal synchronization signal H supplied from a personal computer etc.
I. When a change occurs in the vertical synchronization signal VI, the corresponding display mode is immediately determined, and the new display mode is assigned to the vertical synchronization generation circuit 6, dot clock generation circuit 7, and display unit control circuit 8 as described above. Make the transition to .

Next, a specific example of the synchronization signal analysis circuit will be described.

- 6 - FIG. 3 is a block diagram of the synchronizing signal analysis means, and FIG. 4 is a time chart showing the operation of the circuit.

The synchronous signal analysis circuit 4 includes counters 41, 42, 43, and D.
It consists of type flip-flops (hereinafter referred to as F/F) 44, 45 and various gate circuits, etc., and each counter 41,
42 and 43 are configured to be reset by a counter reset signal R8 outputted to the output port 01 of the CPU 5a.

The vertical synchronization signal VI input to the input terminal 3b is the F/F
44, and the Q output 44b of this F/F 44 alternately changes between H level and L level in synchronization with the vertical synchronization signal VI, as shown in FIG. 4(d). Repeat. Q output 44b of this F/F 44
is applied to one input terminal of the AND circuit 46. The other input terminal of the AND circuit 46 receives a reference clock signal C supplied from a reference clock generation circuit (not shown).
LK is applied. The output of the AND circuit 46 is applied to the clock input terminal 42a of the counter 42,
This counter 42 is configured to measure the period of the vertical synchronization signal VI.

The NQ output 44c of the F/F 44 is connected to the D input terminal 45c of the F/F 45, and the horizontal synchronization signal HI input to the input terminal 3a is applied to the clock input terminal of the F/F 45. ing. Therefore, as shown in FIG. 4(e), the Q output 45b of the F/F 45 has a
A signal obtained by delaying the NQ output 44C of 44 by I horizontal synchronizing signal is output.

And Q output 44b of each F/F 44, 45.

45b is input to the AND circuit 47, and the output 47a of the AND circuit 47 is configured to obtain an H level output only during one horizontal synchronization period from the time when the vertical synchronization signal rises. This output 47a is connected to one input terminal of the AND circuit 48, and the reference clock CLK is applied to the other input terminal, so that the reference clock signal CLK is applied only during one horizontal synchronization period.
LK is supplied to the clock input terminal 41a of the counter 41, and the counter measures the period of the horizontal synchronizing signal HI.

In addition, the AND circuit 49 obtains an AND output of the Q output 44b and the horizontal synchronization signal HI, and supplies the output to the clock input terminal 43a of the counter 43, thereby generating a horizontal synchronization signal during one vertical synchronization period. The counter 43 is configured to measure the number of .

The horizontal synchronizing signal HI is applied to the input terminal 52a of a waveform shaping circuit 52 such as a Schmitt trigger circuit through a time constant circuit consisting of a resistor 50 and five capacitors, and the waveform-shaped output 52b is sent to the input port 52 of the CPU 5b. 1. Similarly, the vertical synchronization signal
5 to the input port 2 of the CPU 5a.

Then, the Q output 44b of the F/F 44 changes from H level to L level.
When the level changes, an interrupt is generated to the CPU 5a, and this interrupt causes the CPU 5a to read the counter value of each counter 414243 via the bus 56. Further, the CPU 5a determines the polarity of each synchronizing signal HI, VI by paying attention to the time difference between the H level and L level of each signal input manually to the input ports Pi, P2.

Next, a specific example of the vertical synchronization signal generation circuit will be explained with reference to the block diagram shown in FIG. 5 and the time chart shown in FIG. 6.

The vertical synchronization signal generation circuit 6 includes first and second preset counters 61 and 62, a D-type F/F 63, a set-reset type F/F 64, and an AND circuit 65.

F/
The Q output 63a of the F 63 alternately repeats H level and L level, as shown in FIG. 6(C). Q output 63a of F/F 63 is applied to one input terminal of AND circuit 65. A horizontal synchronizing signal VI is applied to the other input terminal of the AND circuit 65. Output E6 of AND circuit 65
5a are connected to clock input terminals 61a and 62a of each preset counter 61 and 62, respectively. Each preset counter 61, 62 is controlled by the CPU when not counting.
5a, the preset value is preset.

Then, the F/F 64 is set using the output of the preset counter 61, and the F/F 64 is set using the output of the preset counter 62CY.
64 is reset to obtain a new vertical synchronization signal VM at the Q output 64a of the F/F 64.

Therefore, when a predetermined number of pulses are input, first
The CY output 61b of the preset counter 61 becomes H level and sets the F/F 64, and the second preset counter 62 continues counting until the CY output reaches the preset count. Level F/
Reset F64. Therefore, it is possible to obtain a new vertical synchronization signal VM that has a preset delay time and continues for a certain period of time.

Next, a specific example of the dot clock generation circuit will be explained with reference to the block diagram shown in FIG.

The dot clock generation circuit 7 includes voltage controlled oscillation circuits 71 to 74 each having a different oscillation frequency range, and a CPU 5.
Voltage controlled oscillation circuit 71 that operates based on the designation from a.
-74 is provided. The oscillation output cuffs 1a to 74a of the respective voltage controlled oscillation circuits 71 to 74 are supplied via a NAND circuit 76 as a head clock DCK to the display unit control circuit 8.

The display unit control circuit 8 controls one of the voltage controlled oscillation circuits 71 to 74 using a PLL circuit (not shown) and a prescaler, which are controlled by the CPU 5a, to obtain a stable dot clock DCK.

(Effects of the Invention) As explained above, the dot matrix type display device according to the present invention analyzes the synchronization signal, identifies the display mode of the video signal input to the display device, and outputs the synchronization signal according to the display mode of the video signal input to the display device. Since the display mode is configured to generate a dot clock and a dot clock, the display mode can be automatically switched without performing a manual switching operation.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a dot matrix type display device according to the present invention, Fig. 2 is a flowchart showing the display mode determination procedure, Fig. 3 is a block diagram of a synchronization signal analysis circuit, and Fig. 4 is a synchronization signal analysis circuit. A time chart showing the operation of the signal analysis circuit, FIG. 5 is an example block diagram of the vertical synchronization signal generation circuit, FIG. 6 is a time chart showing the operation of the vertical synchronization signal generation circuit, and FIG. 7 is an example of the dot clock generation circuit. FIG. 2 is a block configuration diagram. DESCRIPTION OF SYMBOLS 1... Dot matrix type display device, 4... Synchronization signal analysis circuit, 5... Display mode selection means, 5a...
・CPU, 5b... Storage means, 6... Vertical synchronization signal generation circuit, 7... Dot clock generation circuit, 8...
Display unit control circuit, 9...Display unit.

Claims (1)

[Claims] In a dot matrix display device that displays a video signal, there is provided a synchronization signal analysis means for measuring and outputting the period and polarity of a synchronization signal and the number of horizontal synchronization signals within a vertical synchronization period, and a synchronization signal analysis means based on the output of the synchronization signal analysis means. display mode selection means for selecting a corresponding display mode from a plurality of preset display modes; synchronization signal generation means for generating a synchronization signal with a cycle corresponding to the selected display mode; 1. A dot matrix type display device comprising: dot clock generating means for generating a dot clock corresponding to a display mode.